dt-bindings: mediatek: Add smi dts binding
This patch add smi binding document and smi local arbiter header file. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>hifive-unleashed-5.1
Yong Wu
Joerg Roedel
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120399ba66
commit
fb6e2ceee3
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SMI (Smart Multimedia Interface) Common
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The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Required properties:
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- compatible : must be "mediatek,mt8173-smi-common"
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- reg : the register and size of the SMI block.
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- power-domains : a phandle to the power domain of this local arbiter.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : must contain 2 entries, as follows:
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- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
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the register.
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- "smi" : It's the clock for transfer data and command.
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They may be the same if both source clocks are the same.
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Example:
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smi_common: smi@14022000 {
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compatible = "mediatek,mt8173-smi-common";
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reg = <0 0x14022000 0 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_SMI_COMMON>,
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<&mmsys CLK_MM_SMI_COMMON>;
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clock-names = "apb", "smi";
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};
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SMI (Smart Multimedia Interface) Local Arbiter
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The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Required properties:
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- compatible : must be "mediatek,mt8173-smi-larb"
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- reg : the register and size of this local arbiter.
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- mediatek,smi : a phandle to the smi_common node.
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- power-domains : a phandle to the power domain of this local arbiter.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names: must contain 2 entries, as follows:
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- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
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the register.
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- "smi" : It's the clock for transfer data and command.
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Example:
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larb1: larb@16010000 {
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compatible = "mediatek,mt8173-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&vdecsys CLK_VDEC_CKEN>,
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<&vdecsys CLK_VDEC_LARB_CKEN>;
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clock-names = "apb", "smi";
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};
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/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DTS_IOMMU_PORT_MT8173_H
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#define __DTS_IOMMU_PORT_MT8173_H
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#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
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/* Local arbiter ID */
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#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x7)
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/* PortID within the local arbiter */
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#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
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#define M4U_LARB0_ID 0
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#define M4U_LARB1_ID 1
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#define M4U_LARB2_ID 2
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#define M4U_LARB3_ID 3
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#define M4U_LARB4_ID 4
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#define M4U_LARB5_ID 5
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/* larb0 */
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#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
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#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
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#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
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#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
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#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
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#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
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#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
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#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
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/* larb1 */
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#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
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#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
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#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
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#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
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#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
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#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
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#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
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#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7)
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#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
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#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9)
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/* larb2 */
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#define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0)
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#define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1)
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#define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2)
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#define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3)
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#define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4)
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#define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5)
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#define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6)
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#define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7)
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#define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8)
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#define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9)
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#define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10)
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#define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11)
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#define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12)
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#define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13)
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#define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14)
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#define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15)
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#define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16)
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#define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17)
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#define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18)
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#define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19)
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#define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20)
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/* larb3 */
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#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
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#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
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#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
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#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
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#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
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#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5)
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#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6)
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#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7)
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#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8)
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#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9)
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#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10)
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#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11)
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#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12)
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#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13)
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#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14)
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/* larb4 */
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#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0)
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#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1)
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#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2)
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#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3)
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#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4)
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#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5)
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/* larb5 */
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#define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0)
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#define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1)
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#define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2)
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#define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3)
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#define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4)
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#define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5)
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#define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6)
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#define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7)
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#define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8)
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#endif
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