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net: ipa: share field mask values for GSI general interrupt

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The GSI general interrupt is managed by three registers: enable;
status; and clear.  The three registers have same set of field bits
at the same locations.  Use a common set of field masks for all
three registers to avoid duplication.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alex Elder 2020-09-28 18:04:43 -05:00 committed by David S. Miller
parent d61bb7166d
commit fb980ef741
2 changed files with 7 additions and 16 deletions
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2
drivers/net/ipa/gsi.c
View file

@ -271,7 +271,7 @@ static void gsi_irq_enable(struct gsi *gsi)
iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);
/* Never enable GSI_BREAK_POINT */
val = GSI_CNTXT_GSI_IRQ_ALL & ~EN_BREAK_POINT_FMASK;
val = GSI_CNTXT_GSI_IRQ_ALL & ~BREAK_POINT_FMASK;
iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
}

21
drivers/net/ipa/gsi_reg.h
View file

@ -340,29 +340,20 @@
GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \
(0x0001f118 + 0x4000 * (ee))
#define BREAK_POINT_FMASK GENMASK(0, 0)
#define BUS_ERROR_FMASK GENMASK(1, 1)
#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \
(0x0001f120 + 0x4000 * (ee))
#define EN_BREAK_POINT_FMASK GENMASK(0, 0)
#define EN_BUS_ERROR_FMASK GENMASK(1, 1)
#define EN_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
#define EN_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
#define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0)
#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \
(0x0001f128 + 0x4000 * (ee))
#define CLR_BREAK_POINT_FMASK GENMASK(0, 0)
#define CLR_BUS_ERROR_FMASK GENMASK(1, 1)
#define CLR_CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
#define CLR_MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
/* The masks below are used for the general IRQ STTS, EN, and CLR registers */
#define BREAK_POINT_FMASK GENMASK(0, 0)
#define BUS_ERROR_FMASK GENMASK(1, 1)
#define CMD_FIFO_OVRFLOW_FMASK GENMASK(2, 2)
#define MCS_STACK_OVRFLOW_FMASK GENMASK(3, 3)
#define GSI_CNTXT_GSI_IRQ_ALL GENMASK(3, 0)
#define GSI_CNTXT_INTSET_OFFSET \
GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP)