drm/i915: rip out early dp port write for gm45/ilk
It's bogus. If I've followed the history of this piece of code correctly, i.e. the initial register write with the following vblank wait, this goes all the way back to the original enabling of DP support in commita4fc5ed698
Author: Keith Packard <keithp@keithp.com> Date: Tue Apr 7 16:16:42 2009 -0700 drm/i915: Add Display Port support Unfortunately it seems to be nothing more than glorified duct-tape and sometimes actively harmful. Adam Jackson noticed this for CPT platforms with commite85194641b
Author: Adam Jackson <ajax@redhat.com> Date: Thu Jul 21 17:48:38 2011 -0400 drm/i915/dp: Don't turn CPT DP ports on too early Unfortunately this kept the code around for ilk and gm45. The specific failure case I'm seeing here is that after a dpms off/on cycle we have the bits from the last link training (hopefully successful link training) set in intel_dp->DP. This is requiered so that complete_link_train can enable the port with the right tuning values. Unfortunately writing these again to the disabled port at dpms on time kills the port somehow until it's disabled - dp link training fails in an endless loop without this patch on my mobile ilk and gm45. Cc: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51493 Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1743,25 +1743,12 @@ static void
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intel_dp_start_link_train(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
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int i;
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uint8_t voltage;
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bool clock_recovery = false;
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int voltage_tries, loop_tries;
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uint32_t DP = intel_dp->DP;
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/*
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* On CPT we have to enable the port in training pattern 1, which
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* will happen below in intel_dp_set_link_train. Otherwise, enable
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* the port and wait for it to become active.
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*/
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if (!HAS_PCH_CPT(dev)) {
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I915_WRITE(intel_dp->output_reg, intel_dp->DP);
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POSTING_READ(intel_dp->output_reg);
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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}
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/* Write the link configuration data */
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intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
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intel_dp->link_configuration,
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