drm/i915/skl: don't set the AsyncFlip performance mode for Gen9+
The following sets the AsyncFlip performance mode for everything above Gen6: commit 4790cb36b3eede8fb0cca529dc1d31b9936fa24b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sun Jan 20 16:11:20 2013 +0000 drm/i915: Disable AsyncFlip performance optimisations Starting from Gen9 the MI_MODE register layout changes and doesn't include the above bit. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -823,7 +823,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
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*
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* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
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*/
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if (INTEL_INFO(dev)->gen >= 6)
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if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
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I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
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/* Required for the hardware to program scanline values for waiting */
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