[POWERPC] Support for DCR based MPIC
This patch implements support for DCR based MPIC implementations. Such implementations have the MPIC_USES_DCR flag set and don't use the phys_addr argument of mpic_alloc (they require a valid dcr mapping in the device node) This version of the patch can use a little bif of cleanup still (I can probably consolidate rb->dbase/doff, at least once I'm sure on how the hardware is actually supposed to work vs. possible simulator issues) and it should be possible to build a DCR-only version of the driver. I need to cleanup a bit the CONFIG_* handling for that and probably introduce CONFIG_MPIC_MMIO and CONFIG_MPIC_DCR. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>hifive-unleashed-5.1
Benjamin Herrenschmidt
Paul Mackerras
parent
1be3770aa9
commit
fbf0274e43
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@ -147,33 +147,51 @@ static u32 mpic_infos[][MPIC_IDX_END] = {
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*/
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static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
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unsigned int reg)
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static inline u32 _mpic_read(enum mpic_reg_type type,
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struct mpic_reg_bank *rb,
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unsigned int reg)
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{
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if (be)
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return in_be32(base + (reg >> 2));
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else
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return in_le32(base + (reg >> 2));
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switch(type) {
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#ifdef CONFIG_PPC_DCR
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case mpic_access_dcr:
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return dcr_read(rb->dhost,
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rb->dbase + reg + rb->doff);
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#endif
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case mpic_access_mmio_be:
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return in_be32(rb->base + (reg >> 2));
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case mpic_access_mmio_le:
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default:
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return in_le32(rb->base + (reg >> 2));
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}
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}
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static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
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unsigned int reg, u32 value)
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static inline void _mpic_write(enum mpic_reg_type type,
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struct mpic_reg_bank *rb,
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unsigned int reg, u32 value)
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{
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if (be)
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out_be32(base + (reg >> 2), value);
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else
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out_le32(base + (reg >> 2), value);
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switch(type) {
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#ifdef CONFIG_PPC_DCR
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case mpic_access_dcr:
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return dcr_write(rb->dhost,
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rb->dbase + reg + rb->doff, value);
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#endif
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case mpic_access_mmio_be:
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return out_be32(rb->base + (reg >> 2), value);
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case mpic_access_mmio_le:
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default:
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return out_le32(rb->base + (reg >> 2), value);
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}
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}
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static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
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{
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unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
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enum mpic_reg_type type = mpic->reg_type;
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unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
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(ipi * MPIC_INFO(GREG_IPI_STRIDE));
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if (mpic->flags & MPIC_BROKEN_IPI)
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be = !be;
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return _mpic_read(be, mpic->gregs, offset);
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if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
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type = mpic_access_mmio_be;
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return _mpic_read(type, &mpic->gregs, offset);
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}
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static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
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@ -181,7 +199,7 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
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unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
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(ipi * MPIC_INFO(GREG_IPI_STRIDE));
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_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
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_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
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}
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static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
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@ -190,8 +208,7 @@ static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,
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mpic->cpuregs[cpu], reg);
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return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
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}
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static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
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@ -201,7 +218,7 @@ static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 valu
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if (mpic->flags & MPIC_PRIMARY)
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cpu = hard_smp_processor_id();
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_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
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_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
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}
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static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
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@ -209,7 +226,7 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
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unsigned int isu = src_no >> mpic->isu_shift;
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unsigned int idx = src_no & mpic->isu_mask;
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return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
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return _mpic_read(mpic->reg_type, &mpic->isus[isu],
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reg + (idx * MPIC_INFO(IRQ_STRIDE)));
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}
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@ -219,12 +236,12 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
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unsigned int isu = src_no >> mpic->isu_shift;
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unsigned int idx = src_no & mpic->isu_mask;
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_mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
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_mpic_write(mpic->reg_type, &mpic->isus[isu],
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reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
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}
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#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
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#define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
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#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
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#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
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#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
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#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
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#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
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@ -238,6 +255,38 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
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*/
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static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
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struct mpic_reg_bank *rb, unsigned int offset,
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unsigned int size)
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{
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rb->base = ioremap(phys_addr + offset, size);
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BUG_ON(rb->base == NULL);
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}
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#ifdef CONFIG_PPC_DCR
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static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
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unsigned int offset, unsigned int size)
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{
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rb->dbase = mpic->dcr_base;
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rb->doff = offset;
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rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size);
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BUG_ON(!DCR_MAP_OK(rb->dhost));
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}
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static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
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struct mpic_reg_bank *rb, unsigned int offset,
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unsigned int size)
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{
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if (mpic->flags & MPIC_USES_DCR)
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_mpic_map_dcr(mpic, rb, offset, size);
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else
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_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
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}
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#else /* CONFIG_PPC_DCR */
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#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
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#endif /* !CONFIG_PPC_DCR */
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/* Check if we have one of those nice broken MPICs with a flipped endian on
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* reads from IPI registers
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@ -883,6 +932,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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if (flags & MPIC_PRIMARY)
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mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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#ifdef CONFIG_SMP
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mpic->hc_ipi = mpic_ipi_chip;
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mpic->hc_ipi.typename = name;
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@ -897,11 +947,26 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
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#endif
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/* default register type */
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mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
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mpic_access_mmio_be : mpic_access_mmio_le;
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#ifdef CONFIG_PPC_DCR
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if (mpic->flags & MPIC_USES_DCR) {
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const u32 *dbasep;
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BUG_ON(mpic->of_node == NULL);
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dbasep = get_property(mpic->of_node, "dcr-reg", NULL);
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BUG_ON(dbasep == NULL);
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mpic->dcr_base = *dbasep;
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mpic->reg_type = mpic_access_dcr;
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}
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#else
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BUG_ON (mpic->flags & MPIC_USES_DCR);
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#endif /* CONFIG_PPC_DCR */
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/* Map the global registers */
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mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
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mpic->tmregs = mpic->gregs +
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((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
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BUG_ON(mpic->gregs == NULL);
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mpic_map(mpic, phys_addr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
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mpic_map(mpic, phys_addr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
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/* Reset */
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if (flags & MPIC_WANTS_RESET) {
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@ -926,17 +991,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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/* Map the per-CPU registers */
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for (i = 0; i < mpic->num_cpus; i++) {
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mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
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i * MPIC_INFO(CPU_STRIDE), 0x1000);
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BUG_ON(mpic->cpuregs[i] == NULL);
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mpic_map(mpic, phys_addr, &mpic->cpuregs[i],
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MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
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0x1000);
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}
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/* Initialize main ISU if none provided */
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if (mpic->isu_size == 0) {
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mpic->isu_size = mpic->num_sources;
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mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
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MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
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BUG_ON(mpic->isus[0] == NULL);
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mpic_map(mpic, phys_addr, &mpic->isus[0],
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MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
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}
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mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
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mpic->isu_mask = (1 << mpic->isu_shift) - 1;
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@ -979,8 +1043,8 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
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BUG_ON(isu_num >= MPIC_MAX_ISU);
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mpic->isus[isu_num] = ioremap(phys_addr,
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MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
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mpic_map(mpic, phys_addr, &mpic->isus[isu_num], 0,
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MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
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if ((isu_first + mpic->isu_size) > mpic->num_sources)
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mpic->num_sources = isu_first + mpic->isu_size;
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}
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@ -3,6 +3,7 @@
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#ifdef __KERNEL__
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#include <linux/irq.h>
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#include <asm/dcr.h>
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/*
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* Global registers
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@ -225,6 +226,23 @@ struct mpic_irq_fixup
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#endif /* CONFIG_MPIC_BROKEN_U3 */
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enum mpic_reg_type {
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mpic_access_mmio_le,
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mpic_access_mmio_be,
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#ifdef CONFIG_PPC_DCR
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mpic_access_dcr
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#endif
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};
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struct mpic_reg_bank {
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u32 __iomem *base;
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#ifdef CONFIG_PPC_DCR
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dcr_host_t dhost;
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unsigned int dbase;
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unsigned int doff;
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#endif /* CONFIG_PPC_DCR */
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};
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/* The instance data of a given MPIC */
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struct mpic
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{
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@ -264,11 +282,18 @@ struct mpic
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spinlock_t fixup_lock;
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#endif
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/* Register access method */
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enum mpic_reg_type reg_type;
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/* The various ioremap'ed bases */
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volatile u32 __iomem *gregs;
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volatile u32 __iomem *tmregs;
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volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
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volatile u32 __iomem *isus[MPIC_MAX_ISU];
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struct mpic_reg_bank gregs;
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struct mpic_reg_bank tmregs;
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struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
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struct mpic_reg_bank isus[MPIC_MAX_ISU];
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#ifdef CONFIG_PPC_DCR
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unsigned int dcr_base;
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#endif
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#ifdef CONFIG_MPIC_WEIRD
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/* Pointer to HW info array */
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@ -305,6 +330,8 @@ struct mpic
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#define MPIC_SPV_EOI 0x00000020
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/* No passthrough disable */
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#define MPIC_NO_PTHROU_DIS 0x00000040
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/* DCR based MPIC */
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#define MPIC_USES_DCR 0x00000080
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/* MPIC HW modification ID */
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#define MPIC_REGSET_MASK 0xf0000000
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