phy-sun4i-usb: Add support for the usb-phys on the sun8i-a33 SoC
The usb-phys on the sun8i-a33 SoC are mostly the same as sun8i-a23 but for some reason (hw bug?) the phyctl register was moved to a different address and is not initialized to 0 on reset. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -8,6 +8,7 @@ Required properties:
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* allwinner,sun6i-a31-usb-phy
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* allwinner,sun7i-a20-usb-phy
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* allwinner,sun8i-a23-usb-phy
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* allwinner,sun8i-a33-usb-phy
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- reg : a list of offset + length pairs
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- reg-names :
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* "phy_ctrl"
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@ -40,9 +40,10 @@
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#include <linux/workqueue.h>
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#define REG_ISCR 0x00
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#define REG_PHYCTL 0x04
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#define REG_PHYCTL_A10 0x04
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#define REG_PHYBIST 0x08
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#define REG_PHYTUNE 0x0c
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#define REG_PHYCTL_A33 0x10
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#define PHYCTL_DATA BIT(7)
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@ -90,6 +91,7 @@ struct sun4i_usb_phy_data {
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struct mutex mutex;
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int num_phys;
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u32 disc_thresh;
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bool has_a33_phyctl;
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struct sun4i_usb_phy {
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struct phy *phy;
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void __iomem *pmu;
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@ -152,37 +154,46 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
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{
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struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
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u32 temp, usbc_bit = BIT(phy->index * 2);
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void *phyctl;
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int i;
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mutex_lock(&phy_data->mutex);
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if (phy_data->has_a33_phyctl) {
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phyctl = phy_data->base + REG_PHYCTL_A33;
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/* A33 needs us to set phyctl to 0 explicitly */
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writel(0, phyctl);
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} else {
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phyctl = phy_data->base + REG_PHYCTL_A10;
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}
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for (i = 0; i < len; i++) {
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temp = readl(phy_data->base + REG_PHYCTL);
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temp = readl(phyctl);
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/* clear the address portion */
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temp &= ~(0xff << 8);
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/* set the address */
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temp |= ((addr + i) << 8);
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writel(temp, phy_data->base + REG_PHYCTL);
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writel(temp, phyctl);
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/* set the data bit and clear usbc bit*/
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temp = readb(phy_data->base + REG_PHYCTL);
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temp = readb(phyctl);
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if (data & 0x1)
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temp |= PHYCTL_DATA;
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else
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temp &= ~PHYCTL_DATA;
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temp &= ~usbc_bit;
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writeb(temp, phy_data->base + REG_PHYCTL);
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writeb(temp, phyctl);
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/* pulse usbc_bit */
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temp = readb(phy_data->base + REG_PHYCTL);
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temp = readb(phyctl);
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temp |= usbc_bit;
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writeb(temp, phy_data->base + REG_PHYCTL);
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writeb(temp, phyctl);
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temp = readb(phy_data->base + REG_PHYCTL);
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temp = readb(phyctl);
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temp &= ~usbc_bit;
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writeb(temp, phy_data->base + REG_PHYCTL);
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writeb(temp, phyctl);
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data >>= 1;
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}
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@ -443,7 +454,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
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dev_set_drvdata(dev, data);
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if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy") ||
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of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy"))
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of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
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of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
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data->num_phys = 2;
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else
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data->num_phys = 3;
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@ -455,11 +467,15 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
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data->disc_thresh = 3;
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if (of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy") ||
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of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy"))
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of_device_is_compatible(np, "allwinner,sun8i-a23-usb-phy") ||
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of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
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dedicated_clocks = true;
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else
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dedicated_clocks = false;
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if (of_device_is_compatible(np, "allwinner,sun8i-a33-usb-phy"))
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data->has_a33_phyctl = true;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
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data->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(data->base))
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@ -591,6 +607,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
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{ .compatible = "allwinner,sun6i-a31-usb-phy" },
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{ .compatible = "allwinner,sun7i-a20-usb-phy" },
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{ .compatible = "allwinner,sun8i-a23-usb-phy" },
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{ .compatible = "allwinner,sun8i-a33-usb-phy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
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