drm/i915/uc: Place uC firmware in upper range of GGTT
Currently we pin the GuC or HuC firmware image just before uploading.
Perma-pin during uC initialization instead and use the range reserved at
the top of the address space.
Moving the firmware resulted in needing to:
- use an additional pinning for the rsa signature which will be used
during HuC auth as addresses above GUC_GGTT_TOP do not map through GTT.
v2: Remove call to set to gtt domain
Do not restore fw gtt mapping unconditionally
Separate out pin/unpin functions and drop usage of pin/unpin
Use uc_fw init/fini functions to bind/unbind fw object
v3: Bind is only needed during xfer (Chris)
Remove attempts to bind outside of xfer (Chris)
Mark fw bind/unbind static
Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419230015.18121-4-fernando.pacheco@intel.com
alistair/sunxi64-5.4-dsi
Fernando Pacheco
Chris Wilson
parent
911800765e
commit
fc488b5903
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@ -189,9 +189,13 @@ int intel_guc_init(struct intel_guc *guc)
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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int ret;
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ret = guc_shared_data_create(guc);
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ret = intel_uc_fw_init(&guc->fw);
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if (ret)
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goto err_fetch;
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ret = guc_shared_data_create(guc);
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if (ret)
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goto err_fw;
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GEM_BUG_ON(!guc->shared_data);
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ret = intel_guc_log_create(&guc->log);
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@ -220,6 +224,8 @@ err_log:
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intel_guc_log_destroy(&guc->log);
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err_shared:
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guc_shared_data_destroy(guc);
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err_fw:
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intel_uc_fw_fini(&guc->fw);
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err_fetch:
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intel_uc_fw_cleanup_fetch(&guc->fw);
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return ret;
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@ -237,6 +243,7 @@ void intel_guc_fini(struct intel_guc *guc)
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intel_guc_ads_destroy(guc);
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intel_guc_log_destroy(&guc->log);
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guc_shared_data_destroy(guc);
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intel_uc_fw_fini(&guc->fw);
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intel_uc_fw_cleanup_fetch(&guc->fw);
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}
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@ -122,14 +122,16 @@ static void guc_prepare_xfer(struct intel_guc *guc)
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}
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/* Copy RSA signature from the fw image to HW for verification */
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static void guc_xfer_rsa(struct intel_guc *guc, struct i915_vma *vma)
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static void guc_xfer_rsa(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_uc_fw *fw = &guc->fw;
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struct sg_table *pages = fw->obj->mm.pages;
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u32 rsa[UOS_RSA_SCRATCH_COUNT];
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int i;
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sg_pcopy_to_buffer(vma->pages->sgl, vma->pages->nents,
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rsa, sizeof(rsa), guc->fw.rsa_offset);
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sg_pcopy_to_buffer(pages->sgl, pages->nents,
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rsa, sizeof(rsa), fw->rsa_offset);
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for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
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I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
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@ -201,7 +203,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
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* transfer between GTT locations. This functionality is left out of the API
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* for now as there is no need for it.
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*/
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static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
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static int guc_xfer_ucode(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_uc_fw *guc_fw = &guc->fw;
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@ -214,7 +216,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
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I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
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/* Set the source address for the new blob */
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offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
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offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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@ -233,7 +235,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
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/*
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* Load the GuC firmware blob into the MinuteIA.
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*/
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static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
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static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
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{
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struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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@ -250,9 +252,9 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
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* by the DMA engine in one operation, whereas the RSA signature is
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* loaded via MMIO.
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*/
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guc_xfer_rsa(guc, vma);
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guc_xfer_rsa(guc);
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ret = guc_xfer_ucode(guc, vma);
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ret = guc_xfer_ucode(guc);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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@ -40,6 +40,61 @@ int intel_huc_init_misc(struct intel_huc *huc)
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return 0;
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}
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static int intel_huc_rsa_data_create(struct intel_huc *huc)
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{
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struct drm_i915_private *i915 = huc_to_i915(huc);
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struct intel_guc *guc = &i915->guc;
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struct i915_vma *vma;
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void *vaddr;
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/*
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* HuC firmware will sit above GUC_GGTT_TOP and will not map
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* through GTT. Unfortunately, this means GuC cannot perform
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* the HuC auth. as the rsa offset now falls within the GuC
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* inaccessible range. We resort to perma-pinning an additional
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* vma within the accessible range that only contains the rsa
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* signature. The GuC can use this extra pinning to perform
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* the authentication since its GGTT offset will be GuC
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* accessible.
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*/
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vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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i915_vma_unpin_and_release(&vma, 0);
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return PTR_ERR(vaddr);
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}
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huc->rsa_data = vma;
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huc->rsa_data_vaddr = vaddr;
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return 0;
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}
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static void intel_huc_rsa_data_destroy(struct intel_huc *huc)
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{
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i915_vma_unpin_and_release(&huc->rsa_data, I915_VMA_RELEASE_MAP);
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}
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int intel_huc_init(struct intel_huc *huc)
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{
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int err;
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err = intel_huc_rsa_data_create(huc);
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if (err)
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return err;
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return intel_uc_fw_init(&huc->fw);
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}
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void intel_huc_fini(struct intel_huc *huc)
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{
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intel_uc_fw_fini(&huc->fw);
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intel_huc_rsa_data_destroy(huc);
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}
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/**
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* intel_huc_auth() - Authenticate HuC uCode
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* @huc: intel_huc structure
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@ -55,27 +110,17 @@ int intel_huc_auth(struct intel_huc *huc)
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{
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struct drm_i915_private *i915 = huc_to_i915(huc);
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struct intel_guc *guc = &i915->guc;
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struct i915_vma *vma;
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u32 status;
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int ret;
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if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return -ENOEXEC;
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vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
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PIN_OFFSET_BIAS | i915->ggtt.pin_bias);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
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goto fail;
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}
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ret = intel_guc_auth_huc(guc,
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intel_guc_ggtt_offset(guc, vma) +
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huc->fw.rsa_offset);
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intel_guc_ggtt_offset(guc, huc->rsa_data));
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if (ret) {
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DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
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goto fail_unpin;
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goto fail;
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}
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/* Check authentication status, it should be done by now */
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@ -86,14 +131,11 @@ int intel_huc_auth(struct intel_huc *huc)
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2, 50, &status);
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if (ret) {
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DRM_ERROR("HuC: Firmware not verified %#x\n", status);
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goto fail_unpin;
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goto fail;
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}
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i915_vma_unpin(vma);
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return 0;
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fail_unpin:
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i915_vma_unpin(vma);
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fail:
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huc->fw.load_status = INTEL_UC_FIRMWARE_FAIL;
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@ -33,10 +33,14 @@ struct intel_huc {
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struct intel_uc_fw fw;
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/* HuC-specific additions */
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struct i915_vma *rsa_data;
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void *rsa_data_vaddr;
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};
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void intel_huc_init_early(struct intel_huc *huc);
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int intel_huc_init_misc(struct intel_huc *huc);
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int intel_huc_init(struct intel_huc *huc);
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void intel_huc_fini(struct intel_huc *huc);
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int intel_huc_auth(struct intel_huc *huc);
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int intel_huc_check_status(struct intel_huc *huc);
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@ -93,18 +93,24 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
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huc_fw_select(huc_fw);
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}
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/**
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* huc_fw_xfer() - DMA's the firmware
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* @huc_fw: the firmware descriptor
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* @vma: the firmware image (bound into the GGTT)
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*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Return: 0 on success, non-zero on failure
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*/
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static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
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static void huc_xfer_rsa(struct intel_huc *huc)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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struct intel_uc_fw *fw = &huc->fw;
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struct sg_table *pages = fw->obj->mm.pages;
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/*
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* HuC firmware image is outside GuC accessible range.
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* Copy the RSA signature out of the image into
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* the perma-pinned region set aside for it
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*/
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sg_pcopy_to_buffer(pages->sgl, pages->nents,
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huc->rsa_data_vaddr, fw->rsa_size,
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fw->rsa_offset);
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}
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static int huc_xfer_ucode(struct intel_huc *huc)
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{
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struct intel_uc_fw *huc_fw = &huc->fw;
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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struct intel_uncore *uncore = &dev_priv->uncore;
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unsigned long offset = 0;
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@ -116,7 +122,7 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
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intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
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/* Set the source address for the uCode */
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offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
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offset = intel_uc_fw_ggtt_offset(huc_fw) +
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huc_fw->header_offset;
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intel_uncore_write(uncore, DMA_ADDR_0_LOW,
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lower_32_bits(offset));
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@ -150,6 +156,23 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
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return ret;
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}
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/**
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* huc_fw_xfer() - DMA's the firmware
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* @huc_fw: the firmware descriptor
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*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Return: 0 on success, non-zero on failure
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*/
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static int huc_fw_xfer(struct intel_uc_fw *huc_fw)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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huc_xfer_rsa(huc);
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return huc_xfer_ucode(huc);
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}
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/**
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* intel_huc_fw_upload() - load HuC uCode to device
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* @huc: intel_huc structure
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@ -280,6 +280,7 @@ void intel_uc_fini_misc(struct drm_i915_private *i915)
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int intel_uc_init(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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struct intel_huc *huc = &i915->huc;
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int ret;
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if (!USES_GUC(i915))
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@ -292,19 +293,30 @@ int intel_uc_init(struct drm_i915_private *i915)
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if (ret)
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return ret;
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if (USES_HUC(i915)) {
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ret = intel_huc_init(huc);
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if (ret)
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goto err_guc;
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}
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if (USES_GUC_SUBMISSION(i915)) {
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/*
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* This is stuff we need to have available at fw load time
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* if we are planning to enable submission later
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*/
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ret = intel_guc_submission_init(guc);
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if (ret) {
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intel_guc_fini(guc);
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return ret;
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}
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if (ret)
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goto err_huc;
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}
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return 0;
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err_huc:
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if (USES_HUC(i915))
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intel_huc_fini(huc);
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err_guc:
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intel_guc_fini(guc);
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return ret;
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}
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void intel_uc_fini(struct drm_i915_private *i915)
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@ -319,6 +331,9 @@ void intel_uc_fini(struct drm_i915_private *i915)
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if (USES_GUC_SUBMISSION(i915))
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intel_guc_submission_fini(guc);
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if (USES_HUC(i915))
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intel_huc_fini(&i915->huc);
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intel_guc_fini(guc);
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}
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@ -191,6 +191,35 @@ fail:
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release_firmware(fw); /* OK even if fw is NULL */
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}
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static void intel_uc_fw_ggtt_bind(struct intel_uc_fw *uc_fw)
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{
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struct drm_i915_gem_object *obj = uc_fw->obj;
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struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
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struct i915_vma dummy = {
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.node.start = intel_uc_fw_ggtt_offset(uc_fw),
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.node.size = obj->base.size,
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.pages = obj->mm.pages,
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.vm = &ggtt->vm,
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};
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GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
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GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size);
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/* uc_fw->obj cache domains were not controlled across suspend */
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drm_clflush_sg(dummy.pages);
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ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, 0);
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}
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static void intel_uc_fw_ggtt_unbind(struct intel_uc_fw *uc_fw)
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{
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struct drm_i915_gem_object *obj = uc_fw->obj;
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struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
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u64 start = intel_uc_fw_ggtt_offset(uc_fw);
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ggtt->vm.clear_range(&ggtt->vm, start, obj->base.size);
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}
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/**
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* intel_uc_fw_upload - load uC firmware using custom loader
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* @uc_fw: uC firmware
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|
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@ -201,11 +230,8 @@ fail:
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* Return: 0 on success, non-zero on failure.
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*/
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int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
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int (*xfer)(struct intel_uc_fw *uc_fw,
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struct i915_vma *vma))
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int (*xfer)(struct intel_uc_fw *uc_fw))
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{
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struct i915_vma *vma;
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u32 ggtt_pin_bias;
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int err;
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DRM_DEBUG_DRIVER("%s fw load %s\n",
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|
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@ -219,36 +245,15 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
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intel_uc_fw_type_repr(uc_fw->type),
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intel_uc_fw_status_repr(uc_fw->load_status));
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/* Pin object with firmware */
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err = i915_gem_object_set_to_gtt_domain(uc_fw->obj, false);
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if (err) {
|
||||
DRM_DEBUG_DRIVER("%s fw set-domain err=%d\n",
|
||||
intel_uc_fw_type_repr(uc_fw->type), err);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ggtt_pin_bias = to_i915(uc_fw->obj->base.dev)->ggtt.pin_bias;
|
||||
vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
|
||||
PIN_OFFSET_BIAS | ggtt_pin_bias);
|
||||
if (IS_ERR(vma)) {
|
||||
err = PTR_ERR(vma);
|
||||
DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
|
||||
intel_uc_fw_type_repr(uc_fw->type), err);
|
||||
goto fail;
|
||||
}
|
||||
intel_uc_fw_ggtt_bind(uc_fw);
|
||||
|
||||
/* Call custom loader */
|
||||
err = xfer(uc_fw, vma);
|
||||
|
||||
/*
|
||||
* We keep the object pages for reuse during resume. But we can unpin it
|
||||
* now that DMA has completed, so it doesn't continue to take up space.
|
||||
*/
|
||||
i915_vma_unpin(vma);
|
||||
|
||||
err = xfer(uc_fw);
|
||||
if (err)
|
||||
goto fail;
|
||||
|
||||
intel_uc_fw_ggtt_unbind(uc_fw);
|
||||
|
||||
uc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
|
||||
DRM_DEBUG_DRIVER("%s fw load %s\n",
|
||||
intel_uc_fw_type_repr(uc_fw->type),
|
||||
|
|
@ -273,6 +278,42 @@ fail:
|
|||
return err;
|
||||
}
|
||||
|
||||
int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
|
||||
return -ENOEXEC;
|
||||
|
||||
err = i915_gem_object_pin_pages(uc_fw->obj);
|
||||
if (err)
|
||||
DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n",
|
||||
intel_uc_fw_type_repr(uc_fw->type), err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
void intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
|
||||
{
|
||||
if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
|
||||
return;
|
||||
|
||||
i915_gem_object_unpin_pages(uc_fw->obj);
|
||||
}
|
||||
|
||||
u32 intel_uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
|
||||
struct i915_ggtt *ggtt = &i915->ggtt;
|
||||
struct drm_mm_node *node = &ggtt->uc_fw;
|
||||
|
||||
GEM_BUG_ON(!node->allocated);
|
||||
GEM_BUG_ON(upper_32_bits(node->start));
|
||||
GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
|
||||
|
||||
return lower_32_bits(node->start);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_uc_fw_cleanup_fetch - cleanup uC firmware
|
||||
*
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
|
||||
struct drm_printer;
|
||||
struct drm_i915_private;
|
||||
struct i915_vma;
|
||||
|
||||
/* Home of GuC, HuC and DMC firmwares */
|
||||
#define INTEL_UC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915"
|
||||
|
|
@ -147,8 +146,10 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
|
|||
struct intel_uc_fw *uc_fw);
|
||||
void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw);
|
||||
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
|
||||
int (*xfer)(struct intel_uc_fw *uc_fw,
|
||||
struct i915_vma *vma));
|
||||
int (*xfer)(struct intel_uc_fw *uc_fw));
|
||||
int intel_uc_fw_init(struct intel_uc_fw *uc_fw);
|
||||
void intel_uc_fw_fini(struct intel_uc_fw *uc_fw);
|
||||
u32 intel_uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw);
|
||||
void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue