cxgb4: Replaced the backdoor mechanism to access the HW memory with PCIe Window method
Rip out a bunch of redundant PCI-E Memory Window Read/Write routines, collapse the more general purpose routines into a single routine thereby eliminating the need for a large stack frame (and extra data copying) in the outer routine, change everything to use the improved routine t4_memory_rw. Based on origninal work by Casey Leedom <leedom@chelsio.com> and Steve Wise <swise@opengridcomputing.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Hariprasad Shenai
David S. Miller
parent
0abfd1524b
commit
fc5ab02096
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@ -654,6 +654,7 @@ struct adapter {
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struct dentry *debugfs_root;
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spinlock_t stats_lock;
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spinlock_t win0_lock ____cacheline_aligned_in_smp;
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};
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/* Defined bit width of user definable filter tuples
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@ -960,8 +961,17 @@ int t4_wait_dev_ready(struct adapter *adap);
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int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
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struct link_config *lc);
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int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
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int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
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__be32 *buf);
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#define T4_MEMORY_WRITE 0
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#define T4_MEMORY_READ 1
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int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
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__be32 *buf, int dir);
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static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
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u32 len, __be32 *buf)
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{
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return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
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}
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int t4_seeprom_wp(struct adapter *adapter, bool enable);
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int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
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int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
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@ -1059,7 +1069,6 @@ int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
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int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
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void t4_db_full(struct adapter *adapter);
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void t4_db_dropped(struct adapter *adapter);
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int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
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int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
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u32 addr, u32 val);
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void t4_sge_decode_idma_state(struct adapter *adapter, int state);
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@ -3066,6 +3066,8 @@ static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
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loff_t avail = file_inode(file)->i_size;
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unsigned int mem = (uintptr_t)file->private_data & 3;
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struct adapter *adap = file->private_data - mem;
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__be32 *data;
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int ret;
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if (pos < 0)
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return -EINVAL;
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@ -3074,29 +3076,24 @@ static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
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if (count > avail - pos)
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count = avail - pos;
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while (count) {
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size_t len;
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int ret, ofst;
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__be32 data[16];
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data = t4_alloc_mem(count);
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if (!data)
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return -ENOMEM;
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if ((mem == MEM_MC) || (mem == MEM_MC1))
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ret = t4_mc_read(adap, mem % MEM_MC, pos, data, NULL);
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else
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ret = t4_edc_read(adap, mem, pos, data, NULL);
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if (ret)
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return ret;
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ofst = pos % sizeof(data);
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len = min(count, sizeof(data) - ofst);
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if (copy_to_user(buf, (u8 *)data + ofst, len))
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return -EFAULT;
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buf += len;
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pos += len;
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count -= len;
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spin_lock(&adap->win0_lock);
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ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
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spin_unlock(&adap->win0_lock);
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if (ret) {
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t4_free_mem(data);
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return ret;
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}
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count = pos - *ppos;
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*ppos = pos;
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ret = copy_to_user(buf, data, count);
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t4_free_mem(data);
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if (ret)
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return -EFAULT;
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*ppos = pos + count;
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return count;
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}
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@ -3757,7 +3754,11 @@ static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
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__be64 indices;
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int ret;
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ret = t4_mem_win_read_len(adap, addr, (__be32 *)&indices, 8);
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spin_lock(&adap->win0_lock);
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ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
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sizeof(indices), (__be32 *)&indices,
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T4_MEMORY_READ);
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spin_unlock(&adap->win0_lock);
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if (!ret) {
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*cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
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*pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
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@ -5076,7 +5077,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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adapter->fn, 0, 1, params, val);
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if (ret == 0) {
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/*
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* For t4_memory_write() below addresses and
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* For t4_memory_rw() below addresses and
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* sizes have to be in terms of multiples of 4
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* bytes. So, if the Configuration File isn't
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* a multiple of 4 bytes in length we'll have
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@ -5092,8 +5093,9 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
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maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
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ret = t4_memory_write(adapter, mtype, maddr,
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size, data);
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spin_lock(&adapter->win0_lock);
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ret = t4_memory_rw(adapter, 0, mtype, maddr,
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size, data, T4_MEMORY_WRITE);
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if (ret == 0 && resid != 0) {
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union {
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__be32 word;
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@ -5104,10 +5106,12 @@ static int adap_init0_config(struct adapter *adapter, int reset)
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last.word = data[size >> 2];
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for (i = resid; i < 4; i++)
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last.buf[i] = 0;
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ret = t4_memory_write(adapter, mtype,
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maddr + size,
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4, &last.word);
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ret = t4_memory_rw(adapter, 0, mtype,
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maddr + size,
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4, &last.word,
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T4_MEMORY_WRITE);
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}
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spin_unlock(&adapter->win0_lock);
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}
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}
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@ -413,78 +413,41 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
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return 0;
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}
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/*
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* t4_mem_win_rw - read/write memory through PCIE memory window
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* @adap: the adapter
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* @addr: address of first byte requested
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* @data: MEMWIN0_APERTURE bytes of data containing the requested address
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* @dir: direction of transfer 1 => read, 0 => write
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*
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* Read/write MEMWIN0_APERTURE bytes of data from MC starting at a
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* MEMWIN0_APERTURE-byte-aligned address that covers the requested
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* address @addr.
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*/
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static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
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{
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int i;
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u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
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/*
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* Setup offset into PCIE memory window. Address must be a
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* MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to
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* ensure that changes propagate before we attempt to use the new
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* values.)
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*/
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t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
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(addr & ~(MEMWIN0_APERTURE - 1)) | win_pf);
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t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
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/* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
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for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
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if (dir)
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*data++ = (__force __be32) t4_read_reg(adap,
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(MEMWIN0_BASE + i));
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else
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t4_write_reg(adap, (MEMWIN0_BASE + i),
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(__force u32) *data++);
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}
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return 0;
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}
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/**
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* t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
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* @adap: the adapter
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* @win: PCI-E Memory Window to use
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* @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
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* @addr: address within indicated memory type
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* @len: amount of memory to transfer
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* @buf: host memory buffer
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* @dir: direction of transfer 1 => read, 0 => write
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* @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
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*
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* Reads/writes an [almost] arbitrary memory region in the firmware: the
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* firmware memory address, length and host buffer must be aligned on
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* 32-bit boudaries. The memory is transferred as a raw byte sequence
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* from/to the firmware's memory. If this memory contains data
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* structures which contain multi-byte integers, it's the callers
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* responsibility to perform appropriate byte order conversions.
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* firmware memory address and host buffer must be aligned on 32-bit
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* boudaries; the length may be arbitrary. The memory is transferred as
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* a raw byte sequence from/to the firmware's memory. If this memory
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* contains data structures which contain multi-byte integers, it's the
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* caller's responsibility to perform appropriate byte order conversions.
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*/
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static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
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__be32 *buf, int dir)
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int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
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u32 len, __be32 *buf, int dir)
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{
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u32 pos, start, end, offset, memoffset;
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u32 edc_size, mc_size;
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int ret = 0;
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__be32 *data;
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u32 pos, offset, resid, memoffset;
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u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
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/*
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* Argument sanity checks ...
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/* Argument sanity checks ...
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*/
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if ((addr & 0x3) || (len & 0x3))
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if (addr & 0x3)
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return -EINVAL;
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data = vmalloc(MEMWIN0_APERTURE);
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if (!data)
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return -ENOMEM;
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/* It's convenient to be able to handle lengths which aren't a
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* multiple of 32-bits because we often end up transferring files to
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* the firmware. So we'll handle that by normalizing the length here
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* and then handling any residual transfer at the end.
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*/
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resid = len & 0x3;
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len -= resid;
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/* Offset into the region of memory which is being accessed
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* MEM_EDC0 = 0
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@ -505,66 +468,98 @@ static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
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/* Determine the PCIE_MEM_ACCESS_OFFSET */
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addr = addr + memoffset;
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/*
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* The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes
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* at a time so we need to round down the start and round up the end.
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* We'll start copying out of the first line at (addr - start) a word
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* at a time.
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/* Each PCI-E Memory Window is programmed with a window size -- or
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* "aperture" -- which controls the granularity of its mapping onto
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* adapter memory. We need to grab that aperture in order to know
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* how to use the specified window. The window is also programmed
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* with the base address of the Memory Window in BAR0's address
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* space. For T4 this is an absolute PCI-E Bus Address. For T5
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* the address is relative to BAR0.
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*/
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start = addr & ~(MEMWIN0_APERTURE-1);
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end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1);
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offset = (addr - start)/sizeof(__be32);
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mem_reg = t4_read_reg(adap,
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PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN,
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win));
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mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10);
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mem_base = GET_PCIEOFST(mem_reg) << 10;
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if (is_t4(adap->params.chip))
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mem_base -= adap->t4_bar0;
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win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
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for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) {
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/* Calculate our initial PCI-E Memory Window Position and Offset into
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* that Window.
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*/
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pos = addr & ~(mem_aperture-1);
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offset = addr - pos;
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/*
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* If we're writing, copy the data from the caller's memory
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* buffer
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/* Set up initial PCI-E Memory Window to cover the start of our
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* transfer. (Read it back to ensure that changes propagate before we
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* attempt to use the new value.)
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*/
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t4_write_reg(adap,
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PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win),
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pos | win_pf);
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t4_read_reg(adap,
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PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
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/* Transfer data to/from the adapter as long as there's an integral
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* number of 32-bit transfers to complete.
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*/
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while (len > 0) {
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if (dir == T4_MEMORY_READ)
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*buf++ = (__force __be32) t4_read_reg(adap,
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mem_base + offset);
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else
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t4_write_reg(adap, mem_base + offset,
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(__force u32) *buf++);
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offset += sizeof(__be32);
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len -= sizeof(__be32);
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/* If we've reached the end of our current window aperture,
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* move the PCI-E Memory Window on to the next. Note that
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* doing this here after "len" may be 0 allows us to set up
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* the PCI-E Memory Window for a possible final residual
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* transfer below ...
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*/
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if (!dir) {
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/*
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* If we're doing a partial write, then we need to do
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* a read-modify-write ...
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*/
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if (offset || len < MEMWIN0_APERTURE) {
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ret = t4_mem_win_rw(adap, pos, data, 1);
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if (ret)
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break;
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}
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while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
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len > 0) {
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data[offset++] = *buf++;
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len -= sizeof(__be32);
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}
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if (offset == mem_aperture) {
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pos += mem_aperture;
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offset = 0;
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t4_write_reg(adap,
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PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
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win), pos | win_pf);
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t4_read_reg(adap,
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PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
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win));
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}
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/*
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* Transfer a block of memory and bail if there's an error.
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*/
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ret = t4_mem_win_rw(adap, pos, data, dir);
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if (ret)
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break;
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/*
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* If we're reading, copy the data into the caller's memory
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* buffer.
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*/
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if (dir)
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while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
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len > 0) {
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*buf++ = data[offset++];
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len -= sizeof(__be32);
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}
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}
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vfree(data);
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return ret;
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}
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/* If the original transfer had a length which wasn't a multiple of
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* 32-bits, now's where we need to finish off the transfer of the
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* residual amount. The PCI-E Memory Window has already been moved
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* above (if necessary) to cover this final transfer.
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*/
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if (resid) {
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union {
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__be32 word;
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char byte[4];
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} last;
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unsigned char *bp;
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int i;
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int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
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__be32 *buf)
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{
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return t4_memory_rw(adap, mtype, addr, len, buf, 0);
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if (dir == T4_MEMORY_WRITE) {
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last.word = (__force __be32) t4_read_reg(adap,
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mem_base + offset);
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for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
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bp[i] = last.byte[i];
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} else {
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last.word = *buf;
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for (i = resid; i < 4; i++)
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last.byte[i] = 0;
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t4_write_reg(adap, mem_base + offset,
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(__force u32) last.word);
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}
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}
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return 0;
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}
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#define EEPROM_STAT_ADDR 0x7bfc
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@ -2528,39 +2523,6 @@ int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
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return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
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}
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/**
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* t4_mem_win_read_len - read memory through PCIE memory window
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* @adap: the adapter
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* @addr: address of first byte requested aligned on 32b.
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* @data: len bytes to hold the data read
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* @len: amount of data to read from window. Must be <=
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* MEMWIN0_APERATURE after adjusting for 16B for T4 and
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* 128B for T5 alignment requirements of the the memory window.
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*
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* Read len bytes of data from MC starting at @addr.
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*/
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int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
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{
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int i, off;
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u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
|
||||
|
||||
/* Align on a 2KB boundary.
|
||||
*/
|
||||
off = addr & MEMWIN0_APERTURE;
|
||||
if ((addr & 3) || (len + off) > MEMWIN0_APERTURE)
|
||||
return -EINVAL;
|
||||
|
||||
t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
|
||||
(addr & ~MEMWIN0_APERTURE) | win_pf);
|
||||
t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
|
||||
|
||||
for (i = 0; i < len; i += 4)
|
||||
*data++ = (__force __be32) t4_read_reg(adap,
|
||||
(MEMWIN0_BASE + off + i));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* t4_mdio_rd - read a PHY register through MDIO
|
||||
* @adap: the adapter
|
||||
|
|
|
|||
|
|
@ -400,6 +400,7 @@
|
|||
#define WINDOW_MASK 0x000000ffU
|
||||
#define WINDOW_SHIFT 0
|
||||
#define WINDOW(x) ((x) << WINDOW_SHIFT)
|
||||
#define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK)
|
||||
#define PCIE_MEM_ACCESS_OFFSET 0x306c
|
||||
#define ENABLE (1U << 30)
|
||||
#define FUNCTION(x) ((x) << 12)
|
||||
|
|
|
|||
Loading…
Reference in New Issue