net: mvmdio: new Marvell MDIO driver
This patch adds a separate driver for the MDIO interface of the
Marvell Ethernet controllers. There are two reasons to have a separate
driver rather than including it inside the MAC driver itself:
*) The MDIO interface is shared by all Ethernet ports, so a driver
must guarantee non-concurrent accesses to this MDIO interface. The
most logical way is to have a separate driver that handles this
single MDIO interface, used by all Ethernet ports.
*) The MDIO interface is the same between the existing mv643xx_eth
driver and the new mvneta driver. Even though it is for now only
used by the mvneta driver, it will in the future be used by the
mv643xx_eth driver as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Thomas Petazzoni
parent
77b67063bb
commit
fc8f5aded1
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@ -0,0 +1,35 @@
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* Marvell MDIO Ethernet Controller interface
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The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x,
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MV78xx0, Armada 370 and Armada XP have an identical unit that provides
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an interface with the MDIO bus. This driver handles this MDIO
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interface.
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Required properties:
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- compatible: "marvell,orion-mdio"
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- reg: address and length of the SMI register
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The child nodes of the MDIO driver are the individual PHY devices
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connected to this MDIO bus. They must have a "reg" property given the
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PHY address on the MDIO bus.
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Example at the SoC level:
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0xd0072004 0x4>;
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};
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And at the board level:
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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}
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@ -31,6 +31,17 @@ config MV643XX_ETH
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Some boards that use the Discovery chipset are the Momenco
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Ocelot C and Jaguar ATX and Pegasos II.
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config MVMDIO
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tristate "Marvell MDIO interface support"
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---help---
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This driver supports the MDIO interface found in the network
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interface units of the Marvell EBU SoCs (Kirkwood, Orion5x,
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Dove, Armada 370 and Armada XP).
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For now, this driver is only needed for the MVNETA driver
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(used on Armada 370 and XP), but it could be used in the
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future by the MV643XX_ETH driver.
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config PXA168_ETH
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tristate "Marvell pxa168 ethernet support"
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depends on CPU_PXA168
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@ -3,6 +3,7 @@
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#
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obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
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obj-$(CONFIG_MVMDIO) += mvmdio.o
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obj-$(CONFIG_PXA168_ETH) += pxa168_eth.o
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obj-$(CONFIG_SKGE) += skge.o
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obj-$(CONFIG_SKY2) += sky2.o
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@ -0,0 +1,230 @@
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/*
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* Driver for the MDIO interface of Marvell network interfaces.
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*
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* Since the MDIO interface of Marvell network interfaces is shared
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* between all network interfaces, having a single driver allows to
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* handle concurrent accesses properly (you may have four Ethernet
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* ports, but they in fact share the same SMI interface to access the
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* MDIO bus). Moreover, this MDIO interface code is similar between
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* the mv643xx_eth driver and the mvneta driver. For now, it is only
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* used by the mvneta driver, but it could later be used by the
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* mv643xx_eth driver as well.
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/phy.h>
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#include <linux/of_address.h>
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#include <linux/of_mdio.h>
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#include <linux/platform_device.h>
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#include <asm/delay.h>
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#define MVMDIO_SMI_DATA_SHIFT 0
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#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
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#define MVMDIO_SMI_PHY_REG_SHIFT 21
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#define MVMDIO_SMI_READ_OPERATION BIT(26)
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#define MVMDIO_SMI_WRITE_OPERATION 0
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#define MVMDIO_SMI_READ_VALID BIT(27)
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#define MVMDIO_SMI_BUSY BIT(28)
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struct orion_mdio_dev {
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struct mutex lock;
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void __iomem *smireg;
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};
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/*
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* Wait for the SMI unit to be ready for another operation
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*/
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static int orion_mdio_wait_ready(struct mii_bus *bus)
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{
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struct orion_mdio_dev *dev = bus->priv;
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int count;
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u32 val;
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count = 0;
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while (1) {
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val = readl(dev->smireg);
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if (!(val & MVMDIO_SMI_BUSY))
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break;
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if (count > 100) {
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dev_err(bus->parent, "Timeout: SMI busy for too long\n");
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return -ETIMEDOUT;
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}
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udelay(10);
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count++;
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}
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return 0;
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}
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static int orion_mdio_read(struct mii_bus *bus, int mii_id,
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int regnum)
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{
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struct orion_mdio_dev *dev = bus->priv;
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int count;
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u32 val;
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int ret;
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mutex_lock(&dev->lock);
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ret = orion_mdio_wait_ready(bus);
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if (ret < 0) {
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mutex_unlock(&dev->lock);
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return ret;
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}
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writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_READ_OPERATION),
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dev->smireg);
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/* Wait for the value to become available */
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count = 0;
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while (1) {
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val = readl(dev->smireg);
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if (val & MVMDIO_SMI_READ_VALID)
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break;
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if (count > 100) {
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dev_err(bus->parent, "Timeout when reading PHY\n");
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mutex_unlock(&dev->lock);
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return -ETIMEDOUT;
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}
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udelay(10);
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count++;
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}
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mutex_unlock(&dev->lock);
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return val & 0xFFFF;
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}
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static int orion_mdio_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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struct orion_mdio_dev *dev = bus->priv;
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int ret;
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mutex_lock(&dev->lock);
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ret = orion_mdio_wait_ready(bus);
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if (ret < 0) {
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mutex_unlock(&dev->lock);
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return ret;
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}
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writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_WRITE_OPERATION |
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(value << MVMDIO_SMI_DATA_SHIFT)),
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dev->smireg);
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mutex_unlock(&dev->lock);
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return 0;
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}
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static int orion_mdio_reset(struct mii_bus *bus)
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{
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return 0;
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}
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static int __devinit orion_mdio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct mii_bus *bus;
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struct orion_mdio_dev *dev;
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int i, ret;
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bus = mdiobus_alloc_size(sizeof(struct orion_mdio_dev));
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if (!bus) {
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dev_err(&pdev->dev, "Cannot allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->name = "orion_mdio_bus";
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bus->read = orion_mdio_read;
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bus->write = orion_mdio_write;
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bus->reset = orion_mdio_reset;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
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dev_name(&pdev->dev));
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bus->parent = &pdev->dev;
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bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
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if (!bus->irq) {
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dev_err(&pdev->dev, "Cannot allocate PHY IRQ array\n");
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mdiobus_free(bus);
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return -ENOMEM;
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}
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for (i = 0; i < PHY_MAX_ADDR; i++)
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bus->irq[i] = PHY_POLL;
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dev = bus->priv;
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dev->smireg = of_iomap(pdev->dev.of_node, 0);
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if (!dev->smireg) {
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dev_err(&pdev->dev, "No SMI register address given in DT\n");
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kfree(bus->irq);
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mdiobus_free(bus);
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return -ENODEV;
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}
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mutex_init(&dev->lock);
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ret = of_mdiobus_register(bus, np);
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if (ret < 0) {
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dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
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iounmap(dev->smireg);
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kfree(bus->irq);
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mdiobus_free(bus);
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return ret;
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}
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platform_set_drvdata(pdev, bus);
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return 0;
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}
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static int __devexit orion_mdio_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = platform_get_drvdata(pdev);
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mdiobus_unregister(bus);
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kfree(bus->irq);
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mdiobus_free(bus);
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return 0;
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}
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static const struct of_device_id orion_mdio_match[] = {
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{ .compatible = "marvell,orion-mdio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, orion_mdio_match);
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static struct platform_driver orion_mdio_driver = {
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.probe = orion_mdio_probe,
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.remove = __devexit_p(orion_mdio_remove),
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.driver = {
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.name = "orion-mdio",
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.of_match_table = orion_mdio_match,
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},
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};
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module_platform_driver(orion_mdio_driver);
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MODULE_DESCRIPTION("Marvell MDIO interface driver");
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MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
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MODULE_LICENSE("GPL");
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