drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-4-chris@chris-wilson.co.uk
(cherry picked from commit c3b93a943f
)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
parent
695a2b1164
commit
fd2599bda5
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@ -692,6 +692,45 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
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return 0;
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}
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static void
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snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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/* WaDisableHiZPlanesWhenMSAAEnabled:snb */
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wa_masked_en(wal,
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_3D_CHICKEN,
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_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
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/* WaDisable_RenderCache_OperationalFlush:snb */
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wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
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/*
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* BSpec recommends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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wa_add(wal,
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GEN6_GT_MODE, 0,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB);
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wa_masked_en(wal,
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_3D_CHICKEN3,
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/* WaStripsFansDisableFastClipPerformanceFix:snb */
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_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
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/*
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* Bspec says:
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* "This bit must be set if 3DSTATE_CLIP clip mode is set
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* to normal and 3DSTATE_SF number of SF output attributes
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* is more than 16."
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*/
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_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
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}
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static void
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ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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@ -1132,6 +1171,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
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vlv_gt_workarounds_init(i915, wal);
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else if (IS_IVYBRIDGE(i915))
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ivb_gt_workarounds_init(i915, wal);
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else if (IS_GEN(i915, 6))
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snb_gt_workarounds_init(i915, wal);
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else if (INTEL_GEN(i915) <= 8)
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return;
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else
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@ -6902,27 +6902,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_ELPIN_409_SELECT);
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/* WaDisableHiZPlanesWhenMSAAEnabled:snb */
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I915_WRITE(_3D_CHICKEN,
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_MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
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/* WaDisable_RenderCache_OperationalFlush:snb */
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I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
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/*
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* BSpec recoomends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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I915_WRITE(GEN6_GT_MODE,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
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I915_WRITE(CACHE_MODE_0,
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_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
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I915_WRITE(GEN6_UCGCTL1,
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I915_READ(GEN6_UCGCTL1) |
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GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
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@ -6945,18 +6924,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
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GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
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GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
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/* WaStripsFansDisableFastClipPerformanceFix:snb */
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I915_WRITE(_3D_CHICKEN3,
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_MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
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/*
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* Bspec says:
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* "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
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* 3DSTATE_SF number of SF output attributes is more than 16."
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*/
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I915_WRITE(_3D_CHICKEN3,
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_MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
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/*
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* According to the spec the following bits should be
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* set in order to enable memory self-refresh and fbc:
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