USB/PHY fixes for 5.6-rc5
Here are some small USB and PHY driver fixes for reported issues for 5.6-rc5. Included in here are: - phy driver fixes - new USB quirks - USB cdns3 gadget driver fixes - USB hub core fixes All of these have been in linux-next with no reported issues. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXmS/qw8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+ynEUwCfWN11rUIm4gI3qL3IBnbDdyOwN+wAnj8Nt6gh nNJi+MAmGC1hWaB5CiJY =4eZ8 -----END PGP SIGNATURE----- Merge tag 'usb-5.6-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY fixes from Greg KH: "Here are some small USB and PHY driver fixes for reported issues for 5.6-rc5. Included in here are: - phy driver fixes - new USB quirks - USB cdns3 gadget driver fixes - USB hub core fixes All of these have been in linux-next with no reported issues" * tag 'usb-5.6-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: usb: dwc3: gadget: Update chain bit correctly when using sg list usb: core: port: do error out if usb_autopm_get_interface() fails usb: core: hub: do error out if usb_autopm_get_interface() fails usb: core: hub: fix unhandled return by employing a void function usb: storage: Add quirk for Samsung Fit flash usb: quirks: add NO_LPM quirk for Logitech Screen Share usb: usb251xb: fix regulator probe and error handling phy: allwinner: Fix GENMASK misuse usb: cdns3: gadget: toggle cycle bit before reset endpoint usb: cdns3: gadget: link trb should point to next request phy: mapphone-mdm6600: Fix timeouts by adding wake-up handling phy: brcm-sata: Correct MDIO operations for 40nm platforms phy: ti: gmii-sel: do not fail in case of gmii phy: ti: gmii-sel: fix set of copy-paste errors phy: core: Fix phy_get() to not return error on link creation failure phy: mapphone-mdm6600: Fix write timeouts with shorter GPIO toggle interval
This commit is contained in:
Linus Torvalds
commit
fd3f6cc980
|
|
@ -49,7 +49,7 @@
|
|||
#define SUNXI_LOS_BIAS(n) ((n) << 3)
|
||||
#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
|
||||
#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
|
||||
#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2)
|
||||
#define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)
|
||||
|
||||
struct sun50i_usb3_phy {
|
||||
struct phy *phy;
|
||||
|
|
|
|||
|
|
@ -186,29 +186,6 @@ enum sata_phy_ctrl_regs {
|
|||
PHY_CTRL_1_RESET = BIT(0),
|
||||
};
|
||||
|
||||
static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
|
||||
{
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
u32 size = 0;
|
||||
|
||||
switch (priv->version) {
|
||||
case BRCM_SATA_PHY_STB_16NM:
|
||||
case BRCM_SATA_PHY_STB_28NM:
|
||||
case BRCM_SATA_PHY_IPROC_NS2:
|
||||
case BRCM_SATA_PHY_DSL_28NM:
|
||||
size = SATA_PCB_REG_28NM_SPACE_SIZE;
|
||||
break;
|
||||
case BRCM_SATA_PHY_STB_40NM:
|
||||
size = SATA_PCB_REG_40NM_SPACE_SIZE;
|
||||
break;
|
||||
default:
|
||||
dev_err(priv->dev, "invalid phy version\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return priv->phy_base + (port->portnum * size);
|
||||
}
|
||||
|
||||
static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
|
||||
{
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
|
|
@ -226,19 +203,34 @@ static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
|
|||
return priv->ctrl_base + (port->portnum * size);
|
||||
}
|
||||
|
||||
static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
|
||||
static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
|
||||
u32 ofs, u32 msk, u32 value)
|
||||
{
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
void __iomem *pcb_base = priv->phy_base;
|
||||
u32 tmp;
|
||||
|
||||
if (priv->version == BRCM_SATA_PHY_STB_40NM)
|
||||
bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
|
||||
else
|
||||
pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
|
||||
|
||||
writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
|
||||
tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
|
||||
tmp = (tmp & msk) | value;
|
||||
writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
|
||||
}
|
||||
|
||||
static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
|
||||
static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
|
||||
{
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
void __iomem *pcb_base = priv->phy_base;
|
||||
|
||||
if (priv->version == BRCM_SATA_PHY_STB_40NM)
|
||||
bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
|
||||
else
|
||||
pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
|
||||
|
||||
writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
|
||||
return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
|
||||
}
|
||||
|
|
@ -250,16 +242,15 @@ static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
|
|||
|
||||
static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
|
||||
{
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
u32 tmp;
|
||||
|
||||
/* override the TX spread spectrum setting */
|
||||
tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
|
||||
brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
|
||||
brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
|
||||
|
||||
/* set fixed min freq */
|
||||
brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
|
||||
brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
|
||||
~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
|
||||
STB_FMIN_VAL_DEFAULT);
|
||||
|
||||
|
|
@ -271,7 +262,7 @@ static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
|
|||
tmp = STB_FMAX_VAL_DEFAULT;
|
||||
}
|
||||
|
||||
brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
|
||||
brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
|
||||
~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
|
||||
}
|
||||
|
||||
|
|
@ -280,7 +271,6 @@ static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
|
|||
|
||||
static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
|
||||
{
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
u32 tmp = 0, reg = 0;
|
||||
|
||||
switch (port->rxaeq_mode) {
|
||||
|
|
@ -301,8 +291,8 @@ static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
|
|||
break;
|
||||
}
|
||||
|
||||
brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
|
||||
brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
|
||||
brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
|
||||
brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -316,18 +306,17 @@ static int brcm_stb_sata_init(struct brcm_sata_port *port)
|
|||
|
||||
static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
|
||||
{
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
u32 tmp, value;
|
||||
|
||||
/* Reduce CP tail current to 1/16th of its default value */
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
|
||||
|
||||
/* Turn off CP tail current boost */
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
|
||||
|
||||
/* Set a specific AEQ equalizer value */
|
||||
tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
|
||||
brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
|
||||
brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
|
||||
~(tmp | AEQ_RFZ_FRC_VAL |
|
||||
AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
|
||||
tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
|
||||
|
|
@ -337,7 +326,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
|
|||
value = 0x52;
|
||||
else
|
||||
value = 0;
|
||||
brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
|
||||
brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
|
||||
~RXPMD_RX_PPM_VAL_MASK, value);
|
||||
|
||||
/* Set proportional loop bandwith Gen1/2/3 */
|
||||
|
|
@ -352,7 +341,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
|
|||
value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
|
||||
1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
|
||||
1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
|
||||
brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
|
||||
brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
|
||||
value);
|
||||
|
||||
/* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
|
||||
|
|
@ -365,7 +354,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
|
|||
1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
|
||||
else
|
||||
value = 0;
|
||||
brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
|
||||
brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
|
||||
~tmp, value);
|
||||
|
||||
/* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
|
||||
|
|
@ -378,7 +367,7 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
|
|||
1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
|
||||
else
|
||||
value = 0;
|
||||
brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
|
||||
brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
|
||||
~tmp, value);
|
||||
|
||||
/* Set no guard band and clamp CDR */
|
||||
|
|
@ -387,11 +376,11 @@ static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
|
|||
value = 0x51;
|
||||
else
|
||||
value = 0;
|
||||
brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
|
||||
brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
|
||||
~tmp, RXPMD_MON_CORRECT_EN | value);
|
||||
|
||||
/* Turn on/off SSC */
|
||||
brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
|
||||
brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
|
||||
port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
|
||||
|
||||
return 0;
|
||||
|
|
@ -411,7 +400,6 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
|
|||
{
|
||||
int try;
|
||||
unsigned int val;
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
|
||||
struct device *dev = port->phy_priv->dev;
|
||||
|
||||
|
|
@ -421,24 +409,24 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
|
|||
val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
|
||||
val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
|
||||
val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
|
||||
brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
|
||||
brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
|
||||
val = 0x0;
|
||||
val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
|
||||
val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
|
||||
val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
|
||||
brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
|
||||
brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
|
||||
|
||||
/* Configure PHY PLL register bank 1 */
|
||||
val = NS2_PLL1_ACTRL2_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
|
||||
val = NS2_PLL1_ACTRL3_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
|
||||
val = NS2_PLL1_ACTRL4_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
|
||||
|
||||
/* Configure PHY BLOCK0 register bank */
|
||||
/* Set oob_clk_sel to refclk/2 */
|
||||
brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
|
||||
brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
|
||||
~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
|
||||
BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
|
||||
|
||||
|
|
@ -451,7 +439,7 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
|
|||
/* Wait for PHY PLL lock by polling pll_lock bit */
|
||||
try = 50;
|
||||
while (try) {
|
||||
val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
|
||||
val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
|
||||
BLOCK0_XGXSSTATUS);
|
||||
if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
|
||||
break;
|
||||
|
|
@ -471,9 +459,7 @@ static int brcm_ns2_sata_init(struct brcm_sata_port *port)
|
|||
|
||||
static int brcm_nsp_sata_init(struct brcm_sata_port *port)
|
||||
{
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
struct device *dev = port->phy_priv->dev;
|
||||
void __iomem *base = priv->phy_base;
|
||||
unsigned int oob_bank;
|
||||
unsigned int val, try;
|
||||
|
||||
|
|
@ -490,36 +476,36 @@ static int brcm_nsp_sata_init(struct brcm_sata_port *port)
|
|||
val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
|
||||
val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
|
||||
val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
|
||||
brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
|
||||
brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
|
||||
|
||||
val = 0x0;
|
||||
val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
|
||||
val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
|
||||
val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
|
||||
brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
|
||||
brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
|
||||
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
|
||||
~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
|
||||
0x0c << PLL_ACTRL2_SELDIV_SHIFT);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
|
||||
0xff0, 0x4f0);
|
||||
|
||||
val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
~val, val);
|
||||
val = PLLCONTROL_0_SEQ_START;
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
~val, 0);
|
||||
mdelay(10);
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
~val, val);
|
||||
|
||||
/* Wait for pll_seq_done bit */
|
||||
try = 50;
|
||||
while (--try) {
|
||||
val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
|
||||
val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
|
||||
BLOCK0_XGXSSTATUS);
|
||||
if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
|
||||
break;
|
||||
|
|
@ -546,27 +532,25 @@ static int brcm_nsp_sata_init(struct brcm_sata_port *port)
|
|||
|
||||
static int brcm_sr_sata_init(struct brcm_sata_port *port)
|
||||
{
|
||||
struct brcm_sata_phy *priv = port->phy_priv;
|
||||
struct device *dev = port->phy_priv->dev;
|
||||
void __iomem *base = priv->phy_base;
|
||||
unsigned int val, try;
|
||||
|
||||
/* Configure PHY PLL register bank 1 */
|
||||
val = SR_PLL1_ACTRL2_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
|
||||
val = SR_PLL1_ACTRL3_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
|
||||
val = SR_PLL1_ACTRL4_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
|
||||
|
||||
/* Configure PHY PLL register bank 0 */
|
||||
val = SR_PLL0_ACTRL6_MAGIC;
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
|
||||
|
||||
/* Wait for PHY PLL lock by polling pll_lock bit */
|
||||
try = 50;
|
||||
do {
|
||||
val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
|
||||
val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
|
||||
BLOCK0_XGXSSTATUS);
|
||||
if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
|
||||
break;
|
||||
|
|
@ -581,7 +565,7 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
|
|||
}
|
||||
|
||||
/* Invert Tx polarity */
|
||||
brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0,
|
||||
brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
|
||||
~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
|
||||
|
||||
/* Configure OOB control to handle 100MHz reference clock */
|
||||
|
|
@ -589,52 +573,51 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
|
|||
(0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
|
||||
(0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
|
||||
(0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
|
||||
brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
|
||||
brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
|
||||
val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
|
||||
(0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
|
||||
(0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
|
||||
brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
|
||||
brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcm_dsl_sata_init(struct brcm_sata_port *port)
|
||||
{
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
struct device *dev = port->phy_priv->dev;
|
||||
unsigned int try;
|
||||
u32 tmp;
|
||||
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
|
||||
brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
0, 0x3089);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
|
||||
0, 0x3088);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
|
||||
brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
|
||||
0, 0x3000);
|
||||
|
||||
brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
|
||||
brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
|
||||
0, 0x3000);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
|
||||
|
||||
brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
|
||||
brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
|
||||
usleep_range(1000, 2000);
|
||||
|
||||
/* Acquire PLL lock */
|
||||
try = 50;
|
||||
while (try) {
|
||||
tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
|
||||
tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
|
||||
BLOCK0_XGXSSTATUS);
|
||||
if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
|
||||
break;
|
||||
|
|
@ -687,10 +670,9 @@ static int brcm_sata_phy_init(struct phy *phy)
|
|||
|
||||
static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
|
||||
{
|
||||
void __iomem *base = brcm_sata_pcb_base(port);
|
||||
u32 tmp = BIT(8);
|
||||
|
||||
brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
|
||||
brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
|
||||
~tmp, tmp);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */
|
||||
#define PHY_MDM6600_ENABLED_DELAY_MS 8000 /* 8s more total for MDM6600 */
|
||||
#define PHY_MDM6600_WAKE_KICK_MS 600 /* time on after GPIO toggle */
|
||||
#define MDM6600_MODEM_IDLE_DELAY_MS 1000 /* modem after USB suspend */
|
||||
#define MDM6600_MODEM_WAKE_DELAY_MS 200 /* modem response after idle */
|
||||
|
||||
|
|
@ -243,10 +244,24 @@ static irqreturn_t phy_mdm6600_wakeirq_thread(int irq, void *data)
|
|||
{
|
||||
struct phy_mdm6600 *ddata = data;
|
||||
struct gpio_desc *mode_gpio1;
|
||||
int error, wakeup;
|
||||
|
||||
mode_gpio1 = ddata->mode_gpios->desc[PHY_MDM6600_MODE1];
|
||||
dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n",
|
||||
gpiod_get_value(mode_gpio1));
|
||||
wakeup = gpiod_get_value(mode_gpio1);
|
||||
if (!wakeup)
|
||||
return IRQ_NONE;
|
||||
|
||||
dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n", wakeup);
|
||||
error = pm_runtime_get_sync(ddata->dev);
|
||||
if (error < 0) {
|
||||
pm_runtime_put_noidle(ddata->dev);
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
/* Just wake-up and kick the autosuspend timer */
|
||||
pm_runtime_mark_last_busy(ddata->dev);
|
||||
pm_runtime_put_autosuspend(ddata->dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
@ -496,8 +511,14 @@ static void phy_mdm6600_modem_wake(struct work_struct *work)
|
|||
|
||||
ddata = container_of(work, struct phy_mdm6600, modem_wake_work.work);
|
||||
phy_mdm6600_wake_modem(ddata);
|
||||
|
||||
/*
|
||||
* The modem does not always stay awake 1.2 seconds after toggling
|
||||
* the wake GPIO, and sometimes it idles after about some 600 ms
|
||||
* making writes time out.
|
||||
*/
|
||||
schedule_delayed_work(&ddata->modem_wake_work,
|
||||
msecs_to_jiffies(MDM6600_MODEM_IDLE_DELAY_MS));
|
||||
msecs_to_jiffies(PHY_MDM6600_WAKE_KICK_MS));
|
||||
}
|
||||
|
||||
static int __maybe_unused phy_mdm6600_runtime_suspend(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -688,11 +688,9 @@ struct phy *phy_get(struct device *dev, const char *string)
|
|||
get_device(&phy->dev);
|
||||
|
||||
link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
|
||||
if (!link) {
|
||||
dev_err(dev, "failed to create device link to %s\n",
|
||||
if (!link)
|
||||
dev_dbg(dev, "failed to create device link to %s\n",
|
||||
dev_name(phy->dev.parent));
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
|
@ -803,11 +801,9 @@ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
|
|||
}
|
||||
|
||||
link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
|
||||
if (!link) {
|
||||
dev_err(dev, "failed to create device link to %s\n",
|
||||
if (!link)
|
||||
dev_dbg(dev, "failed to create device link to %s\n",
|
||||
dev_name(phy->dev.parent));
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
|
@ -852,11 +848,9 @@ struct phy *devm_of_phy_get_by_index(struct device *dev, struct device_node *np,
|
|||
devres_add(dev, ptr);
|
||||
|
||||
link = device_link_add(dev, &phy->dev, DL_FLAG_STATELESS);
|
||||
if (!link) {
|
||||
dev_err(dev, "failed to create device link to %s\n",
|
||||
if (!link)
|
||||
dev_dbg(dev, "failed to create device link to %s\n",
|
||||
dev_name(phy->dev.parent));
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -80,20 +80,20 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
|
|||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
mode = AM33XX_GMII_SEL_MODE_MII;
|
||||
case PHY_INTERFACE_MODE_GMII:
|
||||
gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_warn(dev,
|
||||
"port%u: unsupported mode: \"%s\". Defaulting to MII.\n",
|
||||
if_phy->id, phy_modes(rgmii_id));
|
||||
dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
|
||||
if_phy->id, phy_modes(submode));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if_phy->phy_if_mode = submode;
|
||||
|
||||
dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
|
||||
__func__, if_phy->id, mode, rgmii_id,
|
||||
__func__, if_phy->id, submode, rgmii_id,
|
||||
if_phy->rmii_clock_external);
|
||||
|
||||
regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];
|
||||
|
|
|
|||
|
|
@ -2550,7 +2550,7 @@ found:
|
|||
/* Update ring only if removed request is on pending_req_list list */
|
||||
if (req_on_hw_ring) {
|
||||
link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +
|
||||
(priv_req->start_trb * TRB_SIZE));
|
||||
((priv_req->end_trb + 1) * TRB_SIZE));
|
||||
link_trb->control = (link_trb->control & TRB_CYCLE) |
|
||||
TRB_TYPE(TRB_LINK) | TRB_CHAIN;
|
||||
|
||||
|
|
@ -2595,11 +2595,21 @@ int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep)
|
|||
{
|
||||
struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
|
||||
struct usb_request *request;
|
||||
struct cdns3_request *priv_req;
|
||||
struct cdns3_trb *trb = NULL;
|
||||
int ret;
|
||||
int val;
|
||||
|
||||
trace_cdns3_halt(priv_ep, 0, 0);
|
||||
|
||||
request = cdns3_next_request(&priv_ep->pending_req_list);
|
||||
if (request) {
|
||||
priv_req = to_cdns3_request(request);
|
||||
trb = priv_req->trb;
|
||||
if (trb)
|
||||
trb->control = trb->control ^ TRB_CYCLE;
|
||||
}
|
||||
|
||||
writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
|
||||
|
||||
/* wait for EPRST cleared */
|
||||
|
|
@ -2610,10 +2620,11 @@ int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep)
|
|||
|
||||
priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING);
|
||||
|
||||
request = cdns3_next_request(&priv_ep->pending_req_list);
|
||||
|
||||
if (request)
|
||||
if (request) {
|
||||
if (trb)
|
||||
trb->control = trb->control ^ TRB_CYCLE;
|
||||
cdns3_rearm_transfer(priv_ep, 1);
|
||||
}
|
||||
|
||||
cdns3_start_all_request(priv_dev, priv_ep);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -988,13 +988,17 @@ int usb_remove_device(struct usb_device *udev)
|
|||
{
|
||||
struct usb_hub *hub;
|
||||
struct usb_interface *intf;
|
||||
int ret;
|
||||
|
||||
if (!udev->parent) /* Can't remove a root hub */
|
||||
return -EINVAL;
|
||||
hub = usb_hub_to_struct_hub(udev->parent);
|
||||
intf = to_usb_interface(hub->intfdev);
|
||||
|
||||
usb_autopm_get_interface(intf);
|
||||
ret = usb_autopm_get_interface(intf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
set_bit(udev->portnum, hub->removed_bits);
|
||||
hub_port_logical_disconnect(hub, udev->portnum);
|
||||
usb_autopm_put_interface(intf);
|
||||
|
|
@ -1866,7 +1870,7 @@ static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
|
|||
|
||||
if (id->driver_info & HUB_QUIRK_DISABLE_AUTOSUSPEND) {
|
||||
hub->quirk_disable_autosuspend = 1;
|
||||
usb_autopm_get_interface(intf);
|
||||
usb_autopm_get_interface_no_resume(intf);
|
||||
}
|
||||
|
||||
if (hub_configure(hub, &desc->endpoint[0].desc) >= 0)
|
||||
|
|
|
|||
|
|
@ -213,7 +213,10 @@ static int usb_port_runtime_resume(struct device *dev)
|
|||
if (!port_dev->is_superspeed && peer)
|
||||
pm_runtime_get_sync(&peer->dev);
|
||||
|
||||
usb_autopm_get_interface(intf);
|
||||
retval = usb_autopm_get_interface(intf);
|
||||
if (retval < 0)
|
||||
return retval;
|
||||
|
||||
retval = usb_hub_set_port_power(hdev, hub, port1, true);
|
||||
msleep(hub_power_on_good_delay(hub));
|
||||
if (udev && !retval) {
|
||||
|
|
@ -266,7 +269,10 @@ static int usb_port_runtime_suspend(struct device *dev)
|
|||
if (usb_port_block_power_off)
|
||||
return -EBUSY;
|
||||
|
||||
usb_autopm_get_interface(intf);
|
||||
retval = usb_autopm_get_interface(intf);
|
||||
if (retval < 0)
|
||||
return retval;
|
||||
|
||||
retval = usb_hub_set_port_power(hdev, hub, port1, false);
|
||||
usb_clear_port_feature(hdev, port1, USB_PORT_FEAT_C_CONNECTION);
|
||||
if (!port_dev->is_superspeed)
|
||||
|
|
|
|||
|
|
@ -231,6 +231,9 @@ static const struct usb_device_id usb_quirk_list[] = {
|
|||
/* Logitech PTZ Pro Camera */
|
||||
{ USB_DEVICE(0x046d, 0x0853), .driver_info = USB_QUIRK_DELAY_INIT },
|
||||
|
||||
/* Logitech Screen Share */
|
||||
{ USB_DEVICE(0x046d, 0x086c), .driver_info = USB_QUIRK_NO_LPM },
|
||||
|
||||
/* Logitech Quickcam Fusion */
|
||||
{ USB_DEVICE(0x046d, 0x08c1), .driver_info = USB_QUIRK_RESET_RESUME },
|
||||
|
||||
|
|
|
|||
|
|
@ -1071,7 +1071,14 @@ static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
|
|||
unsigned int rem = length % maxp;
|
||||
unsigned chain = true;
|
||||
|
||||
if (sg_is_last(s))
|
||||
/*
|
||||
* IOMMU driver is coalescing the list of sgs which shares a
|
||||
* page boundary into one and giving it to USB driver. With
|
||||
* this the number of sgs mapped is not equal to the number of
|
||||
* sgs passed. So mark the chain bit to false if it isthe last
|
||||
* mapped sg.
|
||||
*/
|
||||
if (i == remaining - 1)
|
||||
chain = false;
|
||||
|
||||
if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
|
||||
|
|
|
|||
|
|
@ -424,10 +424,6 @@ static int usb251xb_get_ofdata(struct usb251xb *hub,
|
|||
return err;
|
||||
}
|
||||
|
||||
hub->vdd = devm_regulator_get(dev, "vdd");
|
||||
if (IS_ERR(hub->vdd))
|
||||
return PTR_ERR(hub->vdd);
|
||||
|
||||
if (of_property_read_u16_array(np, "vendor-id", &hub->vendor_id, 1))
|
||||
hub->vendor_id = USB251XB_DEF_VENDOR_ID;
|
||||
|
||||
|
|
@ -640,6 +636,13 @@ static int usb251xb_get_ofdata(struct usb251xb *hub,
|
|||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
static void usb251xb_regulator_disable_action(void *data)
|
||||
{
|
||||
struct usb251xb *hub = data;
|
||||
|
||||
regulator_disable(hub->vdd);
|
||||
}
|
||||
|
||||
static int usb251xb_probe(struct usb251xb *hub)
|
||||
{
|
||||
struct device *dev = hub->dev;
|
||||
|
|
@ -676,10 +679,19 @@ static int usb251xb_probe(struct usb251xb *hub)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
hub->vdd = devm_regulator_get(dev, "vdd");
|
||||
if (IS_ERR(hub->vdd))
|
||||
return PTR_ERR(hub->vdd);
|
||||
|
||||
err = regulator_enable(hub->vdd);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = devm_add_action_or_reset(dev,
|
||||
usb251xb_regulator_disable_action, hub);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = usb251xb_connect(hub);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed to connect hub (%d)\n", err);
|
||||
|
|
|
|||
|
|
@ -1258,6 +1258,12 @@ UNUSUAL_DEV( 0x090a, 0x1200, 0x0000, 0x9999,
|
|||
USB_SC_RBC, USB_PR_BULK, NULL,
|
||||
0 ),
|
||||
|
||||
UNUSUAL_DEV(0x090c, 0x1000, 0x1100, 0x1100,
|
||||
"Samsung",
|
||||
"Flash Drive FIT",
|
||||
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
|
||||
US_FL_MAX_SECTORS_64),
|
||||
|
||||
/* aeb */
|
||||
UNUSUAL_DEV( 0x090c, 0x1132, 0x0000, 0xffff,
|
||||
"Feiya",
|
||||
|
|
|
|||
Loading…
Reference in a new issue