xen/pciback: guest SR-IOV support for PV guest
These changes are for PV guest to use Virtual Function. Because the VF's vendor, device registers in cfg space are 0xffff, which are invalid and ignored by PCI device scan. Values in 'struct pci_dev' are fixed up by SR-IOV code, and using these values will present correct VID and DID to PV guest kernel. And command registers in the cfg space are read only 0, which means we have to emulate MMIO enable bit (VF only uses MMIO resource) so PV kernel can work properly. Acked-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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@ -18,6 +18,25 @@ struct pci_bar_info {
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#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
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#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
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static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
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{
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int i;
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int ret;
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ret = pciback_read_config_word(dev, offset, value, data);
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if (!atomic_read(&dev->enable_cnt))
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return ret;
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for (i = 0; i < PCI_ROM_RESOURCE; i++) {
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if (dev->resource[i].flags & IORESOURCE_IO)
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*value |= PCI_COMMAND_IO;
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if (dev->resource[i].flags & IORESOURCE_MEM)
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*value |= PCI_COMMAND_MEMORY;
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}
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return ret;
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}
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static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
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{
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int err;
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@ -142,10 +161,26 @@ static inline void read_dev_bar(struct pci_dev *dev,
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struct pci_bar_info *bar_info, int offset,
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u32 len_mask)
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{
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pci_read_config_dword(dev, offset, &bar_info->val);
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pci_write_config_dword(dev, offset, len_mask);
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pci_read_config_dword(dev, offset, &bar_info->len_val);
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pci_write_config_dword(dev, offset, bar_info->val);
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int pos;
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struct resource *res = dev->resource;
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if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
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pos = PCI_ROM_RESOURCE;
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else {
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pos = (offset - PCI_BASE_ADDRESS_0) / 4;
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if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE |
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PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64))) {
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bar_info->val = res[pos - 1].start >> 32;
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bar_info->len_val = res[pos - 1].end >> 32;
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return;
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}
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}
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bar_info->val = res[pos].start |
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(res[pos].flags & PCI_REGION_FLAG_MASK);
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bar_info->len_val = res[pos].end - res[pos].start + 1;
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}
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static void *bar_init(struct pci_dev *dev, int offset)
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@ -186,6 +221,22 @@ static void bar_release(struct pci_dev *dev, int offset, void *data)
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kfree(data);
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}
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static int pciback_read_vendor(struct pci_dev *dev, int offset,
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u16 *value, void *data)
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{
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*value = dev->vendor;
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return 0;
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}
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static int pciback_read_device(struct pci_dev *dev, int offset,
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u16 *value, void *data)
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{
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*value = dev->device;
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return 0;
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}
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static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
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void *data)
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{
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@ -212,10 +263,20 @@ out:
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}
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static const struct config_field header_common[] = {
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{
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.offset = PCI_VENDOR_ID,
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.size = 2,
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.u.w.read = pciback_read_vendor,
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},
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{
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.offset = PCI_DEVICE_ID,
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.size = 2,
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.u.w.read = pciback_read_device,
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},
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{
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.offset = PCI_COMMAND,
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.size = 2,
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.u.w.read = pciback_read_config_word,
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.u.w.read = command_read,
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.u.w.write = command_write,
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},
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{
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