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iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG 

This is a 32-bit register. Apparently harmless on real hardware, but
causing justified warnings in simulation.

Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org
hifive-unleashed-5.1
CQ Tang 2016-01-13 21:15:03 +00:00 committed by David Woodhouse
parent e57e58bd39
commit fda3bec12d
2 changed files with 2 additions and 2 deletions
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2
drivers/iommu/dmar.c
View File

@ -1347,7 +1347,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
raw_spin_lock_irqsave(&iommu->register_lock, flags);
sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
sts = readl(iommu->reg + DMAR_GSTS_REG);
if (!(sts & DMA_GSTS_QIES))
goto end;

2
drivers/iommu/intel_irq_remapping.c
View File

@ -629,7 +629,7 @@ static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
raw_spin_lock_irqsave(&iommu->register_lock, flags);
sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
sts = readl(iommu->reg + DMAR_GSTS_REG);
if (!(sts & DMA_GSTS_IRES))
goto end;