serial/8250: Add support for NI-Serial PXI/PXIe+485 devices
Add support for NI-Serial PXIe-RS232, PXI-RS485 and PXIe-RS485 devices. Signed-off-by: Je Yen Tam <je.yen.tam@ni.com> Link: https://lore.kernel.org/r/20190726074012.2590-1-je.yen.tam@ni.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>alistair/sunxi64-5.4-dsi
Je Yen Tam
Greg Kroah-Hartman
parent
fe94347d6d
commit
fdc2de8712
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@ -730,8 +730,16 @@ static int pci_ni8430_init(struct pci_dev *dev)
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}
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/* UART Port Control Register */
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#define NI8430_PORTCON 0x0f
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#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
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#define NI16550_PCR_OFFSET 0x0f
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#define NI16550_PCR_RS422 0x00
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#define NI16550_PCR_ECHO_RS485 0x01
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#define NI16550_PCR_DTR_RS485 0x02
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#define NI16550_PCR_AUTO_RS485 0x03
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#define NI16550_PCR_WIRE_MODE_MASK 0x03
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#define NI16550_PCR_TXVR_ENABLE_BIT BIT(3)
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#define NI16550_PCR_RS485_TERMINATION_BIT BIT(6)
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#define NI16550_ACR_DTR_AUTO_DTR (0x2 << 3)
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#define NI16550_ACR_DTR_MANUAL_DTR (0x0 << 3)
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static int
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pci_ni8430_setup(struct serial_private *priv,
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@ -753,14 +761,117 @@ pci_ni8430_setup(struct serial_private *priv,
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return -ENOMEM;
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/* enable the transceiver */
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writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
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p + offset + NI8430_PORTCON);
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writeb(readb(p + offset + NI16550_PCR_OFFSET) | NI16550_PCR_TXVR_ENABLE_BIT,
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p + offset + NI16550_PCR_OFFSET);
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iounmap(p);
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return setup_port(priv, port, bar, offset, board->reg_shift);
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}
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static int pci_ni8431_config_rs485(struct uart_port *port,
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struct serial_rs485 *rs485)
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{
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u8 pcr, acr;
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struct uart_8250_port *up;
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up = container_of(port, struct uart_8250_port, port);
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acr = up->acr;
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pcr = port->serial_in(port, NI16550_PCR_OFFSET);
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pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
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if (rs485->flags & SER_RS485_ENABLED) {
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/* RS-485 */
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if ((rs485->flags & SER_RS485_RX_DURING_TX) &&
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(rs485->flags & SER_RS485_RTS_ON_SEND)) {
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dev_dbg(port->dev, "Invalid 2-wire mode\n");
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return -EINVAL;
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}
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if (rs485->flags & SER_RS485_RX_DURING_TX) {
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/* Echo */
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dev_vdbg(port->dev, "2-wire DTR with echo\n");
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pcr |= NI16550_PCR_ECHO_RS485;
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acr |= NI16550_ACR_DTR_MANUAL_DTR;
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} else {
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/* Auto or DTR */
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if (rs485->flags & SER_RS485_RTS_ON_SEND) {
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/* Auto */
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dev_vdbg(port->dev, "2-wire Auto\n");
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pcr |= NI16550_PCR_AUTO_RS485;
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acr |= NI16550_ACR_DTR_AUTO_DTR;
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} else {
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/* DTR-controlled */
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/* No Echo */
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dev_vdbg(port->dev, "2-wire DTR no echo\n");
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pcr |= NI16550_PCR_DTR_RS485;
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acr |= NI16550_ACR_DTR_MANUAL_DTR;
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}
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}
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} else {
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/* RS-422 */
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dev_vdbg(port->dev, "4-wire\n");
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pcr |= NI16550_PCR_RS422;
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acr |= NI16550_ACR_DTR_MANUAL_DTR;
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}
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dev_dbg(port->dev, "write pcr: 0x%08x\n", pcr);
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port->serial_out(port, NI16550_PCR_OFFSET, pcr);
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up->acr = acr;
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port->serial_out(port, UART_SCR, UART_ACR);
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port->serial_out(port, UART_ICR, up->acr);
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/* Update the cache. */
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port->rs485 = *rs485;
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return 0;
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}
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static int pci_ni8431_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *uart, int idx)
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{
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u8 pcr, acr;
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struct pci_dev *dev = priv->dev;
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void __iomem *addr;
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unsigned int bar, offset = board->first_offset;
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if (idx >= board->num_ports)
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return 1;
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bar = FL_GET_BASE(board->flags);
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offset += idx * board->uart_offset;
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addr = pci_ioremap_bar(dev, bar);
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if (!addr)
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return -ENOMEM;
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/* enable the transceiver */
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writeb(readb(addr + NI16550_PCR_OFFSET) | NI16550_PCR_TXVR_ENABLE_BIT,
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addr + NI16550_PCR_OFFSET);
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pcr = readb(addr + NI16550_PCR_OFFSET);
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pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
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/* set wire mode to default RS-422 */
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pcr |= NI16550_PCR_RS422;
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acr = NI16550_ACR_DTR_MANUAL_DTR;
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/* write port configuration to register */
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writeb(pcr, addr + NI16550_PCR_OFFSET);
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/* access and write to UART acr register */
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writeb(UART_ACR, addr + UART_SCR);
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writeb(acr, addr + UART_ICR);
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uart->port.rs485_config = &pci_ni8431_config_rs485;
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iounmap(addr);
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return setup_port(priv, uart, bar, offset, board->reg_shift);
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}
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static int pci_netmos_9900_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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@ -1786,6 +1897,15 @@ pci_wch_ch38x_setup(struct serial_private *priv,
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#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
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#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
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#define PCIE_DEVICE_ID_NI_PXIE8430_2328 0x74C2
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#define PCIE_DEVICE_ID_NI_PXIE8430_23216 0x74C1
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#define PCI_DEVICE_ID_NI_PXI8431_4852 0x7081
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#define PCI_DEVICE_ID_NI_PXI8431_4854 0x70DE
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#define PCI_DEVICE_ID_NI_PXI8431_4858 0x70E3
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#define PCI_DEVICE_ID_NI_PXI8433_4852 0x70E9
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#define PCI_DEVICE_ID_NI_PXI8433_4854 0x70ED
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#define PCIE_DEVICE_ID_NI_PXIE8431_4858 0x74C4
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#define PCIE_DEVICE_ID_NI_PXIE8431_48516 0x74C3
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/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
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@ -2011,6 +2131,87 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.setup = pci_ni8430_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCIE_DEVICE_ID_NI_PXIE8430_2328,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8430_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCIE_DEVICE_ID_NI_PXIE8430_23216,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8430_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCI_DEVICE_ID_NI_PXI8431_4852,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8431_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCI_DEVICE_ID_NI_PXI8431_4854,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8431_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCI_DEVICE_ID_NI_PXI8431_4858,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8431_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCI_DEVICE_ID_NI_PXI8433_4852,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8431_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCI_DEVICE_ID_NI_PXI8433_4854,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8431_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCIE_DEVICE_ID_NI_PXIE8431_4858,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8431_setup,
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.exit = pci_ni8430_exit,
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},
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{
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.vendor = PCI_VENDOR_ID_NI,
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.device = PCIE_DEVICE_ID_NI_PXIE8431_48516,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ni8430_init,
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.setup = pci_ni8431_setup,
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.exit = pci_ni8430_exit,
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},
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/* Quatech */
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{
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.vendor = PCI_VENDOR_ID_QUATECH,
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@ -2740,6 +2941,13 @@ enum pci_board_num_t {
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pbn_ni8430_4,
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pbn_ni8430_8,
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pbn_ni8430_16,
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pbn_ni8430_pxie_8,
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pbn_ni8430_pxie_16,
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pbn_ni8431_2,
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pbn_ni8431_4,
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pbn_ni8431_8,
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pbn_ni8431_pxie_8,
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pbn_ni8431_pxie_16,
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pbn_ADDIDATA_PCIe_1_3906250,
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pbn_ADDIDATA_PCIe_2_3906250,
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pbn_ADDIDATA_PCIe_4_3906250,
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@ -3381,6 +3589,55 @@ static struct pciserial_board pci_boards[] = {
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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[pbn_ni8430_pxie_16] = {
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.flags = FL_BASE0,
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.num_ports = 16,
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.base_baud = 3125000,
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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[pbn_ni8430_pxie_8] = {
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.flags = FL_BASE0,
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.num_ports = 8,
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.base_baud = 3125000,
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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[pbn_ni8431_8] = {
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.flags = FL_BASE0,
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.num_ports = 8,
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.base_baud = 3686400,
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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[pbn_ni8431_4] = {
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.flags = FL_BASE0,
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.num_ports = 4,
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.base_baud = 3686400,
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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[pbn_ni8431_2] = {
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.flags = FL_BASE0,
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.num_ports = 2,
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.base_baud = 3686400,
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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[pbn_ni8431_pxie_16] = {
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.flags = FL_BASE0,
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.num_ports = 16,
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.base_baud = 3125000,
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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[pbn_ni8431_pxie_8] = {
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.flags = FL_BASE0,
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.num_ports = 8,
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.base_baud = 3125000,
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.uart_offset = 0x10,
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.first_offset = 0x800,
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},
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/*
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* ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
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*/
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@ -5063,6 +5320,33 @@ static const struct pci_device_id serial_pci_tbl[] = {
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{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8430_4 },
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{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8430_2328,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8430_pxie_8 },
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{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8430_23216,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8430_pxie_16 },
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{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4852,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8431_2 },
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{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4854,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8431_4 },
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{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4858,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8431_8 },
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{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8431_4858,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8431_pxie_8 },
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{ PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8431_48516,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8431_pxie_16 },
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{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8433_4852,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8431_2 },
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{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8433_4854,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ni8431_4 },
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/*
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* ADDI-DATA GmbH communication cards <info@addi-data.com>
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