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Merge branches 'pxa-misc', 'pxa-pwm' and 'pxa-multi' into pxa

hifive-unleashed-5.1
Russell King 2008-07-09 20:56:05 +01:00 committed by Russell King
parent bdb08cb2d3 c0f7edb309 9fc697b0b0
commit fdc614e873
49 changed files with 2202 additions and 2347 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/Kconfig
View File

@ -22,6 +22,9 @@ config ARM
Europe. There is an ARM Linux project with a web page at
<http://www.arm.linux.org.uk/>.
config HAVE_PWM
bool
config SYS_SUPPORTS_APM_EMULATION
bool

3
arch/arm/common/sharpsl_pm.c
View File

@ -31,6 +31,7 @@
#include <asm/irq.h>
#include <asm/arch/pm.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/sharpsl.h>
#include <asm/hardware/sharpsl_pm.h>
@ -157,6 +158,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
#ifdef CONFIG_BACKLIGHT_CORGI
/* If battery is low. limit backlight intensity to save power. */
if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
&& ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) ||
@ -169,6 +171,7 @@ static void sharpsl_battery_thread(struct work_struct *private_)
sharpsl_pm.machinfo->backlight_limit(0);
sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
}
#endif
/* Suspend if critical battery level */
if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)

1265
arch/arm/configs/em_x270_defconfig
View File

File diff suppressed because it is too large Load Diff

874
arch/arm/configs/cm_x270_defconfig → arch/arm/configs/xm_x270_defconfig
View File

File diff suppressed because it is too large Load Diff

59
arch/arm/mach-pxa/Kconfig
View File

@ -20,8 +20,7 @@ endmenu
endif
choice
prompt "Select target board"
menu "Select target boards"
config ARCH_GUMSTIX
bool "Gumstix XScale boards"
@ -37,10 +36,12 @@ config ARCH_LUBBOCK
config MACH_LOGICPD_PXA270
bool "LogicPD PXA270 Card Engine Development Platform"
select PXA27x
select HAVE_PWM
config MACH_MAINSTONE
bool "Intel HCDDBBVA0 Development Platform"
select PXA27x
select HAVE_PWM
config ARCH_PXA_IDP
bool "Accelent Xscale IDP"
@ -116,6 +117,7 @@ config MACH_COLIBRI
config MACH_ZYLONITE
bool "PXA3xx Development Platform"
select PXA3xx
select HAVE_PWM
config MACH_LITTLETON
bool "PXA3xx Form Factor Platform (aka Littleton)"
@ -138,7 +140,7 @@ config MACH_PCM027
select PXA27x
select IWMMXT
endchoice
endmenu
choice
prompt "Used baseboard"
@ -146,26 +148,25 @@ choice
config MACH_PCM990_BASEBOARD
bool "PHYTEC PCM-990 development board"
select HAVE_PWM
endchoice
if PXA_SHARPSL
choice
prompt "Select target Sharp Zaurus device range"
prompt "display on pcm990"
depends on MACH_PCM990_BASEBOARD
config PXA_SHARPSL_25x
bool "Sharp PXA25x models (SL-5600, SL-C7xx and SL-C6000x)"
select PXA25x
config PCM990_DISPLAY_SHARP
bool "sharp lq084v1dg21 stn display"
config PXA_SHARPSL_27x
bool "Sharp PXA270 models (SL-Cxx00)"
select PXA27x
config PCM990_DISPLAY_NEC
bool "nec nl6448bc20_18d tft display"
config PCM990_DISPLAY_NONE
bool "no display"
endchoice
endif
if ARCH_GUMSTIX
choice
@ -199,28 +200,33 @@ endmenu
config MACH_POODLE
bool "Enable Sharp SL-5600 (Poodle) Support"
depends on PXA_SHARPSL_25x
depends on PXA_SHARPSL
select PXA25x
select SHARP_LOCOMO
select PXA_SSP
config MACH_CORGI
bool "Enable Sharp SL-C700 (Corgi) Support"
depends on PXA_SHARPSL_25x
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_SHEPHERD
bool "Enable Sharp SL-C750 (Shepherd) Support"
depends on PXA_SHARPSL_25x
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_HUSKY
bool "Enable Sharp SL-C760 (Husky) Support"
depends on PXA_SHARPSL_25x
depends on PXA_SHARPSL
select PXA25x
select PXA_SHARP_C7xx
config MACH_AKITA
bool "Enable Sharp SL-1000 (Akita) Support"
depends on PXA_SHARPSL_27x
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
select MACH_SPITZ
select I2C
@ -228,17 +234,20 @@ config MACH_AKITA
config MACH_SPITZ
bool "Enable Sharp Zaurus SL-3000 (Spitz) Support"
depends on PXA_SHARPSL_27x
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
config MACH_BORZOI
bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support"
depends on PXA_SHARPSL_27x
depends on PXA_SHARPSL
select PXA27x
select PXA_SHARP_Cxx00
config MACH_TOSA
bool "Enable Sharp SL-6000x (Tosa) Support"
depends on PXA_SHARPSL_25x
depends on PXA_SHARPSL
select PXA25x
config PXA25x
bool
@ -273,4 +282,10 @@ config PXA_SSP
tristate
help
Enable support for PXA2xx SSP ports
config PXA_PWM
tristate
default BACKLIGHT_PWM
help
Enable support for PXA2xx/PXA3xx PWM controllers
endif

1
arch/arm/mach-pxa/Makefile
View File

@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
# Generic drivers that other drivers may depend upon
obj-$(CONFIG_PXA_SSP) += ssp.o
obj-$(CONFIG_PXA_PWM) += pwm.o
# SoC-specific code
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o

2
arch/arm/mach-pxa/clock.c
View File

@ -12,7 +12,7 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/hardware.h>

22
arch/arm/mach-pxa/cm-x270-pci.c
View File

@ -41,18 +41,20 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
{
unsigned int sz = SZ_64M >> PAGE_SHIFT;
pr_info("Adjusting zones for CM-x270\n");
if (machine_is_armcore()) {
pr_info("Adjusting zones for CM-x270\n");
/*
* Only adjust if > 64M on current system
*/
if (node || (zone_size[0] <= sz))
return;
/*
* Only adjust if > 64M on current system
*/
if (node || (zone_size[0] <= sz))
return;
zone_size[1] = zone_size[0] - sz;
zone_size[0] = sz;
zhole_size[1] = zhole_size[0];
zhole_size[0] = 0;
zone_size[1] = zone_size[0] - sz;
zone_size[0] = sz;
zhole_size[1] = zhole_size[0];
zhole_size[0] = 0;
}
}
static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)

1
arch/arm/mach-pxa/corgi.c
View File

@ -36,6 +36,7 @@
#include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/irda.h>
#include <asm/arch/mmc.h>

7
arch/arm/mach-pxa/corgi_pm.c
View File

@ -26,6 +26,7 @@
#include <asm/arch/sharpsl.h>
#include <asm/arch/corgi.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include "sharpsl.h"
@ -204,7 +205,9 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
.read_devdata = corgipm_read_devdata,
.charger_wakeup = corgi_charger_wakeup,
.should_wakeup = corgi_should_wakeup,
#ifdef CONFIG_BACKLIGHT_CORGI
.backlight_limit = corgibl_limit_intensity,
#endif
.charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
.charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
.charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@ -226,6 +229,10 @@ static int __devinit corgipm_init(void)
{
int ret;
if (!machine_is_corgi() && !machine_is_shepherd()
&& !machine_is_husky())
return -ENODEV;
corgipm_device = platform_device_alloc("sharpsl-pm", -1);
if (!corgipm_device)
return -ENOMEM;

69
arch/arm/mach-pxa/devices.c
View File

@ -10,11 +10,13 @@
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/i2c.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pxa27x_keypad.h>
#include <asm/arch/camera.h>
#include "devices.h"
#include "generic.h"
void __init pxa_register_device(struct platform_device *dev, void *data)
{
@ -233,8 +235,15 @@ struct platform_device pxa_device_i2c = {
.num_resources = ARRAY_SIZE(pxai2c_resources),
};
static unsigned long pxa27x_i2c_mfp_cfg[] = {
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
};
void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
{
if (cpu_is_pxa27x())
pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
pxa_register_device(&pxa_device_i2c, info);
}
@ -280,6 +289,36 @@ struct platform_device pxa_device_rtc = {
#ifdef CONFIG_PXA25x
static struct resource pxa25x_resource_pwm0[] = {
[0] = {
.start = 0x40b00000,
.end = 0x40b0000f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa25x_device_pwm0 = {
.name = "pxa25x-pwm",
.id = 0,
.resource = pxa25x_resource_pwm0,
.num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
};
static struct resource pxa25x_resource_pwm1[] = {
[0] = {
.start = 0x40c00000,
.end = 0x40c0000f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa25x_device_pwm1 = {
.name = "pxa25x-pwm",
.id = 1,
.resource = pxa25x_resource_pwm1,
.num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
};
static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa25x_resource_ssp[] = {
@ -568,6 +607,36 @@ struct platform_device pxa27x_device_ssp3 = {
.num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
};
static struct resource pxa27x_resource_pwm0[] = {
[0] = {
.start = 0x40b00000,
.end = 0x40b0001f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa27x_device_pwm0 = {
.name = "pxa27x-pwm",
.id = 0,
.resource = pxa27x_resource_pwm0,
.num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
};
static struct resource pxa27x_resource_pwm1[] = {
[0] = {
.start = 0x40c00000,
.end = 0x40c0001f,
.flags = IORESOURCE_MEM,
},
};
struct platform_device pxa27x_device_pwm1 = {
.name = "pxa27x-pwm",
.id = 1,
.resource = pxa27x_resource_pwm1,
.num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
};
static struct resource pxa27x_resource_camera[] = {
[0] = {
.start = 0x50000000,

5
arch/arm/mach-pxa/devices.h
View File

@ -24,4 +24,9 @@ extern struct platform_device pxa27x_device_ssp2;
extern struct platform_device pxa27x_device_ssp3;
extern struct platform_device pxa3xx_device_ssp4;
extern struct platform_device pxa25x_device_pwm0;
extern struct platform_device pxa25x_device_pwm1;
extern struct platform_device pxa27x_device_pwm0;
extern struct platform_device pxa27x_device_pwm1;
void __init pxa_register_device(struct platform_device *dev, void *data);

1
arch/arm/mach-pxa/em-x270.c
View File

@ -24,6 +24,7 @@
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/pxa27x-udc.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/ohci.h>
#include <asm/arch/mmc.h>

1
arch/arm/mach-pxa/generic.c
View File

@ -26,6 +26,7 @@
#include <asm/mach/map.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h> /* for __pxa_set_cken */
#include "generic.h"

47
arch/arm/mach-pxa/lpd270.c
View File

@ -23,6 +23,7 @@
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/pwm_backlight.h>
#include <asm/types.h>
#include <asm/setup.h>
@ -134,9 +135,12 @@ static struct sys_device lpd270_irq_device = {
static int __init lpd270_irq_device_init(void)
{
int ret = sysdev_class_register(&lpd270_irq_sysclass);
if (ret == 0)
ret = sysdev_register(&lpd270_irq_device);
int ret = -ENODEV;
if (machine_is_logicpd_pxa270()) {
ret = sysdev_class_register(&lpd270_irq_sysclass);
if (ret == 0)
ret = sysdev_register(&lpd270_irq_device);
}
return ret;
}
@ -233,21 +237,20 @@ static struct platform_device lpd270_flash_device[2] = {
},
};
static void lpd270_backlight_power(int on)
{
if (on) {
pxa_gpio_mode(GPIO16_PWM0_MD);
pxa_set_cken(CKEN_PWM0, 1);
PWM_CTRL0 = 0;
PWM_PWDUTY0 = 0x3ff;
PWM_PERVAL0 = 0x3ff;
} else {
PWM_CTRL0 = 0;
PWM_PWDUTY0 = 0x0;
PWM_PERVAL0 = 0x3FF;
pxa_set_cken(CKEN_PWM0, 0);
}
}
static struct platform_pwm_backlight_data lpd270_backlight_data = {
.pwm_id = 0,
.max_brightness = 1,
.dft_brightness = 1,
.pwm_period_ns = 78770,
};
static struct platform_device lpd270_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &lpd270_backlight_data,
},
};
/* 5.7" TFT QVGA (LoLo display number 1) */
static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
@ -269,7 +272,6 @@ static struct pxafb_mach_info sharp_lq057q3dc02 = {
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 12.1" TFT SVGA (LoLo display number 2) */
@ -292,7 +294,6 @@ static struct pxafb_mach_info sharp_lq121s1dg31 = {
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 3.6" TFT QVGA (LoLo display number 3) */
@ -315,7 +316,6 @@ static struct pxafb_mach_info sharp_lq036q1da01 = {
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 6.4" TFT VGA (LoLo display number 5) */
@ -338,7 +338,6 @@ static struct pxafb_mach_info sharp_lq64d343 = {
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 10.4" TFT VGA (LoLo display number 7) */
@ -361,7 +360,6 @@ static struct pxafb_mach_info sharp_lq10d368 = {
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
/* 3.5" TFT QVGA (LoLo display number 8) */
@ -384,7 +382,6 @@ static struct pxafb_mach_info sharp_lq035q7db02_20 = {
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.pxafb_backlight_power = lpd270_backlight_power,
};
static struct pxafb_mach_info *lpd270_lcd_to_use;
@ -414,6 +411,7 @@ __setup("lcd=", lpd270_set_lcd);
static struct platform_device *platform_devices[] __initdata = {
&smc91x_device,
&lpd270_backlight_device,
&lpd270_audio_device,
&lpd270_flash_device[0],
&lpd270_flash_device[1],
@ -454,6 +452,7 @@ static void __init lpd270_init(void)
* On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
*/
pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
pxa_gpio_mode(GPIO16_PWM0_MD);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

69
arch/arm/mach-pxa/magician.c
View File

@ -25,6 +25,7 @@
#include <linux/mtd/map.h>
#include <linux/mtd/physmap.h>
#include <linux/pda_power.h>
#include <linux/pwm_backlight.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
@ -33,12 +34,14 @@
#include <asm/arch/magician.h>
#include <asm/arch/mfp-pxa27x.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/i2c.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>
#include "devices.h"
#include "generic.h"
static unsigned long magician_pin_config[] = {
@ -348,40 +351,58 @@ static struct pxafb_mach_info samsung_info = {
* Backlight
*/
static void magician_set_bl_intensity(int intensity)
static int magician_backlight_init(struct device *dev)
{
if (intensity) {
PWM_CTRL0 = 1;
PWM_PERVAL0 = 0xc8;
if (intensity > 0xc7) {
PWM_PWDUTY0 = intensity - 0x48;
gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
} else {
PWM_PWDUTY0 = intensity;
gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
}
gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1);
pxa_set_cken(CKEN_PWM0, 1);
int ret;
ret = gpio_request(EGPIO_MAGICIAN_BL_POWER, "BL_POWER");
if (ret)
goto err;
ret = gpio_request(EGPIO_MAGICIAN_BL_POWER2, "BL_POWER2");
if (ret)
goto err2;
return 0;
err2:
gpio_free(EGPIO_MAGICIAN_BL_POWER);
err:
return ret;
}
static int magician_backlight_notify(int brightness)
{
gpio_set_value(EGPIO_MAGICIAN_BL_POWER, brightness);
if (brightness >= 200) {
gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
return brightness - 72;
} else {
/* PWM_PWDUTY0 = intensity; */
gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0);
pxa_set_cken(CKEN_PWM0, 0);
gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
return brightness;
}
}
static struct generic_bl_info backlight_info = {
.default_intensity = 0x64,
.limit_mask = 0x0b,
.max_intensity = 0xc7+0x48,
.set_bl_intensity = magician_set_bl_intensity,
static void magician_backlight_exit(struct device *dev)
{
gpio_free(EGPIO_MAGICIAN_BL_POWER);
gpio_free(EGPIO_MAGICIAN_BL_POWER2);
}
static struct platform_pwm_backlight_data backlight_data = {
.pwm_id = 0,
.max_brightness = 272,
.dft_brightness = 100,
.pwm_period_ns = 30923,
.init = magician_backlight_init,
.notify = magician_backlight_notify,
.exit = magician_backlight_exit,
};
static struct platform_device backlight = {
.name = "generic-bl",
.name = "pwm-backlight",
.dev = {
.platform_data = &backlight_info,
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &backlight_data,
},
.id = -1,
};
/*

63
arch/arm/mach-pxa/mainstone.c
View File

@ -23,9 +23,9 @@
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/backlight.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/pwm_backlight.h>
#include <asm/types.h>
#include <asm/setup.h>
@ -349,56 +349,27 @@ static struct platform_device mst_flash_device[2] = {
},
};
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
static int mainstone_backlight_update_status(struct backlight_device *bl)
{
int brightness = bl->props.brightness;
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct platform_pwm_backlight_data mainstone_backlight_data = {
.pwm_id = 0,
.max_brightness = 1023,
.dft_brightness = 1023,
.pwm_period_ns = 78770,
};
if (bl->props.power != FB_BLANK_UNBLANK ||
bl->props.fb_blank != FB_BLANK_UNBLANK)
brightness = 0;
if (brightness != 0)
pxa_set_cken(CKEN_PWM0, 1);
PWM_CTRL0 = 0;
PWM_PWDUTY0 = brightness;
PWM_PERVAL0 = bl->props.max_brightness;
if (brightness == 0)
pxa_set_cken(CKEN_PWM0, 0);
return 0; /* pointless return value */
}
static int mainstone_backlight_get_brightness(struct backlight_device *bl)
{
return PWM_PWDUTY0;
}
static /*const*/ struct backlight_ops mainstone_backlight_ops = {
.update_status = mainstone_backlight_update_status,
.get_brightness = mainstone_backlight_get_brightness,
static struct platform_device mainstone_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &mainstone_backlight_data,
},
};
static void __init mainstone_backlight_register(void)
{
struct backlight_device *bl;
bl = backlight_device_register("mainstone-bl", &pxa_device_fb.dev,
NULL, &mainstone_backlight_ops);
if (IS_ERR(bl)) {
printk(KERN_ERR "mainstone: unable to register backlight: %ld\n",
PTR_ERR(bl));
return;
}
/*
* broken design - register-then-setup interfaces are
* utterly broken by definition.
*/
bl->props.max_brightness = 1023;
bl->props.brightness = 1023;
backlight_update_status(bl);
int ret = platform_device_register(&mainstone_backlight_device);
if (ret)
printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
}
#else
#define mainstone_backlight_register() do { } while (0)

1
arch/arm/mach-pxa/mfp-pxa2xx.c
View File

@ -20,6 +20,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/mfp-pxa2xx.h>
#include "generic.h"

99
arch/arm/mach-pxa/pcm990-baseboard.c
View File

@ -24,6 +24,7 @@
#include <linux/platform_device.h>
#include <linux/ide.h>
#include <linux/i2c.h>
#include <linux/pwm_backlight.h>
#include <media/soc_camera.h>
@ -36,9 +37,99 @@
#include <asm/arch/mmc.h>
#include <asm/arch/ohci.h>
#include <asm/arch/pcm990_baseboard.h>
#include <asm/arch/pxafb.h>
#include "devices.h"
/*
* The PCM-990 development baseboard uses PCM-027's hardeware in the
* pcm990_lcd_power - control power supply to the LCD
* @on: 0 = switch off, 1 = switch on
*
* Called by the pxafb driver
*/
#ifndef CONFIG_PCM990_DISPLAY_NONE
static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
{
if (on) {
/* enable LCD-Latches
* power on LCD
*/
__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) =
PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON;
} else {
/* disable LCD-Latches
* power off LCD
*/
__PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 0x00;
}
}
#endif
#if defined(CONFIG_PCM990_DISPLAY_SHARP)
static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
.pixclock = 28000,
.xres = 640,
.yres = 480,
.bpp = 16,
.hsync_len = 20,
.left_margin = 103,
.right_margin = 47,
.vsync_len = 6,
.upper_margin = 28,
.lower_margin = 5,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info pcm990_fbinfo __initdata = {
.modes = &fb_info_sharp_lq084v1dg21,
.num_modes = 1,
.lccr0 = LCCR0_PAS,
.lccr3 = LCCR3_PCP,
.pxafb_lcd_power = pcm990_lcd_power,
};
#elif defined(CONFIG_PCM990_DISPLAY_NEC)
struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
.pixclock = 39720,
.xres = 640,
.yres = 480,
.bpp = 16,
.hsync_len = 32,
.left_margin = 16,
.right_margin = 48,
.vsync_len = 2,
.upper_margin = 12,
.lower_margin = 17,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info pcm990_fbinfo __initdata = {
.modes = &fb_info_nec_nl6448bc20_18d,
.num_modes = 1,
.lccr0 = LCCR0_Act,
.lccr3 = LCCR3_PixFlEdg,
.pxafb_lcd_power = pcm990_lcd_power,
};
#endif
static struct platform_pwm_backlight_data pcm990_backlight_data = {
.pwm_id = 0,
.max_brightness = 1023,
.dft_brightness = 1023,
.pwm_period_ns = 78770,
};
static struct platform_device pcm990_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm0.dev,
.platform_data = &pcm990_backlight_data,
},
};
/*
* The PCM-990 development baseboard uses PCM-027's hardware in the
* following way:
*
* - LCD support is in use
@ -393,6 +484,12 @@ void __init pcm990_baseboard_init(void)
/* register CPLD's IRQ controller */
pcm990_init_irq();
#ifndef CONFIG_PCM990_DISPLAY_NONE
set_pxa_fb_info(&pcm990_fbinfo);
#endif
pxa_gpio_mode(GPIO16_PWM0_MD);
platform_device_register(&pcm990_backlight_device);
platform_device_register(&pxa27x_device_ac97);
/* MMC */

1
arch/arm/mach-pxa/poodle.c
View File

@ -32,6 +32,7 @@
#include <asm/mach/irq.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/udc.h>

319
arch/arm/mach-pxa/pwm.c 100644
View File

@ -0,0 +1,319 @@
/*
* linux/arch/arm/mach-pxa/pwm.c
*
* simple driver for PWM (Pulse Width Modulator) controller
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* 2008-02-13 initial version
* eric miao <eric.miao@marvell.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/pwm.h>
#include <asm/div64.h>
#include <asm/arch/pxa-regs.h>
/* PWM registers and bits definitions */
#define PWMCR (0x00)
#define PWMDCR (0x04)
#define PWMPCR (0x08)
#define PWMCR_SD (1 << 6)
#define PWMDCR_FD (1 << 10)
struct pwm_device {
struct list_head node;
struct platform_device *pdev;
const char *label;
struct clk *clk;
int clk_enabled;
void __iomem *mmio_base;
unsigned int use_count;
unsigned int pwm_id;
};
/*
* period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
* duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
*/
int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
{
unsigned long long c;
unsigned long period_cycles, prescale, pv, dc;
if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
return -EINVAL;
c = clk_get_rate(pwm->clk);
c = c * period_ns;
do_div(c, 1000000000);
period_cycles = c;
if (period_cycles < 0)
period_cycles = 1;
prescale = (period_cycles - 1) / 1024;
pv = period_cycles / (prescale + 1) - 1;
if (prescale > 63)
return -EINVAL;
if (duty_ns == period_ns)
dc = PWMDCR_FD;
else
dc = (pv + 1) * duty_ns / period_ns;
/* NOTE: the clock to PWM has to be enabled first
* before writing to the registers
*/
clk_enable(pwm->clk);
__raw_writel(prescale, pwm->mmio_base + PWMCR);
__raw_writel(dc, pwm->mmio_base + PWMDCR);
__raw_writel(pv, pwm->mmio_base + PWMPCR);
clk_disable(pwm->clk);
return 0;
}
EXPORT_SYMBOL(pwm_config);
int pwm_enable(struct pwm_device *pwm)
{
int rc = 0;
if (!pwm->clk_enabled) {
rc = clk_enable(pwm->clk);
if (!rc)
pwm->clk_enabled = 1;
}
return rc;
}
EXPORT_SYMBOL(pwm_enable);
void pwm_disable(struct pwm_device *pwm)
{
if (pwm->clk_enabled) {
clk_disable(pwm->clk);
pwm->clk_enabled = 0;
}
}
EXPORT_SYMBOL(pwm_disable);
static DEFINE_MUTEX(pwm_lock);
static LIST_HEAD(pwm_list);
struct pwm_device *pwm_request(int pwm_id, const char *label)
{
struct pwm_device *pwm;
int found = 0;
mutex_lock(&pwm_lock);
list_for_each_entry(pwm, &pwm_list, node) {
if (pwm->pwm_id == pwm_id) {
found = 1;
break;
}
}
if (found) {
if (pwm->use_count == 0) {
pwm->use_count++;
pwm->label = label;
} else
pwm = ERR_PTR(-EBUSY);
} else
pwm = ERR_PTR(-ENOENT);
mutex_unlock(&pwm_lock);
return pwm;
}
EXPORT_SYMBOL(pwm_request);
void pwm_free(struct pwm_device *pwm)
{
mutex_lock(&pwm_lock);
if (pwm->use_count) {
pwm->use_count--;
pwm->label = NULL;
} else
pr_warning("PWM device already freed\n");
mutex_unlock(&pwm_lock);
}
EXPORT_SYMBOL(pwm_free);
static inline void __add_pwm(struct pwm_device *pwm)
{
mutex_lock(&pwm_lock);
list_add_tail(&pwm->node, &pwm_list);
mutex_unlock(&pwm_lock);
}
static struct pwm_device *pwm_probe(struct platform_device *pdev,
unsigned int pwm_id, struct pwm_device *parent_pwm)
{
struct pwm_device *pwm;
struct resource *r;
int ret = 0;
pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
if (pwm == NULL) {
dev_err(&pdev->dev, "failed to allocate memory\n");
return ERR_PTR(-ENOMEM);
}
pwm->clk = clk_get(&pdev->dev, "PWMCLK");
if (IS_ERR(pwm->clk)) {
ret = PTR_ERR(pwm->clk);
goto err_free;
}
pwm->clk_enabled = 0;
pwm->use_count = 0;
pwm->pwm_id = pwm_id;
pwm->pdev = pdev;
if (parent_pwm != NULL) {
/* registers for the second PWM has offset of 0x10 */
pwm->mmio_base = parent_pwm->mmio_base + 0x10;
__add_pwm(pwm);
return pwm;
}
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (r == NULL) {
dev_err(&pdev->dev, "no memory resource defined\n");
ret = -ENODEV;
goto err_free_clk;
}
r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
if (r == NULL) {
dev_err(&pdev->dev, "failed to request memory resource\n");
ret = -EBUSY;
goto err_free_clk;
}
pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
if (pwm->mmio_base == NULL) {
dev_err(&pdev->dev, "failed to ioremap() registers\n");
ret = -ENODEV;
goto err_free_mem;
}
__add_pwm(pwm);
platform_set_drvdata(pdev, pwm);
return pwm;
err_free_mem:
release_mem_region(r->start, r->end - r->start + 1);
err_free_clk:
clk_put(pwm->clk);
err_free:
kfree(pwm);
return ERR_PTR(ret);
}
static int __devinit pxa25x_pwm_probe(struct platform_device *pdev)
{
struct pwm_device *pwm = pwm_probe(pdev, pdev->id, NULL);
if (IS_ERR(pwm))
return PTR_ERR(pwm);
return 0;
}
static int __devinit pxa27x_pwm_probe(struct platform_device *pdev)
{
struct pwm_device *pwm;
pwm = pwm_probe(pdev, pdev->id, NULL);
if (IS_ERR(pwm))
return PTR_ERR(pwm);
pwm = pwm_probe(pdev, pdev->id + 2, pwm);
if (IS_ERR(pwm))
return PTR_ERR(pwm);
return 0;
}
static int __devexit pwm_remove(struct platform_device *pdev)
{
struct pwm_device *pwm;
struct resource *r;
pwm = platform_get_drvdata(pdev);
if (pwm == NULL)
return -ENODEV;
mutex_lock(&pwm_lock);
list_del(&pwm->node);
mutex_unlock(&pwm_lock);
iounmap(pwm->mmio_base);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, r->end - r->start + 1);
clk_put(pwm->clk);
kfree(pwm);
return 0;
}
static struct platform_driver pxa25x_pwm_driver = {
.driver = {
.name = "pxa25x-pwm",
},
.probe = pxa25x_pwm_probe,
.remove = __devexit_p(pwm_remove),
};
static struct platform_driver pxa27x_pwm_driver = {
.driver = {
.name = "pxa27x-pwm",
},
.probe = pxa27x_pwm_probe,
.remove = __devexit_p(pwm_remove),
};
static int __init pwm_init(void)
{
int ret = 0;
ret = platform_driver_register(&pxa25x_pwm_driver);
if (ret) {
printk(KERN_ERR "failed to register pxa25x_pwm_driver\n");
return ret;
}
ret = platform_driver_register(&pxa27x_pwm_driver);
if (ret) {
printk(KERN_ERR "failed to register pxa27x_pwm_driver\n");
return ret;
}
return ret;
}
arch_initcall(pwm_init);
static void __exit pwm_exit(void)
{
platform_driver_unregister(&pxa25x_pwm_driver);
platform_driver_unregister(&pxa27x_pwm_driver);
}
module_exit(pwm_exit);
MODULE_LICENSE("GPL v2");

7
arch/arm/mach-pxa/pxa25x.c
View File

@ -26,6 +26,7 @@
#include <asm/hardware.h>
#include <asm/arch/irqs.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/mfp-pxa25x.h>
#include <asm/arch/pm.h>
#include <asm/arch/dma.h>
@ -133,12 +134,12 @@ static struct clk pxa25x_clks[] = {
INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
/*
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
*/
INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
@ -275,6 +276,8 @@ static struct platform_device *pxa25x_devices[] __initdata = {
&pxa25x_device_ssp,
&pxa25x_device_nssp,
&pxa25x_device_assp,
&pxa25x_device_pwm0,
&pxa25x_device_pwm1,
};
static struct sys_device pxa25x_sysdev[] = {

10
arch/arm/mach-pxa/pxa27x.c
View File

@ -157,12 +157,13 @@ static struct clk pxa27x_clks[] = {
INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
INIT_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
INIT_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
/*
INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
@ -349,11 +350,14 @@ struct platform_device pxa27x_device_i2c_power = {
void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
local_irq_disable();
PCFR |= PCFR_PI2CEN;
local_irq_enable();
pxa27x_device_i2c_power.dev.platform_data = info;
}
static struct platform_device *devices[] __initdata = {
&pxa_device_udc,
/* &pxa_device_udc, The UDC driver is PXA25x only */
&pxa_device_ffuart,
&pxa_device_btuart,
&pxa_device_stuart,
@ -363,6 +367,8 @@ static struct platform_device *devices[] __initdata = {
&pxa27x_device_ssp1,
&pxa27x_device_ssp2,
&pxa27x_device_ssp3,
&pxa27x_device_pwm0,
&pxa27x_device_pwm1,
};
static struct sys_device pxa27x_sysdev[] = {

6
arch/arm/mach-pxa/pxa3xx.c
View File

@ -239,6 +239,8 @@ static struct clk pxa3xx_clks[] = {
PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
PXA3xx_CKEN("PWMCLK", PWM0, 13000000, 0, &pxa27x_device_pwm0.dev),
PXA3xx_CKEN("PWMCLK", PWM1, 13000000, 0, &pxa27x_device_pwm1.dev),
PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
@ -520,7 +522,7 @@ void __init pxa3xx_init_irq(void)
*/
static struct platform_device *devices[] __initdata = {
&pxa_device_udc,
/* &pxa_device_udc, The UDC driver is PXA25x only */
&pxa_device_ffuart,
&pxa_device_btuart,
&pxa_device_stuart,
@ -530,6 +532,8 @@ static struct platform_device *devices[] __initdata = {
&pxa27x_device_ssp2,
&pxa27x_device_ssp3,
&pxa3xx_device_ssp4,
&pxa27x_device_pwm0,
&pxa27x_device_pwm1,
};
static struct sys_device pxa3xx_sysdev[] = {

7
arch/arm/mach-pxa/spitz_pm.c
View File

@ -26,6 +26,7 @@
#include <asm/arch/sharpsl.h>
#include <asm/arch/spitz.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include "sharpsl.h"
@ -207,7 +208,9 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
.read_devdata = spitzpm_read_devdata,
.charger_wakeup = spitz_charger_wakeup,
.should_wakeup = spitz_should_wakeup,
#ifdef CONFIG_BACKLIGHT_CORGI
.backlight_limit = corgibl_limit_intensity,
#endif
.charge_on_volt = SHARPSL_CHARGE_ON_VOLT,
.charge_on_temp = SHARPSL_CHARGE_ON_TEMP,
.charge_acin_high = SHARPSL_CHARGE_ON_ACIN_HIGH,
@ -229,6 +232,10 @@ static int __devinit spitzpm_init(void)
{
int ret;
if (!machine_is_spitz() && !machine_is_akita()
&& !machine_is_borzoi())
return -ENODEV;
spitzpm_device = platform_device_alloc("sharpsl-pm", -1);
if (!spitzpm_device)
return -ENOMEM;

83
arch/arm/mach-pxa/standby.S
View File

@ -14,6 +14,7 @@
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
.text
@ -35,20 +36,20 @@ ENTRY(pxa_cpu_standby)
#ifdef CONFIG_PXA3xx
#define MDCNFG 0x0000
#define MDCNFG_DMCEN (1 << 30)
#define DDR_HCAL 0x0060
#define DDR_HCAL_HCRNG 0x1f
#define DDR_HCAL_HCPROG (1 << 28)
#define DDR_HCAL_HCEN (1 << 31)
#define DMCIER 0x0070
#define DMCIER_EDLP (1 << 29)
#define DMCISR 0x0078
#define RCOMP 0x0100
#define RCOMP_SWEVAL (1 << 31)
#define PXA3_MDCNFG 0x0000
#define PXA3_MDCNFG_DMCEN (1 << 30)
#define PXA3_DDR_HCAL 0x0060
#define PXA3_DDR_HCAL_HCRNG 0x1f
#define PXA3_DDR_HCAL_HCPROG (1 << 28)
#define PXA3_DDR_HCAL_HCEN (1 << 31)
#define PXA3_DMCIER 0x0070
#define PXA3_DMCIER_EDLP (1 << 29)
#define PXA3_DMCISR 0x0078
#define PXA3_RCOMP 0x0100
#define PXA3_RCOMP_SWEVAL (1 << 31)
ENTRY(pm_enter_standby_start)
mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG)
mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
add r1, r1, #0x00100000
/*
@ -59,54 +60,54 @@ ENTRY(pm_enter_standby_start)
* This also means that only the dynamic memory controller
* can be reliably accessed in the code following standby.
*/
ldr r2, [r1] @ Dummy read MDCNFG
ldr r2, [r1] @ Dummy read PXA3_MDCNFG
mcr p14, 0, r0, c7, c0, 0
.rept 8
nop
.endr
ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN
bic r0, r0, #DDR_HCAL_HCEN
str r0, [r1, #DDR_HCAL]
1: ldr r0, [r1, #DDR_HCAL]
tst r0, #DDR_HCAL_HCEN
ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
bic r0, r0, #PXA3_DDR_HCAL_HCEN
str r0, [r1, #PXA3_DDR_HCAL]
1: ldr r0, [r1, #PXA3_DDR_HCAL]
tst r0, #PXA3_DDR_HCAL_HCEN
bne 1b
ldr r0, [r1, #RCOMP] @ Initiate RCOMP
orr r0, r0, #RCOMP_SWEVAL
str r0, [r1, #RCOMP]
ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
orr r0, r0, #PXA3_RCOMP_SWEVAL
str r0, [r1, #PXA3_RCOMP]
mov r0, #~0 @ Clear interrupts
str r0, [r1, #DMCISR]
mov r0, #~0 @ Clear interrupts
str r0, [r1, #PXA3_DMCISR]
ldr r0, [r1, #DMCIER] @ set DMIER[EDLP]
orr r0, r0, #DMCIER_EDLP
str r0, [r1, #DMCIER]
ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
orr r0, r0, #PXA3_DMCIER_EDLP
str r0, [r1, #PXA3_DMCIER]
ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
bic r0, r0, #DDR_HCAL_HCRNG
orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG
str r0, [r1, #DDR_HCAL]
ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
bic r0, r0, #PXA3_DDR_HCAL_HCRNG
orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
str r0, [r1, #PXA3_DDR_HCAL]
1: ldr r0, [r1, #DMCISR]
tst r0, #DMCIER_EDLP
1: ldr r0, [r1, #PXA3_DMCISR]
tst r0, #PXA3_DMCIER_EDLP
beq 1b
ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN]
orr r0, r0, #MDCNFG_DMCEN
str r0, [r1, #MDCNFG]
1: ldr r0, [r1, #MDCNFG]
tst r0, #MDCNFG_DMCEN
ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
orr r0, r0, #PXA3_MDCNFG_DMCEN
str r0, [r1, #PXA3_MDCNFG]
1: ldr r0, [r1, #PXA3_MDCNFG]
tst r0, #PXA3_MDCNFG_DMCEN
beq 1b
ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG]
ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
orr r0, r0, #2 @ HCRNG
str r0, [r1, #DDR_HCAL]
str r0, [r1, #PXA3_DDR_HCAL]
ldr r0, [r1, #DMCIER] @ Clear the interrupt
ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
bic r0, r0, #0x20000000
str r0, [r1, #DMCIER]
str r0, [r1, #PXA3_DMCIER]
mov pc, lr
ENTRY(pm_enter_standby_end)

2
arch/arm/mach-pxa/trizeps4.c
View File

@ -41,6 +41,7 @@
#include <asm/mach/flash.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
#include <asm/arch/trizeps4.h>
#include <asm/arch/audio.h>
@ -487,6 +488,7 @@ static void __init trizeps4_map_io(void)
ConXS_BCR = trizeps_conxs_bcr;
#endif
#warning FIXME - accessing PM registers directly is deprecated
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;

26
arch/arm/mach-pxa/zylonite.c
View File

@ -18,6 +18,7 @@
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pwm_backlight.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -28,12 +29,12 @@
#include <asm/arch/mmc.h>
#include <asm/arch/pxa27x_keypad.h>
#include "devices.h"
#include "generic.h"
#define MAX_SLOTS 3
struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
int gpio_backlight;
int gpio_eth_irq;
int wm9713_irq;
@ -62,10 +63,20 @@ static struct platform_device smc91x_device = {
};
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static void zylonite_backlight_power(int on)
{
gpio_set_value(gpio_backlight, on);
}
static struct platform_pwm_backlight_data zylonite_backlight_data = {
.pwm_id = 3,
.max_brightness = 100,
.dft_brightness = 100,
.pwm_period_ns = 10000,
};
static struct platform_device zylonite_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &pxa27x_device_pwm1.dev,
.platform_data = &zylonite_backlight_data,
},
};
static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
.pixclock = 110000,
@ -98,7 +109,6 @@ static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
.num_modes = 1,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
.pxafb_backlight_power = zylonite_backlight_power,
};
static struct pxafb_mode_info sharp_ls037_modes[] = {
@ -134,13 +144,11 @@ static struct pxafb_mach_info zylonite_sharp_lcd_info = {
.modes = sharp_ls037_modes,
.num_modes = 2,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
.pxafb_backlight_power = zylonite_backlight_power,
};
static void __init zylonite_init_lcd(void)
{
/* backlight GPIO: output, default on */
gpio_direction_output(gpio_backlight, 1);
platform_device_register(&zylonite_backlight_device);
if (lcd_id & 0x20) {
set_pxa_fb_info(&zylonite_sharp_lcd_info);

4
arch/arm/mach-pxa/zylonite_pxa300.c
View File

@ -50,6 +50,7 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
GPIO75_LCD_BIAS,
GPIO76_LCD_VSYNC,
GPIO127_LCD_CS_N,
GPIO20_PWM3_OUT, /* backlight */
/* BTUART */
GPIO111_UART2_RTS,
@ -200,9 +201,6 @@ void __init zylonite_pxa300_init(void)
/* detect LCD panel */
zylonite_detect_lcd_panel();
/* GPIO pin assignment */
gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
/* MMC card detect & write protect for controller 0 */
zylonite_mmc_slot[0].gpio_cd = EXT_GPIO(0);
zylonite_mmc_slot[0].gpio_wp = EXT_GPIO(2);

2
arch/arm/mach-pxa/zylonite_pxa320.c
View File

@ -49,6 +49,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
GPIO15_2_LCD_LCLK,
GPIO16_2_LCD_PCLK,
GPIO17_2_LCD_BIAS,
GPIO14_PWM3_OUT, /* backlight */
/* FFUART */
GPIO41_UART1_RXD | MFP_LPM_EDGE_FALL,
@ -187,7 +188,6 @@ void __init zylonite_pxa320_init(void)
zylonite_detect_lcd_panel();
/* GPIO pin assignment */
gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
/* MMC card detect & write protect for controller 0 */

29
drivers/i2c/busses/i2c-pxa.c
View File

@ -944,32 +944,6 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
.functionality = i2c_pxa_functionality,
};
static void i2c_pxa_enable(struct platform_device *dev)
{
if (cpu_is_pxa27x()) {
switch (dev->id) {
case 0:
pxa_gpio_mode(GPIO117_I2CSCL_MD);
pxa_gpio_mode(GPIO118_I2CSDA_MD);
break;
case 1:
local_irq_disable();
PCFR |= PCFR_PI2CEN;
local_irq_enable();
break;
}
}
}
static void i2c_pxa_disable(struct platform_device *dev)
{
if (cpu_is_pxa27x() && dev->id == 1) {
local_irq_disable();
PCFR &= ~PCFR_PI2CEN;
local_irq_enable();
}
}
#define res_len(r) ((r)->end - (r)->start + 1)
static int i2c_pxa_probe(struct platform_device *dev)
{
@ -1035,7 +1009,6 @@ static int i2c_pxa_probe(struct platform_device *dev)
#endif
clk_enable(i2c->clk);
i2c_pxa_enable(dev);
if (plat) {
i2c->adap.class = plat->class;
@ -1079,7 +1052,6 @@ eadapt:
free_irq(irq, i2c);
ereqirq:
clk_disable(i2c->clk);
i2c_pxa_disable(dev);
iounmap(i2c->reg_base);
eremap:
clk_put(i2c->clk);
@ -1102,7 +1074,6 @@ static int __exit i2c_pxa_remove(struct platform_device *dev)
clk_disable(i2c->clk);
clk_put(i2c->clk);
i2c_pxa_disable(dev);
iounmap(i2c->reg_base);
release_mem_region(i2c->iobase, i2c->iosize);

15
drivers/pcmcia/pxa2xx_cm_x270.c
View File

@ -18,6 +18,7 @@
#include <pcmcia/ss.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-gpio.h>
@ -130,7 +131,7 @@ static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
}
static struct pcmcia_low_level cmx270_pcmcia_ops = {
static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = {
.owner = THIS_MODULE,
.hw_init = cmx270_pcmcia_hw_init,
.hw_shutdown = cmx270_pcmcia_shutdown,
@ -147,15 +148,21 @@ static int __init cmx270_pcmcia_init(void)
{
int ret;
if (!machine_is_armcore())
return -ENODEV;
cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
if (!cmx270_pcmcia_device)
return -ENOMEM;
cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops;
ret = platform_device_add_data(cmx270_pcmcia_device, &cmx270_pcmcia_ops,
sizeof(cmx270_pcmcia_ops));
printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
ret = platform_device_add(cmx270_pcmcia_device);
if (ret == 0) {
printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
ret = platform_device_add(cmx270_pcmcia_device);
}
if (ret)
platform_device_put(cmx270_pcmcia_device);

13
drivers/pcmcia/pxa2xx_mainstone.c
View File

@ -22,6 +22,7 @@
#include <pcmcia/ss.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/arch/pxa-regs.h>
@ -136,7 +137,7 @@ static void mst_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
{
}
static struct pcmcia_low_level mst_pcmcia_ops = {
static struct pcmcia_low_level mst_pcmcia_ops __initdata = {
.owner = THIS_MODULE,
.hw_init = mst_pcmcia_hw_init,
.hw_shutdown = mst_pcmcia_hw_shutdown,
@ -153,13 +154,17 @@ static int __init mst_pcmcia_init(void)
{
int ret;
if (!machine_is_mainstone())
return -ENODEV;
mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
if (!mst_pcmcia_device)
return -ENOMEM;
mst_pcmcia_device->dev.platform_data = &mst_pcmcia_ops;
ret = platform_device_add(mst_pcmcia_device);
ret = platform_device_add_data(mst_pcmcia_device, &mst_pcmcia_ops,
sizeof(mst_pcmcia_ops));
if (ret == 0)
ret = platform_device_add(mst_pcmcia_device);
if (ret)
platform_device_put(mst_pcmcia_device);

12
drivers/pcmcia/pxa2xx_sharpsl.c
View File

@ -222,7 +222,7 @@ static void sharpsl_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
sharpsl_pcmcia_init_reset(skt);
}
static struct pcmcia_low_level sharpsl_pcmcia_ops = {
static struct pcmcia_low_level sharpsl_pcmcia_ops __initdata = {
.owner = THIS_MODULE,
.hw_init = sharpsl_pcmcia_hw_init,
.hw_shutdown = sharpsl_pcmcia_hw_shutdown,
@ -261,10 +261,12 @@ static int __init sharpsl_pcmcia_init(void)
if (!sharpsl_pcmcia_device)
return -ENOMEM;
sharpsl_pcmcia_device->dev.platform_data = &sharpsl_pcmcia_ops;
sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev;
ret = platform_device_add(sharpsl_pcmcia_device);
ret = platform_device_add_data(sharpsl_pcmcia_device,
&sharpsl_pcmcia_ops, sizeof(sharpsl_pcmcia_ops));
if (ret == 0) {
sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev;
ret = platform_device_add(sharpsl_pcmcia_device);
}
if (ret)
platform_device_put(sharpsl_pcmcia_device);

5
drivers/usb/gadget/pxa27x_udc.c
View File

@ -38,7 +38,7 @@
#include <linux/usb.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
#include <asm/arch/udc.h>
#include "pxa27x_udc.h"
@ -2359,7 +2359,8 @@ static int pxa_udc_resume(struct platform_device *_dev)
* Software must configure the USB OTG pad, UDC, and UHC
* to the state they were in before entering sleep mode.
*/
PSSR |= PSSR_OTGPH;
if (cpu_is_pxa27x())
PSSR |= PSSR_OTGPH;
return 0;
}

8
drivers/usb/gadget/pxa27x_udc.h
View File

@ -484,12 +484,4 @@ static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
#define ep_warn(ep, fmt, arg...) \
dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
/*
* Cannot include pxa-regs.h, as register names are similar.
* So PSSR is redefined here. This should be removed once UDC registers will
* be gone from pxa-regs.h.
*/
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status */
#define PSSR_OTGPH (1 << 6) /* OTG Peripheral Hold */
#endif /* __LINUX_USB_GADGET_PXA27X_H */

10
drivers/usb/gadget/pxa2xx_udc.c
View File

@ -46,19 +46,25 @@
#include <linux/err.h>
#include <linux/seq_file.h>
#include <linux/debugfs.h>
#include <linux/io.h>
#include <asm/byteorder.h>
#include <asm/dma.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/mach-types.h>
#include <asm/unaligned.h>
#include <asm/hardware.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
/*
* This driver is PXA25x only. Grab the right register definitions.
*/
#ifdef CONFIG_ARCH_PXA
#include <asm/arch/pxa25x-udc.h>
#endif
#include <asm/mach/udc_pxa2xx.h>

3
drivers/usb/host/ohci-pxa27x.c
View File

@ -27,6 +27,7 @@
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */
#include <asm/arch/ohci.h>
#define PXA_UHC_MAX_PORTNUM 3
@ -104,7 +105,7 @@ static int pxa27x_start_hc(struct device *dev)
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
/* Clear any OTG Pin Hold */
if (PSSR & PSSR_OTGPH)
if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
PSSR |= PSSR_OTGPH;
return 0;

7
drivers/video/backlight/Kconfig
View File

@ -112,3 +112,10 @@ config BACKLIGHT_CARILLO_RANCH
help
If you have a Intel LE80578 (Carillo Ranch) say Y to enable the
backlight driver.
config BACKLIGHT_PWM
tristate "Generic PWM based Backlight Driver"
depends on BACKLIGHT_CLASS_DEVICE && HAVE_PWM
help
If you have a LCD backlight adjustable by PWM, say Y to enable
this driver.

1
drivers/video/backlight/Makefile
View File

@ -10,3 +10,4 @@ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o
obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o
obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o

185
drivers/video/backlight/pwm_bl.c 100644
View File

@ -0,0 +1,185 @@
/*
* linux/drivers/video/backlight/pwm_bl.c
*
* simple PWM based backlight control, board code has to setup
* 1) pin configuration so PWM waveforms can output
* 2) platform_data casts to the PWM id (0/1/2/3 on PXA)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
struct pwm_bl_data {
struct pwm_device *pwm;
unsigned int period;
int (*notify)(int brightness);
};
static int pwm_backlight_update_status(struct backlight_device *bl)
{
struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
int brightness = bl->props.brightness;
int max = bl->props.max_brightness;
if (bl->props.power != FB_BLANK_UNBLANK)
brightness = 0;
if (bl->props.fb_blank != FB_BLANK_UNBLANK)
brightness = 0;
if (pb->notify)
brightness = pb->notify(brightness);
if (brightness == 0) {
pwm_config(pb->pwm, 0, pb->period);
pwm_disable(pb->pwm);
} else {
pwm_config(pb->pwm, brightness * pb->period / max, pb->period);
pwm_enable(pb->pwm);
}
return 0;
}
static int pwm_backlight_get_brightness(struct backlight_device *bl)
{
return bl->props.brightness;
}
static struct backlight_ops pwm_backlight_ops = {
.update_status = pwm_backlight_update_status,
.get_brightness = pwm_backlight_get_brightness,
};
static int pwm_backlight_probe(struct platform_device *pdev)
{
struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
struct backlight_device *bl;
struct pwm_bl_data *pb;
int ret;
if (!data)
return -EINVAL;
if (data->init) {
ret = data->init(&pdev->dev);
if (ret < 0)
return ret;
}
pb = kzalloc(sizeof(*pb), GFP_KERNEL);
if (!pb) {
ret = -ENOMEM;
goto err_alloc;
}
pb->period = data->pwm_period_ns;
pb->notify = data->notify;
pb->pwm = pwm_request(data->pwm_id, "backlight");
if (IS_ERR(pb->pwm)) {
dev_err(&pdev->dev, "unable to request PWM for backlight\n");
ret = PTR_ERR(pb->pwm);
goto err_pwm;
}
bl = backlight_device_register(pdev->name, &pdev->dev,
pb, &pwm_backlight_ops);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
ret = PTR_ERR(bl);
goto err_bl;
}
bl->props.max_brightness = data->max_brightness;
bl->props.brightness = data->dft_brightness;
backlight_update_status(bl);
platform_set_drvdata(pdev, bl);
return 0;
err_bl:
pwm_free(pb->pwm);
err_pwm:
kfree(pb);
err_alloc:
if (data->exit)
data->exit(&pdev->dev);
return ret;
}
static int pwm_backlight_remove(struct platform_device *pdev)
{
struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
struct backlight_device *bl = platform_get_drvdata(pdev);
struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
backlight_device_unregister(bl);
pwm_config(pb->pwm, 0, pb->period);
pwm_disable(pb->pwm);
pwm_free(pb->pwm);
kfree(pb);
if (data->exit)
data->exit(&pdev->dev);
return 0;
}
#ifdef CONFIG_PM
static int pwm_backlight_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct backlight_device *bl = platform_get_drvdata(pdev);
struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
pwm_config(pb->pwm, 0, pb->period);
pwm_disable(pb->pwm);
return 0;
}
static int pwm_backlight_resume(struct platform_device *pdev)
{
struct backlight_device *bl = platform_get_drvdata(pdev);
backlight_update_status(bl);
return 0;
}
#else
#define pwm_backlight_suspend NULL
#define pwm_backlight_resume NULL
#endif
static struct platform_driver pwm_backlight_driver = {
.driver = {
.name = "pwm-backlight",
.owner = THIS_MODULE,
},
.probe = pwm_backlight_probe,
.remove = pwm_backlight_remove,
.suspend = pwm_backlight_suspend,
.resume = pwm_backlight_resume,
};
static int __init pwm_backlight_init(void)
{
return platform_driver_register(&pwm_backlight_driver);
}
module_init(pwm_backlight_init);
static void __exit pwm_backlight_exit(void)
{
platform_driver_unregister(&pwm_backlight_driver);
}
module_exit(pwm_backlight_exit);
MODULE_DESCRIPTION("PWM based Backlight Driver");
MODULE_LICENSE("GPL");

570
include/asm-arm/arch-pxa/pxa-regs.h
View File

@ -599,418 +599,6 @@
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
/*
* USB Device Controller
* PXA25x and PXA27x USB device controller registers are different.
*/
#if defined(CONFIG_PXA25x)
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
#elif defined(CONFIG_PXA27x)
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
Protocol Port Support */
#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
Support */
#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
Enable */
#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
#define UDCCR_ACN_S 11
#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
#define UDCCR_AIN_S 8
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
Setting Number */
#define UDCCR_AAISN_S 5
#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
Configuration */
#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
Error */
#define UDCCR_UDR (1 << 2) /* UDC Resume */
#define UDCCR_UDA (1 << 1) /* UDC Active */
#define UDCCR_UDE (1 << 0) /* UDC Enable */
#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
Interrupt Enable */
#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
Edge Interrupt Enable */
#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
Edge Interrupt Enable */
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
Interrupt Enable */
#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_FST (1 << 5) /* Force Stall */
#define UDCCSR0_SST (1 << 4) /* Sent Stall */
#define UDCCSR0_DME (1 << 3) /* DMA Enable */
#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
#define UDCCSR_FST (1 << 5) /* Force STALL */
#define UDCCSR_SST (1 << 4) /* Sent STALL */
#define UDCCSR_DME (1 << 3) /* DMA Enable */
#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
#define UDCDN(x) __REG2(0x40600300, (x)<<2)
#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
#define UDCCN(x) __REG2(0x40600400, (x)<<2)
#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
#define UDCCONR_CN_S (25)
#define UDCCONR_IN (0x07 << 22) /* Interface Number */
#define UDCCONR_IN_S (22)
#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
#define UDCCONR_AISN_S (19)
#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
#define UDCCONR_EN_S (15)
#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
#define UDCCONR_ET_S (13)
#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
#define UDCCONR_MPS_S (2)
#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDC_FNR_MASK (0x7ff)
#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK (0x3ff)
#endif
/*
* Fast Infrared Communication Port
*/
@ -1237,120 +825,9 @@
#endif
/*
* Power Manager
* Power Manager - see pxa2xx-regs.h
*/
#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
#define PCMD(x) __REG2(0x40F00080, (x)<<2)
#define PCMD0 __REG(0x40F00080 + 0 * 4)
#define PCMD1 __REG(0x40F00080 + 1 * 4)
#define PCMD2 __REG(0x40F00080 + 2 * 4)
#define PCMD3 __REG(0x40F00080 + 3 * 4)
#define PCMD4 __REG(0x40F00080 + 4 * 4)
#define PCMD5 __REG(0x40F00080 + 5 * 4)
#define PCMD6 __REG(0x40F00080 + 6 * 4)
#define PCMD7 __REG(0x40F00080 + 7 * 4)
#define PCMD8 __REG(0x40F00080 + 8 * 4)
#define PCMD9 __REG(0x40F00080 + 9 * 4)
#define PCMD10 __REG(0x40F00080 + 10 * 4)
#define PCMD11 __REG(0x40F00080 + 11 * 4)
#define PCMD12 __REG(0x40F00080 + 12 * 4)
#define PCMD13 __REG(0x40F00080 + 13 * 4)
#define PCMD14 __REG(0x40F00080 + 14 * 4)
#define PCMD15 __REG(0x40F00080 + 15 * 4)
#define PCMD16 __REG(0x40F00080 + 16 * 4)
#define PCMD17 __REG(0x40F00080 + 17 * 4)
#define PCMD18 __REG(0x40F00080 + 18 * 4)
#define PCMD19 __REG(0x40F00080 + 19 * 4)
#define PCMD20 __REG(0x40F00080 + 20 * 4)
#define PCMD21 __REG(0x40F00080 + 21 * 4)
#define PCMD22 __REG(0x40F00080 + 22 * 4)
#define PCMD23 __REG(0x40F00080 + 23 * 4)
#define PCMD24 __REG(0x40F00080 + 24 * 4)
#define PCMD25 __REG(0x40F00080 + 25 * 4)
#define PCMD26 __REG(0x40F00080 + 26 * 4)
#define PCMD27 __REG(0x40F00080 + 27 * 4)
#define PCMD28 __REG(0x40F00080 + 28 * 4)
#define PCMD29 __REG(0x40F00080 + 29 * 4)
#define PCMD30 __REG(0x40F00080 + 30 * 4)
#define PCMD31 __REG(0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
#define PCMD_LC (1<<10)
/* FIXME: PCMD_SQC need be checked. */
#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
bit 9 should be 0 all day. */
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
#define PCFR_PI2C_EN (0x1 << 6)
#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_STS (1 << 3) /* Standby Mode Status */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
#define PCFR_RO (1 << 15) /* RDH Override */
#define PCFR_PO (1 << 14) /* PH Override */
#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
/*
* SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
*/
@ -1360,52 +837,9 @@
*/
/*
* Core Clock
* Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
*/
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
#define CKEN_IM (20) /* Internal Memory Clock Enable */
#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
#define CKEN_USIM (18) /* USIM Unit Clock Enable */
#define CKEN_MSL (17) /* MSL Unit Clock Enable */
#define CKEN_LCD (16) /* LCD Unit Clock Enable */
#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
#define CKEN_I2C (14) /* I2C Unit Clock Enable */
#define CKEN_FICP (13) /* FICP Unit Clock Enable */
#define CKEN_MMC (12) /* MMC Unit Clock Enable */
#define CKEN_USB (11) /* USB Unit Clock Enable */
#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
#define CKEN_I2S (8) /* I2S Unit Clock Enable */
#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
#define CKEN_STUART (5) /* STUART Unit Clock Enable */
#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
#define CKEN_SSP (3) /* SSP Unit Clock Enable */
#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
#ifdef CONFIG_PXA27x
/* Camera Interface */

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#ifndef _ASM_ARCH_PXA25X_UDC_H
#define _ASM_ARCH_PXA25X_UDC_H
#ifdef _ASM_ARCH_PXA27X_UDC_H
#error You can't include both PXA25x and PXA27x UDC support
#endif
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
#define UDCCS0_SST (1 << 4) /* Sent stall */
#define UDCCS0_FST (1 << 5) /* Force stall */
#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_BI_SST (1 << 4) /* Sent stall */
#define UDCCS_BI_FST (1 << 5) /* Force stall */
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_BO_DME (1 << 3) /* DMA enable */
#define UDCCS_BO_SST (1 << 4) /* Sent stall */
#define UDCCS_BO_FST (1 << 5) /* Force stall */
#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
#define UDCCS_IO_DME (1 << 3) /* DMA enable */
#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
#define UDCCS_INT_SST (1 << 4) /* Sent stall */
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
#endif

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#ifndef _ASM_ARCH_PXA27X_UDC_H
#define _ASM_ARCH_PXA27X_UDC_H
#ifdef _ASM_ARCH_PXA25X_UDC_H
#error You cannot include both PXA25x and PXA27x UDC support
#endif
#define UDCCR __REG(0x40600000) /* UDC Control Register */
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
Protocol Port Support */
#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
Support */
#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
Enable */
#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
#define UDCCR_ACN_S 11
#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
#define UDCCR_AIN_S 8
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
Setting Number */
#define UDCCR_AAISN_S 5
#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
Configuration */
#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
Error */
#define UDCCR_UDR (1 << 2) /* UDC Resume */
#define UDCCR_UDA (1 << 1) /* UDC Active */
#define UDCCR_UDE (1 << 0) /* UDC Enable */
#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
Interrupt Enable */
#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
Interrupt Enable */
#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
Edge Interrupt Enable */
#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
Edge Interrupt Enable */
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
Interrupt Enable */
#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_FST (1 << 5) /* Force Stall */
#define UDCCSR0_SST (1 << 4) /* Sent Stall */
#define UDCCSR0_DME (1 << 3) /* DMA Enable */
#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
#define UDCCSR_FST (1 << 5) /* Force STALL */
#define UDCCSR_SST (1 << 4) /* Sent STALL */
#define UDCCSR_DME (1 << 3) /* DMA Enable */
#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
#define UDCDN(x) __REG2(0x40600300, (x)<<2)
#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
#define UDCCN(x) __REG2(0x40600400, (x)<<2)
#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
#define UDCCONR_CN_S (25)
#define UDCCONR_IN (0x07 << 22) /* Interface Number */
#define UDCCONR_IN_S (22)
#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
#define UDCCONR_AISN_S (19)
#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
#define UDCCONR_EN_S (15)
#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
#define UDCCONR_ET_S (13)
#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
#define UDCCONR_MPS_S (2)
#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDC_FNR_MASK (0x7ff)
#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK (0x3ff)
#endif

162
include/asm-arm/arch-pxa/pxa2xx-regs.h
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@ -81,4 +81,166 @@
#endif
/*
* Power Manager
*/
#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
#define PCMD(x) __REG2(0x40F00080, (x)<<2)
#define PCMD0 __REG(0x40F00080 + 0 * 4)
#define PCMD1 __REG(0x40F00080 + 1 * 4)
#define PCMD2 __REG(0x40F00080 + 2 * 4)
#define PCMD3 __REG(0x40F00080 + 3 * 4)
#define PCMD4 __REG(0x40F00080 + 4 * 4)
#define PCMD5 __REG(0x40F00080 + 5 * 4)
#define PCMD6 __REG(0x40F00080 + 6 * 4)
#define PCMD7 __REG(0x40F00080 + 7 * 4)
#define PCMD8 __REG(0x40F00080 + 8 * 4)
#define PCMD9 __REG(0x40F00080 + 9 * 4)
#define PCMD10 __REG(0x40F00080 + 10 * 4)
#define PCMD11 __REG(0x40F00080 + 11 * 4)
#define PCMD12 __REG(0x40F00080 + 12 * 4)
#define PCMD13 __REG(0x40F00080 + 13 * 4)
#define PCMD14 __REG(0x40F00080 + 14 * 4)
#define PCMD15 __REG(0x40F00080 + 15 * 4)
#define PCMD16 __REG(0x40F00080 + 16 * 4)
#define PCMD17 __REG(0x40F00080 + 17 * 4)
#define PCMD18 __REG(0x40F00080 + 18 * 4)
#define PCMD19 __REG(0x40F00080 + 19 * 4)
#define PCMD20 __REG(0x40F00080 + 20 * 4)
#define PCMD21 __REG(0x40F00080 + 21 * 4)
#define PCMD22 __REG(0x40F00080 + 22 * 4)
#define PCMD23 __REG(0x40F00080 + 23 * 4)
#define PCMD24 __REG(0x40F00080 + 24 * 4)
#define PCMD25 __REG(0x40F00080 + 25 * 4)
#define PCMD26 __REG(0x40F00080 + 26 * 4)
#define PCMD27 __REG(0x40F00080 + 27 * 4)
#define PCMD28 __REG(0x40F00080 + 28 * 4)
#define PCMD29 __REG(0x40F00080 + 29 * 4)
#define PCMD30 __REG(0x40F00080 + 30 * 4)
#define PCMD31 __REG(0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
#define PCMD_LC (1<<10)
/* FIXME: PCMD_SQC need be checked. */
#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
bit 9 should be 0 all day. */
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
#define PCFR_PI2C_EN (0x1 << 6)
#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
#define PSSR_RDH (1 << 5) /* Read Disable Hold */
#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
#define PSSR_STS (1 << 3) /* Standby Mode Status */
#define PSSR_VFS (1 << 2) /* VDD Fault Status */
#define PSSR_BFS (1 << 1) /* Battery Fault Status */
#define PSSR_SSS (1 << 0) /* Software Sleep Status */
#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
#define PCFR_RO (1 << 15) /* RDH Override */
#define PCFR_PO (1 << 14) /* PH Override */
#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */
#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
/*
* PXA2xx specific Core clock definitions
*/
#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
#define CKEN __REG(0x41300004) /* Clock Enable Register */
#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
#define CKEN_IM (20) /* Internal Memory Clock Enable */
#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
#define CKEN_USIM (18) /* USIM Unit Clock Enable */
#define CKEN_MSL (17) /* MSL Unit Clock Enable */
#define CKEN_LCD (16) /* LCD Unit Clock Enable */
#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
#define CKEN_I2C (14) /* I2C Unit Clock Enable */
#define CKEN_FICP (13) /* FICP Unit Clock Enable */
#define CKEN_MMC (12) /* MMC Unit Clock Enable */
#define CKEN_USB (11) /* USB Unit Clock Enable */
#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
#define CKEN_I2S (8) /* I2S Unit Clock Enable */
#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
#define CKEN_STUART (5) /* STUART Unit Clock Enable */
#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
#define CKEN_SSP (3) /* SSP Unit Clock Enable */
#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
#endif

1
include/asm-arm/arch-pxa/system.h
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@ -12,6 +12,7 @@
#include <asm/proc-fns.h>
#include "hardware.h"
#include "pxa2xx-regs.h"
#include "pxa-regs.h"
static inline void arch_idle(void)

1
include/asm-arm/arch-pxa/zylonite.h
View File

@ -15,7 +15,6 @@ struct platform_mmc_slot {
extern struct platform_mmc_slot zylonite_mmc_slot[];
extern int gpio_backlight;
extern int gpio_eth_irq;
extern int wm9713_irq;

31
include/linux/pwm.h 100644
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@ -0,0 +1,31 @@
#ifndef __LINUX_PWM_H
#define __LINUX_PWM_H
struct pwm_device;
/*
* pwm_request - request a PWM device
*/
struct pwm_device *pwm_request(int pwm_id, const char *label);
/*
* pwm_free - free a PWM device
*/
void pwm_free(struct pwm_device *pwm);
/*
* pwm_config - change a PWM device configuration
*/
int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
/*
* pwm_enable - start a PWM output toggling
*/
int pwm_enable(struct pwm_device *pwm);
/*
* pwm_disable - stop a PWM output toggling
*/
void pwm_disable(struct pwm_device *pwm);
#endif /* __ASM_ARCH_PWM_H */

17
include/linux/pwm_backlight.h 100644
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@ -0,0 +1,17 @@
/*
* Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c
*/
#ifndef __LINUX_PWM_BACKLIGHT_H
#define __LINUX_PWM_BACKLIGHT_H
struct platform_pwm_backlight_data {
int pwm_id;
unsigned int max_brightness;
unsigned int dft_brightness;
unsigned int pwm_period_ns;
int (*init)(struct device *dev);
int (*notify)(int brightness);
void (*exit)(struct device *dev);
};
#endif