platform:x86: add Intel P-Unit mailbox IPC driver
This driver provides support for P-Unit mailbox IPC on Intel platforms. The heart of the P-Unit is the Foxton microcontroller and its firmware, which provide mailbox interface for power management usage. Signed-off-by: Qipeng Zha <qipeng.zha@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart <dvhart@linux.intel.com>hifive-unleashed-5.1
Qipeng Zha
Darren Hart
parent
8cc7fb4a65
commit
fdca4f16f5
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@ -5680,12 +5680,14 @@ F: drivers/dma/mic_x100_dma.c
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F: drivers/dma/mic_x100_dma.h
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F Documentation/mic/
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INTEL PMC IPC DRIVER
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INTEL PMC/P-Unit IPC DRIVER
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M: Zha Qipeng<qipeng.zha@intel.com>
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L: platform-driver-x86@vger.kernel.org
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S: Maintained
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F: drivers/platform/x86/intel_pmc_ipc.c
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F: drivers/platform/x86/intel_punit_ipc.c
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F: arch/x86/include/asm/intel_pmc_ipc.h
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F: arch/x86/include/asm/intel_punit_ipc.h
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IOC3 ETHERNET DRIVER
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M: Ralf Baechle <ralf@linux-mips.org>
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@ -0,0 +1,101 @@
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#ifndef _ASM_X86_INTEL_PUNIT_IPC_H_
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#define _ASM_X86_INTEL_PUNIT_IPC_H_
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/*
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* Three types of 8bit P-Unit IPC commands are supported,
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* bit[7:6]: [00]: BIOS; [01]: GTD; [10]: ISPD.
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*/
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typedef enum {
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BIOS_IPC = 0,
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GTDRIVER_IPC,
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ISPDRIVER_IPC,
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RESERVED_IPC,
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} IPC_TYPE;
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#define IPC_TYPE_OFFSET 6
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#define IPC_PUNIT_BIOS_CMD_BASE (BIOS_IPC << IPC_TYPE_OFFSET)
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#define IPC_PUNIT_GTD_CMD_BASE (GTDDRIVER_IPC << IPC_TYPE_OFFSET)
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#define IPC_PUNIT_ISPD_CMD_BASE (ISPDRIVER_IPC << IPC_TYPE_OFFSET)
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#define IPC_PUNIT_CMD_TYPE_MASK (RESERVED_IPC << IPC_TYPE_OFFSET)
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/* BIOS => Pcode commands */
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#define IPC_PUNIT_BIOS_ZERO (IPC_PUNIT_BIOS_CMD_BASE | 0x00)
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#define IPC_PUNIT_BIOS_VR_INTERFACE (IPC_PUNIT_BIOS_CMD_BASE | 0x01)
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#define IPC_PUNIT_BIOS_READ_PCS (IPC_PUNIT_BIOS_CMD_BASE | 0x02)
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#define IPC_PUNIT_BIOS_WRITE_PCS (IPC_PUNIT_BIOS_CMD_BASE | 0x03)
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#define IPC_PUNIT_BIOS_READ_PCU_CONFIG (IPC_PUNIT_BIOS_CMD_BASE | 0x04)
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#define IPC_PUNIT_BIOS_WRITE_PCU_CONFIG (IPC_PUNIT_BIOS_CMD_BASE | 0x05)
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#define IPC_PUNIT_BIOS_READ_PL1_SETTING (IPC_PUNIT_BIOS_CMD_BASE | 0x06)
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#define IPC_PUNIT_BIOS_WRITE_PL1_SETTING (IPC_PUNIT_BIOS_CMD_BASE | 0x07)
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#define IPC_PUNIT_BIOS_TRIGGER_VDD_RAM (IPC_PUNIT_BIOS_CMD_BASE | 0x08)
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#define IPC_PUNIT_BIOS_READ_TELE_INFO (IPC_PUNIT_BIOS_CMD_BASE | 0x09)
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#define IPC_PUNIT_BIOS_READ_TELE_TRACE_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0a)
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#define IPC_PUNIT_BIOS_WRITE_TELE_TRACE_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0b)
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#define IPC_PUNIT_BIOS_READ_TELE_EVENT_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0c)
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#define IPC_PUNIT_BIOS_WRITE_TELE_EVENT_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0d)
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#define IPC_PUNIT_BIOS_READ_TELE_TRACE (IPC_PUNIT_BIOS_CMD_BASE | 0x0e)
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#define IPC_PUNIT_BIOS_WRITE_TELE_TRACE (IPC_PUNIT_BIOS_CMD_BASE | 0x0f)
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#define IPC_PUNIT_BIOS_READ_TELE_EVENT (IPC_PUNIT_BIOS_CMD_BASE | 0x10)
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#define IPC_PUNIT_BIOS_WRITE_TELE_EVENT (IPC_PUNIT_BIOS_CMD_BASE | 0x11)
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#define IPC_PUNIT_BIOS_READ_MODULE_TEMP (IPC_PUNIT_BIOS_CMD_BASE | 0x12)
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#define IPC_PUNIT_BIOS_RESERVED (IPC_PUNIT_BIOS_CMD_BASE | 0x13)
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#define IPC_PUNIT_BIOS_READ_VOLTAGE_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x14)
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#define IPC_PUNIT_BIOS_WRITE_VOLTAGE_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x15)
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#define IPC_PUNIT_BIOS_READ_RATIO_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x16)
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#define IPC_PUNIT_BIOS_WRITE_RATIO_OVER (IPC_PUNIT_BIOS_CMD_BASE | 0x17)
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#define IPC_PUNIT_BIOS_READ_VF_GL_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x18)
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#define IPC_PUNIT_BIOS_WRITE_VF_GL_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x19)
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#define IPC_PUNIT_BIOS_READ_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1a)
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#define IPC_PUNIT_BIOS_WRITE_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1b)
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/* GT Driver => Pcode commands */
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#define IPC_PUNIT_GTD_ZERO (IPC_PUNIT_GTD_CMD_BASE | 0x00)
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#define IPC_PUNIT_GTD_CONFIG (IPC_PUNIT_GTD_CMD_BASE | 0x01)
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#define IPC_PUNIT_GTD_READ_ICCP_LIC_CDYN_SCAL (IPC_PUNIT_GTD_CMD_BASE | 0x02)
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#define IPC_PUNIT_GTD_WRITE_ICCP_LIC_CDYN_SCAL (IPC_PUNIT_GTD_CMD_BASE | 0x03)
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#define IPC_PUNIT_GTD_GET_WM_VAL (IPC_PUNIT_GTD_CMD_BASE | 0x06)
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#define IPC_PUNIT_GTD_WRITE_CONFIG_WISHREQ (IPC_PUNIT_GTD_CMD_BASE | 0x07)
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#define IPC_PUNIT_GTD_READ_REQ_DUTY_CYCLE (IPC_PUNIT_GTD_CMD_BASE | 0x16)
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#define IPC_PUNIT_GTD_DIS_VOL_FREQ_CHG_REQUEST (IPC_PUNIT_GTD_CMD_BASE | 0x17)
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#define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_CTRL (IPC_PUNIT_GTD_CMD_BASE | 0x1a)
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#define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_TUNING (IPC_PUNIT_GTD_CMD_BASE | 0x1c)
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/* ISP Driver => Pcode commands */
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#define IPC_PUNIT_ISPD_ZERO (IPC_PUNIT_ISPD_CMD_BASE | 0x00)
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#define IPC_PUNIT_ISPD_CONFIG (IPC_PUNIT_ISPD_CMD_BASE | 0x01)
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#define IPC_PUNIT_ISPD_GET_ISP_LTR_VAL (IPC_PUNIT_ISPD_CMD_BASE | 0x02)
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#define IPC_PUNIT_ISPD_ACCESS_IU_FREQ_BOUNDS (IPC_PUNIT_ISPD_CMD_BASE | 0x03)
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#define IPC_PUNIT_ISPD_READ_CDYN_LEVEL (IPC_PUNIT_ISPD_CMD_BASE | 0x04)
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#define IPC_PUNIT_ISPD_WRITE_CDYN_LEVEL (IPC_PUNIT_ISPD_CMD_BASE | 0x05)
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/* Error codes */
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#define IPC_PUNIT_ERR_SUCCESS 0
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#define IPC_PUNIT_ERR_INVALID_CMD 1
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#define IPC_PUNIT_ERR_INVALID_PARAMETER 2
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#define IPC_PUNIT_ERR_CMD_TIMEOUT 3
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#define IPC_PUNIT_ERR_CMD_LOCKED 4
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#define IPC_PUNIT_ERR_INVALID_VR_ID 5
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#define IPC_PUNIT_ERR_VR_ERR 6
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#if IS_ENABLED(CONFIG_INTEL_PUNIT_IPC)
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int intel_punit_ipc_simple_command(int cmd, int para1, int para2);
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int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out);
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#else
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static inline int intel_punit_ipc_simple_command(int cmd,
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int para1, int para2)
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{
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return -ENODEV;
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}
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static inline int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2,
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u32 *in, u32 *out)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_INTEL_PUNIT_IPC */
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#endif
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@ -944,4 +944,10 @@ config SURFACE_PRO3_BUTTON
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depends on ACPI && INPUT
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---help---
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This driver handles the power/home/volume buttons on the Microsoft Surface Pro 3 tablet.
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config INTEL_PUNIT_IPC
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tristate "Intel P-Unit IPC Driver"
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---help---
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This driver provides support for Intel P-Unit Mailbox IPC mechanism,
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which is used to bridge the communications between kernel and P-Unit.
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endif # X86_PLATFORM_DEVICES
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@ -62,3 +62,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o
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obj-$(CONFIG_ALIENWARE_WMI) += alienware-wmi.o
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obj-$(CONFIG_INTEL_PMC_IPC) += intel_pmc_ipc.o
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obj-$(CONFIG_SURFACE_PRO3_BUTTON) += surfacepro3_button.o
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obj-$(CONFIG_INTEL_PUNIT_IPC) += intel_punit_ipc.o
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@ -0,0 +1,338 @@
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/*
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* Driver for the Intel P-Unit Mailbox IPC mechanism
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*
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* (C) Copyright 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The heart of the P-Unit is the Foxton microcontroller and its firmware,
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* which provide mailbox interface for power management usage.
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*/
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#include <linux/module.h>
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <asm/intel_punit_ipc.h>
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/* IPC Mailbox registers */
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#define OFFSET_DATA_LOW 0x0
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#define OFFSET_DATA_HIGH 0x4
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/* bit field of interface register */
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#define CMD_RUN BIT(31)
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#define CMD_ERRCODE_MASK GENMASK(7, 0)
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#define CMD_PARA1_SHIFT 8
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#define CMD_PARA2_SHIFT 16
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#define CMD_TIMEOUT_SECONDS 1
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enum {
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BASE_DATA = 0,
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BASE_IFACE,
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BASE_MAX,
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};
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typedef struct {
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struct device *dev;
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struct mutex lock;
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int irq;
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struct completion cmd_complete;
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/* base of interface and data registers */
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void __iomem *base[RESERVED_IPC][BASE_MAX];
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IPC_TYPE type;
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} IPC_DEV;
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static IPC_DEV *punit_ipcdev;
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static inline u32 ipc_read_status(IPC_DEV *ipcdev, IPC_TYPE type)
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{
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return readl(ipcdev->base[type][BASE_IFACE]);
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}
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static inline void ipc_write_cmd(IPC_DEV *ipcdev, IPC_TYPE type, u32 cmd)
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{
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writel(cmd, ipcdev->base[type][BASE_IFACE]);
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}
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static inline u32 ipc_read_data_low(IPC_DEV *ipcdev, IPC_TYPE type)
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{
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return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
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}
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static inline u32 ipc_read_data_high(IPC_DEV *ipcdev, IPC_TYPE type)
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{
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return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
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}
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static inline void ipc_write_data_low(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
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{
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writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
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}
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static inline void ipc_write_data_high(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
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{
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writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
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}
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static const char *ipc_err_string(int error)
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{
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if (error == IPC_PUNIT_ERR_SUCCESS)
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return "no error";
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else if (error == IPC_PUNIT_ERR_INVALID_CMD)
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return "invalid command";
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else if (error == IPC_PUNIT_ERR_INVALID_PARAMETER)
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return "invalid parameter";
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else if (error == IPC_PUNIT_ERR_CMD_TIMEOUT)
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return "command timeout";
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else if (error == IPC_PUNIT_ERR_CMD_LOCKED)
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return "command locked";
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else if (error == IPC_PUNIT_ERR_INVALID_VR_ID)
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return "invalid vr id";
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else if (error == IPC_PUNIT_ERR_VR_ERR)
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return "vr error";
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else
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return "unknown error";
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}
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static int intel_punit_ipc_check_status(IPC_DEV *ipcdev, IPC_TYPE type)
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{
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int loops = CMD_TIMEOUT_SECONDS * USEC_PER_SEC;
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int errcode;
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int status;
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if (ipcdev->irq) {
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if (!wait_for_completion_timeout(&ipcdev->cmd_complete,
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CMD_TIMEOUT_SECONDS * HZ)) {
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dev_err(ipcdev->dev, "IPC timed out\n");
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return -ETIMEDOUT;
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}
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} else {
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while ((ipc_read_status(ipcdev, type) & CMD_RUN) && --loops)
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udelay(1);
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if (!loops) {
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dev_err(ipcdev->dev, "IPC timed out\n");
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return -ETIMEDOUT;
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}
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}
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status = ipc_read_status(ipcdev, type);
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errcode = status & CMD_ERRCODE_MASK;
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if (errcode) {
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dev_err(ipcdev->dev, "IPC failed: %s, IPC_STS=0x%x\n",
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ipc_err_string(errcode), status);
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return -EIO;
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}
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return 0;
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}
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/**
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* intel_punit_ipc_simple_command() - Simple IPC command
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* @cmd: IPC command code.
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* @para1: First 8bit parameter, set 0 if not used.
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* @para2: Second 8bit parameter, set 0 if not used.
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*
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* Send a IPC command to P-Unit when there is no data transaction
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*
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* Return: IPC error code or 0 on success.
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*/
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int intel_punit_ipc_simple_command(int cmd, int para1, int para2)
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{
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IPC_DEV *ipcdev = punit_ipcdev;
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IPC_TYPE type;
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u32 val;
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int ret;
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mutex_lock(&ipcdev->lock);
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reinit_completion(&ipcdev->cmd_complete);
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type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
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val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
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val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
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ipc_write_cmd(ipcdev, type, val);
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ret = intel_punit_ipc_check_status(ipcdev, type);
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mutex_unlock(&ipcdev->lock);
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return ret;
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}
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EXPORT_SYMBOL(intel_punit_ipc_simple_command);
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/**
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* intel_punit_ipc_command() - IPC command with data and pointers
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* @cmd: IPC command code.
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* @para1: First 8bit parameter, set 0 if not used.
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* @para2: Second 8bit parameter, set 0 if not used.
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* @in: Input data, 32bit for BIOS cmd, two 32bit for GTD and ISPD.
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* @out: Output data.
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*
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* Send a IPC command to P-Unit with data transaction
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*
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* Return: IPC error code or 0 on success.
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*/
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int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out)
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{
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IPC_DEV *ipcdev = punit_ipcdev;
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IPC_TYPE type;
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u32 val;
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int ret;
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mutex_lock(&ipcdev->lock);
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reinit_completion(&ipcdev->cmd_complete);
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type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
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ipc_write_data_low(ipcdev, type, *in);
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if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
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ipc_write_data_high(ipcdev, type, *++in);
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val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
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val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
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ipc_write_cmd(ipcdev, type, val);
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ret = intel_punit_ipc_check_status(ipcdev, type);
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if (ret)
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goto out;
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*out = ipc_read_data_low(ipcdev, type);
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if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
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*++out = ipc_read_data_high(ipcdev, type);
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out:
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mutex_unlock(&ipcdev->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(intel_punit_ipc_command);
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static irqreturn_t intel_punit_ioc(int irq, void *dev_id)
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{
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IPC_DEV *ipcdev = dev_id;
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complete(&ipcdev->cmd_complete);
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return IRQ_HANDLED;
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}
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static int intel_punit_get_bars(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *addr;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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addr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(addr))
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return PTR_ERR(addr);
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punit_ipcdev->base[BIOS_IPC][BASE_DATA] = addr;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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addr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(addr))
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return PTR_ERR(addr);
|
||||
punit_ipcdev->base[BIOS_IPC][BASE_IFACE] = addr;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
addr = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(addr))
|
||||
return PTR_ERR(addr);
|
||||
punit_ipcdev->base[ISPDRIVER_IPC][BASE_DATA] = addr;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
|
||||
addr = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(addr))
|
||||
return PTR_ERR(addr);
|
||||
punit_ipcdev->base[ISPDRIVER_IPC][BASE_IFACE] = addr;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
|
||||
addr = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(addr))
|
||||
return PTR_ERR(addr);
|
||||
punit_ipcdev->base[GTDRIVER_IPC][BASE_DATA] = addr;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 5);
|
||||
addr = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(addr))
|
||||
return PTR_ERR(addr);
|
||||
punit_ipcdev->base[GTDRIVER_IPC][BASE_IFACE] = addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int intel_punit_ipc_probe(struct platform_device *pdev)
|
||||
{
|
||||
int irq, ret;
|
||||
|
||||
punit_ipcdev = devm_kzalloc(&pdev->dev,
|
||||
sizeof(*punit_ipcdev), GFP_KERNEL);
|
||||
if (!punit_ipcdev)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, punit_ipcdev);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
punit_ipcdev->irq = 0;
|
||||
dev_warn(&pdev->dev, "Invalid IRQ, using polling mode\n");
|
||||
} else {
|
||||
ret = devm_request_irq(&pdev->dev, irq, intel_punit_ioc,
|
||||
IRQF_NO_SUSPEND, "intel_punit_ipc",
|
||||
&punit_ipcdev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to request irq: %d\n", irq);
|
||||
return ret;
|
||||
}
|
||||
punit_ipcdev->irq = irq;
|
||||
}
|
||||
|
||||
ret = intel_punit_get_bars(pdev);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
punit_ipcdev->dev = &pdev->dev;
|
||||
mutex_init(&punit_ipcdev->lock);
|
||||
init_completion(&punit_ipcdev->cmd_complete);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int intel_punit_ipc_remove(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct acpi_device_id punit_ipc_acpi_ids[] = {
|
||||
{ "INT34D4", 0 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver intel_punit_ipc_driver = {
|
||||
.probe = intel_punit_ipc_probe,
|
||||
.remove = intel_punit_ipc_remove,
|
||||
.driver = {
|
||||
.name = "intel_punit_ipc",
|
||||
.acpi_match_table = ACPI_PTR(punit_ipc_acpi_ids),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init intel_punit_ipc_init(void)
|
||||
{
|
||||
return platform_driver_register(&intel_punit_ipc_driver);
|
||||
}
|
||||
|
||||
static void __exit intel_punit_ipc_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&intel_punit_ipc_driver);
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
|
||||
MODULE_DESCRIPTION("Intel P-Unit IPC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
/* Some modules are dependent on this, so init earlier */
|
||||
fs_initcall(intel_punit_ipc_init);
|
||||
module_exit(intel_punit_ipc_exit);
|
||||
Loading…
Reference in New Issue