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ARM: dts: aspeed: Add silicon id node 

This register describes the silicon id and chip unique id. It varies
between CPU revisions, but is always part of the SCU.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20200921091644.133107-4-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
zero-sugar-mainline-defconfig
Joel Stanley 2020-09-21 18:46:44 +09:30
parent e0218dca57
commit fe100b382c
3 changed files with 15 additions and 0 deletions
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5
arch/arm/boot/dts/aspeed-g4.dtsi
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@ -192,6 +192,11 @@
status = "disabled";
};
silicon-id@7c {
compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id";
reg = <0x7c 0x4>;
};
pinctrl: pinctrl@80 {
reg = <0x80 0x18>, <0xa0 0x10>;
compatible = "aspeed,ast2400-pinctrl";

5
arch/arm/boot/dts/aspeed-g5.dtsi
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@ -239,6 +239,11 @@
status = "disabled";
};
silicon-id@7c {
compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
reg = <0x7c 0x4 0x150 0x8>;
};
pinctrl: pinctrl@80 {
compatible = "aspeed,ast2500-pinctrl";
reg = <0x80 0x18>, <0xa0 0x10>;

5
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -311,6 +311,11 @@
compatible = "aspeed,ast2600-pinctrl";
};
silicon-id@14 {
compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id";
reg = <0x14 0x4 0x5b0 0x8>;
};
smp-memram@180 {
compatible = "aspeed,ast2600-smpmem";
reg = <0x180 0x40>;