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Pin control changes for v5.2: 

Nex drivers:
 - New driver for Bitmain BM1880 pin controller
 - New driver for Mediatek MT8516
 - New driver for Cirrus Logich Lochnagar PMIC pins
 
 Updates:
 - Incremental development on Renesas SH-PFC
 - Incremental development on Intel pin controller and some
   particular updates for Cedarfork.
 - Pin configuration support in Allwinner SunXi drivers
 - Suspend/resume support in the NXP/Freescale i.MX8MQ driver
 - Support for more packaging of the ST Micro STM32
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Merge tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "It is pretty calm and chill in pin control for the moment. Just
  incremental development.

  There is an odd patch to the Super-H architecture, it's coming from
  the maintainers so should be fine.

  Summary:

  New drivers:
   - Bitmain BM1880 pin controller
   - Mediatek MT8516
   - Cirrus Logich Lochnagar PMIC pins

  Updates:
   - Incremental development on Renesas SH-PFC
   - Incremental development on Intel pin controller and some particular
     updates for Cedarfork.
   - Pin configuration support in Allwinner SunXi drivers
   - Suspend/resume support in the NXP/Freescale i.MX8MQ driver
   - Support for more packaging of the ST Micro STM32"

* tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: mcp23s08: Do not complain about unsupported params
  pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver
  MAINTAINERS: Add entry for BM1880 pinctrl
  pinctrl: Add pinctrl support for BM1880 SoC
  dt-bindings: pinctrl: Add BM1880 pinctrl binding
  pinctrl: stm32: check irq controller availability at probe
  pinctrl: mediatek: Add MT8516 Pinctrl driver
  pinctrl: zte: fix leaked of_node references
  pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()
  pinctrl: intel: Retain HOSTSW_OWN for requested gpio pin
  pinctrl: pistachio: fix leaked of_node references
  pinctrl: sunxi: Support I/O bias voltage setting on H6
  pinctrl: sunxi: Prepare for alternative bias voltage setting methods
  pinctrl: st: fix leaked of_node references
  pinctrl: samsung: fix leaked of_node references
  pinctrl: stm32: align stm32mp157 pin names
  pinctrl: stm32: add package information for stm32mp157c
  pinctrl: stm32: introduce package support
  dt-bindings: pinctrl: stm32: add new entry for package information
  pinctrl: imx8mq: Add suspend/resume ops
  ...
hifive-unleashed-5.2
Linus Torvalds 2019-05-08 10:23:54 -07:00
parent d1cd7c85f9 e0e31695b5
commit fe460a6df6
88 changed files with 8118 additions and 3010 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

98
Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt 100644
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@ -0,0 +1,98 @@
Bitmain BM1880 Pin Controller
This binding describes the pin controller found in the BM1880 SoC.
Required Properties:
- compatible: Should be "bitmain,bm1880-pinctrl"
- reg: Offset and length of pinctrl space in SCTRL.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
includes only pinmux as there is no pinconf support available in SoC.
Each configuration node can consist of multiple nodes describing the pinmux
options. The name of each subnode is not important; all subnodes should be
enumerated and processed purely based on their content.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
Required Properties:
- pins: An array of strings, each string containing the name of a pin.
Valid values for pins are:
MIO0 - MIO111
- groups: An array of strings, each string containing the name of a pin
group. Valid values for groups are:
nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp,
pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp,
pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp,
pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp,
pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp,
pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp,
pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp,
pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp,
i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp,
uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp,
uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp,
uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp,
gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp,
gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp,
gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp,
gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp,
gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp,
gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp,
gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp,
gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp,
gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp,
gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp,
gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp,
gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp,
gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp,
gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp,
i2s1_grp, i2s1_mclkin_grp, spi0_grp
- function: An array of strings, each string containing the name of the
pinmux functions. The following are the list of pinmux
functions available:
nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4,
pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13,
pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22,
pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31,
pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3,
i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7,
uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15,
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8,
gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16,
gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23,
gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37,
gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44,
gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51,
gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58,
gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65,
gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
spi0
Example:
pinctrl: pinctrl@50 {
compatible = "bitmain,bm1880-pinctrl";
reg = <0x50 0x4B0>;
pinctrl_uart0_default: uart0-default {
pinmux {
groups = "uart0_grp";
function = "uart0";
};
};
};

141
Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt 100644
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@ -0,0 +1,141 @@
Cirrus Logic Lochnagar Audio Development Board
Lochnagar is an evaluation and development board for Cirrus Logic
Smart CODEC and Amp devices. It allows the connection of most Cirrus
Logic devices on mini-cards, as well as allowing connection of
various application processor systems to provide a full evaluation
platform. Audio system topology, clocking and power can all be
controlled through the Lochnagar, allowing the device under test
to be used in a variety of possible use cases.
This binding document describes the binding for the pinctrl portion
of the driver.
Also see these documents for generic binding information:
[1] GPIO : ../gpio/gpio.txt
[2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
And these for relevant defines:
[3] include/dt-bindings/pinctrl/lochnagar.h
This binding must be part of the Lochnagar MFD binding:
[4] ../mfd/cirrus,lochnagar.txt
Required properties:
- compatible : One of the following strings:
"cirrus,lochnagar-pinctrl"
- gpio-controller : Indicates this device is a GPIO controller.
- #gpio-cells : Must be 2. The first cell is the pin number, see
[3] for available pins and the second cell is used to specify
optional parameters, see [1].
- gpio-ranges : Range of pins managed by the GPIO controller, see
[1]. Both the GPIO and Pinctrl base should be set to zero and the
count to the appropriate of the LOCHNAGARx_PIN_NUM_GPIOS define,
see [3].
- pinctrl-names : A pinctrl state named "default" must be defined.
- pinctrl-0 : A phandle to the default pinctrl state.
Required sub-nodes:
The pin configurations are defined as a child of the pinctrl states
node, see [2]. Each sub-node can have the following properties:
- groups : A list of groups to select (either this or "pins" must be
specified), available groups:
codec-aif1, codec-aif2, codec-aif3, dsp-aif1, dsp-aif2, psia1,
psia2, gf-aif1, gf-aif2, gf-aif3, gf-aif4, spdif-aif, usb-aif1,
usb-aif2, adat-aif, soundcard-aif
- pins : A list of pin names to select (either this or "groups" must
be specified), available pins:
fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5,
fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4,
codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1,
dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2,
gf-gpio3, gf-gpio7, codec-aif1-bclk, codec-aif1-rxdat,
codec-aif1-lrclk, codec-aif1-txdat, codec-aif2-bclk,
codec-aif2-rxdat, codec-aif2-lrclk, codec-aif2-txdat,
codec-aif3-bclk, codec-aif3-rxdat, codec-aif3-lrclk,
codec-aif3-txdat, dsp-aif1-bclk, dsp-aif1-rxdat, dsp-aif1-lrclk,
dsp-aif1-txdat, dsp-aif2-bclk, dsp-aif2-rxdat,
dsp-aif2-lrclk, dsp-aif2-txdat, psia1-bclk, psia1-rxdat,
psia1-lrclk, psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat, gf-aif3-lrclk,
gf-aif3-txdat, gf-aif4-bclk, gf-aif4-rxdat, gf-aif4-lrclk,
gf-aif4-txdat, gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
gf-aif1-txdat, gf-aif2-bclk, gf-aif2-rxdat, gf-aif2-lrclk,
gf-aif2-txdat, dsp-uart1-rx, dsp-uart1-tx, dsp-uart2-rx,
dsp-uart2-tx, gf-uart2-rx, gf-uart2-tx, usb-uart-rx,
codec-pdmclk1, codec-pdmdat1, codec-pdmclk2, codec-pdmdat2,
codec-dmicclk1, codec-dmicdat1, codec-dmicclk2, codec-dmicdat2,
codec-dmicclk3, codec-dmicdat3, codec-dmicclk4, codec-dmicdat4,
dsp-dmicclk1, dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl,
i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, dsp-standby,
codec-mclk1, codec-mclk2, dsp-clkin, psia1-mclk, psia2-mclk,
gf-gpio1, gf-gpio5, dsp-gpio20, led1, led2
- function : The mux function to select, available functions:
aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5,
fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4,
codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1,
dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2,
gf-gpio3, gf-gpio7, gf-gpio1, gf-gpio5, dsp-gpio20, codec-clkout,
dsp-clkout, pmic-32k, spdif-clkout, clk-12m288, clk-11m2986,
clk-24m576, clk-22m5792, xmos-mclk, gf-clkout1, gf-mclk1,
gf-mclk3, gf-mclk2, gf-clkout2, codec-mclk1, codec-mclk2,
dsp-clkin, psia1-mclk, psia2-mclk, spdif-mclk, codec-irq,
codec-reset, dsp-reset, dsp-irq, dsp-standby, codec-pdmclk1,
codec-pdmdat1, codec-pdmclk2, codec-pdmdat2, codec-dmicclk1,
codec-dmicdat1, codec-dmicclk2, codec-dmicdat2, codec-dmicclk3,
codec-dmicdat3, codec-dmicclk4, codec-dmicdat4, dsp-dmicclk1,
dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, dsp-uart1-rx,
dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, gf-uart2-rx,
gf-uart2-tx, usb-uart-rx, usb-uart-tx, i2c2-scl, i2c2-sda,
i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, spdif-aif, psia1,
psia1-bclk, psia1-lrclk, psia1-rxdat, psia1-txdat, psia2,
psia2-bclk, psia2-lrclk, psia2-rxdat, psia2-txdat, codec-aif1,
codec-aif1-bclk, codec-aif1-lrclk, codec-aif1-rxdat,
codec-aif1-txdat, codec-aif2, codec-aif2-bclk, codec-aif2-lrclk,
codec-aif2-rxdat, codec-aif2-txdat, codec-aif3, codec-aif3-bclk,
codec-aif3-lrclk, codec-aif3-rxdat, codec-aif3-txdat, dsp-aif1,
dsp-aif1-bclk, dsp-aif1-lrclk, dsp-aif1-rxdat, dsp-aif1-txdat,
dsp-aif2, dsp-aif2-bclk, dsp-aif2-lrclk, dsp-aif2-rxdat,
dsp-aif2-txdat, gf-aif3, gf-aif3-bclk, gf-aif3-lrclk,
gf-aif3-rxdat, gf-aif3-txdat, gf-aif4, gf-aif4-bclk,
gf-aif4-lrclk, gf-aif4-rxdat, gf-aif4-txdat, gf-aif1,
gf-aif1-bclk, gf-aif1-lrclk, gf-aif1-rxdat, gf-aif1-txdat,
gf-aif2, gf-aif2-bclk, gf-aif2-lrclk, gf-aif2-rxdat,
gf-aif2-txdat, usb-aif1, usb-aif2, adat-aif, soundcard-aif,
- output-enable : Specifies that an AIF group will be used as a master
interface (either this or input-enable is required if a group is
being muxed to an AIF)
- input-enable : Specifies that an AIF group will be used as a slave
interface (either this or output-enable is required if a group is
being muxed to an AIF)
Example:
lochnagar-pinctrl {
compatible = "cirrus,lochnagar-pinctrl";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lochnagar 0 0 LOCHNAGAR2_PIN_NUM_GPIOS>;
pinctrl-names = "default";
pinctrl-0 = <&pin-settings>;
pin-settings: pin-settings {
ap-aif {
input-enable;
groups = "gf-aif1";
function = "codec-aif3";
};
codec-aif {
output-enable;
groups = "codec-aif3";
function = "gf-aif1";
};
};
};

6
Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
View File

@ -48,9 +48,9 @@ PAD_CTL_HYS (1 << 3)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_FAST (0 << 2)
PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
PAD_CTL_DSE_X4 (1 << 0)
PAD_CTL_DSE_X2 (2 << 0)
PAD_CTL_DSE_X6 (3 << 0)
Examples:
While iomuxc-lpsr is intended to be used by dedicated peripherals to take

1
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
View File

@ -11,6 +11,7 @@ Required properties:
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
- gpio-controller : Marks the device node as a gpio controller.

132
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@ -0,0 +1,132 @@
* Mediatek MT8183 Pin Controller
The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
- gpio-ranges : gpio valid number range.
- reg: physical address base for gpio base registers. There are 10 GPIO
physical address base in mt8183.
Optional properties:
- reg-names: gpio base register names. There are 10 gpio base register
names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
"iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint".
- interrupt-controller: Marks the device node as an interrupt controller
- #interrupt-cells: Should be two.
- interrupts : The interrupt outputs to sysirq.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input schmitt.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in boot/dts/<soc>-pinfunc.h directly.
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low,
output-high, input-schmitt-enable, input-schmitt-disable
and drive-strength are valid.
Some special pins have extra pull up strength, there are R0 and R1 pull-up
resistors available, but for user, it's only need to set R1R0 as 00, 01,
10 or 11. So It needs config "mediatek,pull-up-adv" or
"mediatek,pull-down-adv" to support arguments for those special pins.
Valid arguments are from 0 to 3.
mediatek,tdsel: An integer describing the steps for output level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
mediatek,rdsel: An integer describing the steps for input level shifter
duty cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 63.
When config drive-strength, it can support some arguments, such as
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
It can only support 2/4/6/8/10/12/14/16mA in mt8183.
For I2C pins, there are existing generic driving setup and the specific
driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving
adjustment in generic driving setup. But in specific driving setup,
they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup for I2C pins, the existing generic driving setup will be
disabled. For some special features, we need the I2C pins specific
driving setup. The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of
the generic driving property.
We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific
driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
It is used to enable or disable the specific driving setup.
E1E0 is used to describe the detail strength specification of the I2C pin.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
Examples:
#include "mt8183-pinfunc.h"
...
{
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c0 {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <7>;
};
};
i2c1_pins_a: i2c1 {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
mediatek,drive-strength-adv = <4>;
};
};
...
};
};

2
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
View File

@ -57,6 +57,8 @@ Optional properties:
- st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
used to select GPIOs as interrupts).
- hwlocks: reference to a phandle of a hardware spinlock provider node.
- st,package: Indicates the SOC package used.
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
Example 1:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>

2
MAINTAINERS
View File

@ -1418,7 +1418,9 @@ M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/dts/bitmain/
F: drivers/pinctrl/pinctrl-bm1880.c
F: Documentation/devicetree/bindings/arm/bitmain.yaml
F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt
ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <robh@kernel.org>

2
arch/sh/include/cpu-sh4/cpu/sh7786.h
View File

@ -132,7 +132,7 @@ enum {
static inline u32 sh7786_mm_sel(void)
{
return __raw_readl(0xFC400020) & 0x7;
return __raw_readl((const volatile void __iomem *)0xFC400020) & 0x7;
}
#endif /* __CPU_SH7786_H__ */

2
drivers/gpio/gpiolib-devprop.c
View File

@ -10,6 +10,7 @@
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/export.h>
#include "gpiolib.h"
@ -56,3 +57,4 @@ void devprop_gpiochip_set_names(struct gpio_chip *chip,
kfree(names);
}
EXPORT_SYMBOL_GPL(devprop_gpiochip_set_names);

3
drivers/gpio/gpiolib.h
View File

@ -243,9 +243,6 @@ static inline int gpio_chip_hwgpio(const struct gpio_desc *desc)
return desc - &desc->gdev->descs[0];
}
void devprop_gpiochip_set_names(struct gpio_chip *chip,
const struct fwnode_handle *fwnode);
/* With descriptor prefix */
#define gpiod_emerg(desc, fmt, ...) \

8
drivers/pinctrl/Kconfig
View File

@ -108,6 +108,14 @@ config PINCTRL_AMD
Requires ACPI/FDT device enumeration code to set up a platform
device.
config PINCTRL_BM1880
bool "Bitmain BM1880 Pinctrl driver"
depends on OF && (ARCH_BITMAIN || COMPILE_TEST)
default ARCH_BITMAIN
select PINMUX
help
Pinctrl driver for Bitmain BM1880 SoC.
config PINCTRL_DA850_PUPD
tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups"
depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST)

1
drivers/pinctrl/Makefile
View File

@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o

10
drivers/pinctrl/cirrus/Kconfig
View File

@ -1,3 +1,13 @@
config PINCTRL_LOCHNAGAR
tristate "Cirrus Logic Lochnagar pinctrl driver"
depends on MFD_LOCHNAGAR
select PINMUX
select PINCONF
select GENERIC_PINCONF
help
This driver supports configuring the GPIO and other pin configuration
of the Cirrus Logic Lochnagar audio development board.
# This is all selected by the Madera MFD driver Kconfig options
config PINCTRL_MADERA
tristate

2
drivers/pinctrl/cirrus/Makefile
View File

@ -1,4 +1,6 @@
# Cirrus Logic pinctrl drivers
obj-$(CONFIG_PINCTRL_LOCHNAGAR) += pinctrl-lochnagar.o
pinctrl-madera-objs := pinctrl-madera-core.o
ifeq ($(CONFIG_PINCTRL_CS47L35),y)
pinctrl-madera-objs += pinctrl-cs47l35.o

1235
drivers/pinctrl/cirrus/pinctrl-lochnagar.c 100644
View File

File diff suppressed because it is too large Load Diff

25
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -449,7 +449,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
}
} else {
pin_reg = &ipctl->pin_regs[pin_id];
if (!pin_reg || pin_reg->conf_reg == -1) {
if (pin_reg->conf_reg == -1) {
seq_puts(s, "N/A");
return;
}
@ -785,7 +785,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
struct pinctrl_desc *imx_pinctrl_desc;
struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
struct regmap *gpr;
int ret, i;
@ -817,8 +816,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
ipctl->pin_regs[i].conf_reg = -1;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(&pdev->dev, res);
ipctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
@ -887,3 +885,22 @@ free:
return ret;
}
static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
return pinctrl_force_sleep(ipctl->pctl);
}
static int __maybe_unused imx_pinctrl_resume(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
return pinctrl_force_default(ipctl->pctl);
}
const struct dev_pm_ops imx_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
imx_pinctrl_resume)
};

1
drivers/pinctrl/freescale/pinctrl-imx.h
View File

@ -17,6 +17,7 @@
struct platform_device;
extern struct pinmux_ops imx_pmx_ops;
extern const struct dev_pm_ops imx_pinctrl_pm_ops;
/**
* struct imx_pin_mmio - MMIO pin configurations

1
drivers/pinctrl/freescale/pinctrl-imx8mq.c
View File

@ -339,6 +339,7 @@ static struct platform_driver imx8mq_pinctrl_driver = {
.driver = {
.name = "imx8mq-pinctrl",
.of_match_table = of_match_ptr(imx8mq_pinctrl_of_match),
.pm = &imx_pinctrl_pm_ops,
.suppress_bind_attrs = true,
},
.probe = imx8mq_pinctrl_probe,

2
drivers/pinctrl/freescale/pinctrl-scu.c
View File

@ -35,7 +35,7 @@ struct imx_sc_msg_resp_pad_get {
u32 val;
} __packed;
struct imx_sc_ipc *pinctrl_ipc_handle;
static struct imx_sc_ipc *pinctrl_ipc_handle;
int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
{

2
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -1710,6 +1710,8 @@ static int byt_gpio_probe(struct byt_gpio *vg)
#ifdef CONFIG_PM_SLEEP
vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
sizeof(*vg->saved_context), GFP_KERNEL);
if (!vg->saved_context)
return -ENOMEM;
#endif
ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
if (ret) {

18
drivers/pinctrl/intel/pinctrl-cedarfork.c
View File

@ -91,13 +91,13 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
PINCTRL_PIN(43, "MEMTRIP_N"),
PINCTRL_PIN(44, "UART0_RXD"),
PINCTRL_PIN(45, "UART0_TXD"),
PINCTRL_PIN(46, "UART1_RXD"),
PINCTRL_PIN(47, "UART1_TXD"),
PINCTRL_PIN(46, "GBE_UART_RXD"),
PINCTRL_PIN(47, "GBE_UART_TXD"),
/* WEST01 */
PINCTRL_PIN(48, "GBE_GPIO13"),
PINCTRL_PIN(49, "AUX_PWR"),
PINCTRL_PIN(50, "CPU_GP_2"),
PINCTRL_PIN(51, "CPU_GP_3"),
PINCTRL_PIN(50, "UART0_RTS"),
PINCTRL_PIN(51, "UART0_CTS"),
PINCTRL_PIN(52, "FAN_PWM_0"),
PINCTRL_PIN(53, "FAN_PWM_1"),
PINCTRL_PIN(54, "FAN_PWM_2"),
@ -201,8 +201,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
/* WESTF */
PINCTRL_PIN(145, "NAC_RMII_CLK"),
PINCTRL_PIN(146, "NAC_RGMII_CLK"),
PINCTRL_PIN(147, "NAC_SPARE0"),
PINCTRL_PIN(148, "NAC_SPARE1"),
PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
PINCTRL_PIN(149, "NAC_SPARE2"),
PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
@ -219,8 +219,8 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
PINCTRL_PIN(165, "NAC_GBE_SMB_CLK"),
PINCTRL_PIN(166, "NAC_GBE_SMB_DATA"),
PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
/* EAST2 */
PINCTRL_PIN(168, "USB_OC0_N"),
@ -232,7 +232,7 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
PINCTRL_PIN(174, "GBE_GPIO5"),
PINCTRL_PIN(175, "GBE_GPIO6"),
PINCTRL_PIN(176, "GBE_GPIO7"),
PINCTRL_PIN(177, "GBE_GPIO8"),
PINCTRL_PIN(177, "SPI_TPM_CS_N"),
PINCTRL_PIN(178, "GBE_GPIO9"),
PINCTRL_PIN(179, "GBE_GPIO10"),
PINCTRL_PIN(180, "GBE_GPIO11"),

66
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -81,6 +81,7 @@ struct intel_pad_context {
struct intel_community_context {
u32 *intmask;
u32 *hostown;
};
struct intel_pinctrl_context {
@ -1284,7 +1285,7 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
for (i = 0; i < pctrl->ncommunities; i++) {
struct intel_community *community = &pctrl->communities[i];
u32 *intmask;
u32 *intmask, *hostown;
intmask = devm_kcalloc(pctrl->dev, community->ngpps,
sizeof(*intmask), GFP_KERNEL);
@ -1292,6 +1293,13 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
return -ENOMEM;
communities[i].intmask = intmask;
hostown = devm_kcalloc(pctrl->dev, community->ngpps,
sizeof(*hostown), GFP_KERNEL);
if (!hostown)
return -ENOMEM;
communities[i].hostown = hostown;
}
pctrl->context.pads = pads;
@ -1466,7 +1474,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
return false;
}
int intel_pinctrl_suspend(struct device *dev)
int intel_pinctrl_suspend_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *communities;
@ -1501,11 +1509,15 @@ int intel_pinctrl_suspend(struct device *dev)
base = community->regs + community->ie_offset;
for (gpp = 0; gpp < community->ngpps; gpp++)
communities[i].intmask[gpp] = readl(base + gpp * 4);
base = community->regs + community->hostown_offset;
for (gpp = 0; gpp < community->ngpps; gpp++)
communities[i].hostown[gpp] = readl(base + gpp * 4);
}
return 0;
}
EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
{
@ -1527,7 +1539,32 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
}
}
int intel_pinctrl_resume(struct device *dev)
static u32
intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
{
u32 requested = 0;
unsigned int i;
for (i = 0; i < size; i++)
if (gpiochip_is_requested(chip, base + i))
requested |= BIT(i);
return requested;
}
static u32
intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
{
u32 curr, updated;
curr = readl(hostown);
updated = (curr & ~mask) | (value & mask);
writel(updated, hostown);
return curr;
}
int intel_pinctrl_resume_noirq(struct device *dev)
{
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
const struct intel_community_context *communities;
@ -1585,11 +1622,30 @@ int intel_pinctrl_resume(struct device *dev)
dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
readl(base + gpp * 4));
}
base = community->regs + community->hostown_offset;
for (gpp = 0; gpp < community->ngpps; gpp++) {
const struct intel_padgroup *padgrp = &community->gpps[gpp];
u32 requested = 0, value = 0;
u32 saved = communities[i].hostown[gpp];
if (padgrp->gpio_base < 0)
continue;
requested = intel_gpio_is_requested(&pctrl->chip,
padgrp->gpio_base, padgrp->size);
value = intel_gpio_update_pad_mode(base + gpp * 4,
requested, saved);
if ((value ^ saved) & requested) {
dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
i, gpp, value, saved);
}
}
}
return 0;
}
EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
#endif
MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");

11
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -177,13 +177,14 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
#ifdef CONFIG_PM_SLEEP
int intel_pinctrl_suspend(struct device *dev);
int intel_pinctrl_resume(struct device *dev);
int intel_pinctrl_suspend_noirq(struct device *dev);
int intel_pinctrl_resume_noirq(struct device *dev);
#endif
#define INTEL_PINCTRL_PM_OPS(_name) \
const struct dev_pm_ops _name = { \
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, intel_pinctrl_resume) \
#define INTEL_PINCTRL_PM_OPS(_name) \
const struct dev_pm_ops _name = { \
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
intel_pinctrl_resume_noirq) \
}
#endif /* PINCTRL_INTEL_H */

7
drivers/pinctrl/mediatek/Kconfig
View File

@ -113,6 +113,13 @@ config PINCTRL_MT8183
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8516
bool "Mediatek MT8516 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK
# For PMIC
config PINCTRL_MT6397
bool "Mediatek MT6397 pin control"

1
drivers/pinctrl/mediatek/Makefile
View File

@ -17,4 +17,5 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o

50
drivers/pinctrl/mediatek/pinctrl-mt8183.c
View File

@ -472,6 +472,51 @@ static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = {
PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_e1e0en_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 20, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 15, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 12, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 7, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 12, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 9, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 19, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 22, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 24, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 27, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 17, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_e0_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 21, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 16, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 8, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 13, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 10, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 20, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 23, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 25, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 15, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 28, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt8183_pin_e1_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 22, 1),
PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 9, 1),
PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 14, 1),
PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 11, 1),
PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 21, 1),
PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 24, 1),
PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 26, 1),
PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 16, 1),
PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 29, 1),
PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 19, 1),
};
static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range),
@ -485,6 +530,9 @@ static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range),
[PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8183_pin_e1e0en_range),
[PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8183_pin_e0_range),
[PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8183_pin_e1_range),
};
static const char * const mt8183_pinctrl_register_base_names[] = {
@ -517,6 +565,8 @@ static const struct mtk_pin_soc mt8183_data = {
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_pull_get = mtk_pinconf_adv_pull_get,
.adv_pull_set = mtk_pinconf_adv_pull_set,
.adv_drive_get = mtk_pinconf_adv_drive_get,
.adv_drive_set = mtk_pinconf_adv_drive_set,
};
static const struct of_device_id mt8183_pinctrl_of_match[] = {

362
drivers/pinctrl/mediatek/pinctrl-mt8516.c 100644
View File

@ -0,0 +1,362 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Min.Guo <min.guo@mediatek.com>
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8516.h"
static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
};
static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
};
static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
};
static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
};
static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
ARRAY_SIZE(mt8516_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
ARRAY_SIZE(mt8516_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
.pins = mtk_pins_mt8516,
.npins = ARRAY_SIZE(mtk_pins_mt8516),
.grp_desc = mt8516_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
.pin_drv_grp = mt8516_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
.spec_pull_set = mt8516_spec_pull_set,
.spec_ies_smt_set = mt8516_ies_smt_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0500,
.pullsel_offset = 0x0600,
.dout_offset = 0x0100,
.din_offset = 0x0200,
.pinmux_offset = 0x0300,
.type1_start = 125,
.type1_end = 125,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 169,
.db_cnt = 64,
},
};
static int mt8516_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
}
static const struct of_device_id mt8516_pctrl_match[] = {
{
.compatible = "mediatek,mt8516-pinctrl",
},
{}
};
MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8516_pinctrl_probe,
.driver = {
.name = "mediatek-mt8516-pinctrl",
.of_match_table = mt8516_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);

49
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
View File

@ -674,3 +674,52 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
return 0;
}
int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
int err;
int en = arg & 1;
int e0 = !!(arg & 2);
int e1 = !!(arg & 4);
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
if (err)
return err;
if (!en)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
if (err)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
if (err)
return err;
return err;
}
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val)
{
u32 en, e0, e1;
int err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
if (err)
return err;
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
if (err)
return err;
*val = (en | e0 << 1 | e1 << 2) & 0x7;
return 0;
}

11
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
View File

@ -63,6 +63,9 @@ enum {
PINCTRL_PIN_REG_IES,
PINCTRL_PIN_REG_PULLEN,
PINCTRL_PIN_REG_PULLSEL,
PINCTRL_PIN_REG_DRV_EN,
PINCTRL_PIN_REG_DRV_E0,
PINCTRL_PIN_REG_DRV_E1,
PINCTRL_PIN_REG_MAX,
};
@ -224,6 +227,10 @@ struct mtk_pin_soc {
int (*adv_pull_get)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 *val);
int (*adv_drive_set)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int (*adv_drive_get)(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
/* Specific driver data */
void *driver_data;
@ -287,5 +294,9 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, bool pullup,
u32 *val);
int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
#endif /* __PINCTRL_MTK_COMMON_V2_H */

1182
drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h 100644
View File

File diff suppressed because it is too large Load Diff

21
drivers/pinctrl/mediatek/pinctrl-paris.c
View File

@ -20,12 +20,14 @@
#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
static const struct pinconf_generic_params mtk_custom_bindings[] = {
{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
{"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
};
#ifdef CONFIG_DEBUG_FS
@ -34,6 +36,7 @@ static const struct pin_config_item mtk_conf_items[] = {
PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
};
#endif
@ -176,6 +179,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
return -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_DRV_ADV:
if (hw->soc->adv_drive_get) {
err = hw->soc->adv_drive_get(hw, desc, &ret);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
return -ENOTSUPP;
}
@ -311,6 +323,15 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
return -ENOTSUPP;
}
break;
case MTK_PIN_CONFIG_DRV_ADV:
if (hw->soc->adv_drive_set) {
err = hw->soc->adv_drive_set(hw, desc, arg);
if (err)
return err;
} else {
return -ENOTSUPP;
}
break;
default:
err = -ENOTSUPP;
}

4
drivers/pinctrl/pinctrl-amd.c
View File

@ -930,8 +930,8 @@ static int amd_gpio_probe(struct platform_device *pdev)
goto out2;
}
ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
KBUILD_MODNAME, gpio_dev);
ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
if (ret)
goto out2;

19
drivers/pinctrl/pinctrl-artpec6.c
View File

@ -688,8 +688,9 @@ static void artpec6_pmx_select_func(struct pinctrl_dev *pctldev,
}
}
int artpec6_pmx_enable(struct pinctrl_dev *pctldev, unsigned int function,
unsigned int group)
static int artpec6_pmx_set(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
@ -702,18 +703,6 @@ int artpec6_pmx_enable(struct pinctrl_dev *pctldev, unsigned int function,
return 0;
}
void artpec6_pmx_disable(struct pinctrl_dev *pctldev, unsigned int function,
unsigned int group)
{
struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
dev_dbg(pmx->dev, "disabling %s function for pin group %s\n",
artpec6_pmx_get_fname(pctldev, function),
artpec6_get_group_name(pctldev, group));
artpec6_pmx_select_func(pctldev, function, group, false);
}
static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin)
@ -737,7 +726,7 @@ static const struct pinmux_ops artpec6_pmx_ops = {
.get_functions_count = artpec6_pmx_get_functions_count,
.get_function_name = artpec6_pmx_get_fname,
.get_function_groups = artpec6_pmx_get_fgroups,
.set_mux = artpec6_pmx_enable,
.set_mux = artpec6_pmx_set,
.gpio_request_enable = artpec6_pmx_request_gpio,
};

2
drivers/pinctrl/pinctrl-axp209.c
View File

@ -366,6 +366,8 @@ static int axp20x_build_funcs_groups(struct platform_device *pdev)
pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
npins, sizeof(char *),
GFP_KERNEL);
if (!pctl->funcs[i].groups)
return -ENOMEM;
for (pin = 0; pin < npins; pin++)
pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
}

965
drivers/pinctrl/pinctrl-bm1880.c 100644
View File

@ -0,0 +1,965 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Bitmain BM1880 SoC Pinctrl driver
*
* Copyright (c) 2019 Linaro Ltd.
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/slab.h>
#include "core.h"
#include "pinctrl-utils.h"
#define BM1880_REG_MUX 0x20
/**
* struct bm1880_pinctrl - driver data
* @base: Pinctrl base address
* @pctrl: Pinctrl device
* @groups: Pingroups
* @ngroups: Number of @groups
* @funcs: Pinmux functions
* @nfuncs: Number of @funcs
*/
struct bm1880_pinctrl {
void __iomem *base;
struct pinctrl_dev *pctrldev;
const struct bm1880_pctrl_group *groups;
unsigned int ngroups;
const struct bm1880_pinmux_function *funcs;
unsigned int nfuncs;
};
/**
* struct bm1880_pctrl_group - pinctrl group
* @name: Name of the group
* @pins: Array of pins belonging to this group
* @npins: Number of @pins
*/
struct bm1880_pctrl_group {
const char *name;
const unsigned int *pins;
const unsigned int npins;
};
/**
* struct bm1880_pinmux_function - a pinmux function
* @name: Name of the pinmux function.
* @groups: List of pingroups for this function.
* @ngroups: Number of entries in @groups.
* @mux_val: Selector for this function
* @mux_mask: Mask for function specific selector
* @mux: Offset of function specific mux
* @mux_shift: Shift for function specific selector
*/
struct bm1880_pinmux_function {
const char *name;
const char * const *groups;
unsigned int ngroups;
u32 mux_val;
u32 mux_mask;
u32 mux;
u8 mux_shift;
};
static const struct pinctrl_pin_desc bm1880_pins[] = {
PINCTRL_PIN(0, "MIO0"),
PINCTRL_PIN(1, "MIO1"),
PINCTRL_PIN(2, "MIO2"),
PINCTRL_PIN(3, "MIO3"),
PINCTRL_PIN(4, "MIO4"),
PINCTRL_PIN(5, "MIO5"),
PINCTRL_PIN(6, "MIO6"),
PINCTRL_PIN(7, "MIO7"),
PINCTRL_PIN(8, "MIO8"),
PINCTRL_PIN(9, "MIO9"),
PINCTRL_PIN(10, "MIO10"),
PINCTRL_PIN(11, "MIO11"),
PINCTRL_PIN(12, "MIO12"),
PINCTRL_PIN(13, "MIO13"),
PINCTRL_PIN(14, "MIO14"),
PINCTRL_PIN(15, "MIO15"),
PINCTRL_PIN(16, "MIO16"),
PINCTRL_PIN(17, "MIO17"),
PINCTRL_PIN(18, "MIO18"),
PINCTRL_PIN(19, "MIO19"),
PINCTRL_PIN(20, "MIO20"),
PINCTRL_PIN(21, "MIO21"),
PINCTRL_PIN(22, "MIO22"),
PINCTRL_PIN(23, "MIO23"),
PINCTRL_PIN(24, "MIO24"),
PINCTRL_PIN(25, "MIO25"),
PINCTRL_PIN(26, "MIO26"),
PINCTRL_PIN(27, "MIO27"),
PINCTRL_PIN(28, "MIO28"),
PINCTRL_PIN(29, "MIO29"),
PINCTRL_PIN(30, "MIO30"),
PINCTRL_PIN(31, "MIO31"),
PINCTRL_PIN(32, "MIO32"),
PINCTRL_PIN(33, "MIO33"),
PINCTRL_PIN(34, "MIO34"),
PINCTRL_PIN(35, "MIO35"),
PINCTRL_PIN(36, "MIO36"),
PINCTRL_PIN(37, "MIO37"),
PINCTRL_PIN(38, "MIO38"),
PINCTRL_PIN(39, "MIO39"),
PINCTRL_PIN(40, "MIO40"),
PINCTRL_PIN(41, "MIO41"),
PINCTRL_PIN(42, "MIO42"),
PINCTRL_PIN(43, "MIO43"),
PINCTRL_PIN(44, "MIO44"),
PINCTRL_PIN(45, "MIO45"),
PINCTRL_PIN(46, "MIO46"),
PINCTRL_PIN(47, "MIO47"),
PINCTRL_PIN(48, "MIO48"),
PINCTRL_PIN(49, "MIO49"),
PINCTRL_PIN(50, "MIO50"),
PINCTRL_PIN(51, "MIO51"),
PINCTRL_PIN(52, "MIO52"),
PINCTRL_PIN(53, "MIO53"),
PINCTRL_PIN(54, "MIO54"),
PINCTRL_PIN(55, "MIO55"),
PINCTRL_PIN(56, "MIO56"),
PINCTRL_PIN(57, "MIO57"),
PINCTRL_PIN(58, "MIO58"),
PINCTRL_PIN(59, "MIO59"),
PINCTRL_PIN(60, "MIO60"),
PINCTRL_PIN(61, "MIO61"),
PINCTRL_PIN(62, "MIO62"),
PINCTRL_PIN(63, "MIO63"),
PINCTRL_PIN(64, "MIO64"),
PINCTRL_PIN(65, "MIO65"),
PINCTRL_PIN(66, "MIO66"),
PINCTRL_PIN(67, "MIO67"),
PINCTRL_PIN(68, "MIO68"),
PINCTRL_PIN(69, "MIO69"),
PINCTRL_PIN(70, "MIO70"),
PINCTRL_PIN(71, "MIO71"),
PINCTRL_PIN(72, "MIO72"),
PINCTRL_PIN(73, "MIO73"),
PINCTRL_PIN(74, "MIO74"),
PINCTRL_PIN(75, "MIO75"),
PINCTRL_PIN(76, "MIO76"),
PINCTRL_PIN(77, "MIO77"),
PINCTRL_PIN(78, "MIO78"),
PINCTRL_PIN(79, "MIO79"),
PINCTRL_PIN(80, "MIO80"),
PINCTRL_PIN(81, "MIO81"),
PINCTRL_PIN(82, "MIO82"),
PINCTRL_PIN(83, "MIO83"),
PINCTRL_PIN(84, "MIO84"),
PINCTRL_PIN(85, "MIO85"),
PINCTRL_PIN(86, "MIO86"),
PINCTRL_PIN(87, "MIO87"),
PINCTRL_PIN(88, "MIO88"),
PINCTRL_PIN(89, "MIO89"),
PINCTRL_PIN(90, "MIO90"),
PINCTRL_PIN(91, "MIO91"),
PINCTRL_PIN(92, "MIO92"),
PINCTRL_PIN(93, "MIO93"),
PINCTRL_PIN(94, "MIO94"),
PINCTRL_PIN(95, "MIO95"),
PINCTRL_PIN(96, "MIO96"),
PINCTRL_PIN(97, "MIO97"),
PINCTRL_PIN(98, "MIO98"),
PINCTRL_PIN(99, "MIO99"),
PINCTRL_PIN(100, "MIO100"),
PINCTRL_PIN(101, "MIO101"),
PINCTRL_PIN(102, "MIO102"),
PINCTRL_PIN(103, "MIO103"),
PINCTRL_PIN(104, "MIO104"),
PINCTRL_PIN(105, "MIO105"),
PINCTRL_PIN(106, "MIO106"),
PINCTRL_PIN(107, "MIO107"),
PINCTRL_PIN(108, "MIO108"),
PINCTRL_PIN(109, "MIO109"),
PINCTRL_PIN(110, "MIO110"),
PINCTRL_PIN(111, "MIO111"),
};
enum bm1880_pinmux_functions {
F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2,
F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10,
F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17,
F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24,
F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31,
F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1,
F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4,
F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11,
F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2,
F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10,
F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17,
F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24,
F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31,
F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38,
F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45,
F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52,
F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59,
F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66,
F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0,
F_max
};
static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 16 };
static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 };
static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 };
static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24,
25, 26 };
static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 39, 40, 41, 42 };
static const unsigned int pwm0_pins[] = { 29 };
static const unsigned int pwm1_pins[] = { 30 };
static const unsigned int pwm2_pins[] = { 34 };
static const unsigned int pwm3_pins[] = { 35 };
static const unsigned int pwm4_pins[] = { 43 };
static const unsigned int pwm5_pins[] = { 44 };
static const unsigned int pwm6_pins[] = { 45 };
static const unsigned int pwm7_pins[] = { 46 };
static const unsigned int pwm8_pins[] = { 47 };
static const unsigned int pwm9_pins[] = { 48 };
static const unsigned int pwm10_pins[] = { 49 };
static const unsigned int pwm11_pins[] = { 50 };
static const unsigned int pwm12_pins[] = { 51 };
static const unsigned int pwm13_pins[] = { 52 };
static const unsigned int pwm14_pins[] = { 53 };
static const unsigned int pwm15_pins[] = { 54 };
static const unsigned int pwm16_pins[] = { 55 };
static const unsigned int pwm17_pins[] = { 56 };
static const unsigned int pwm18_pins[] = { 57 };
static const unsigned int pwm19_pins[] = { 58 };
static const unsigned int pwm20_pins[] = { 59 };
static const unsigned int pwm21_pins[] = { 60 };
static const unsigned int pwm22_pins[] = { 61 };
static const unsigned int pwm23_pins[] = { 62 };
static const unsigned int pwm24_pins[] = { 97 };
static const unsigned int pwm25_pins[] = { 98 };
static const unsigned int pwm26_pins[] = { 99 };
static const unsigned int pwm27_pins[] = { 100 };
static const unsigned int pwm28_pins[] = { 101 };
static const unsigned int pwm29_pins[] = { 102 };
static const unsigned int pwm30_pins[] = { 103 };
static const unsigned int pwm31_pins[] = { 104 };
static const unsigned int pwm32_pins[] = { 105 };
static const unsigned int pwm33_pins[] = { 106 };
static const unsigned int pwm34_pins[] = { 107 };
static const unsigned int pwm35_pins[] = { 108 };
static const unsigned int pwm36_pins[] = { 109 };
static const unsigned int pwm37_pins[] = { 110 };
static const unsigned int i2c0_pins[] = { 63, 64 };
static const unsigned int i2c1_pins[] = { 65, 66 };
static const unsigned int i2c2_pins[] = { 67, 68 };
static const unsigned int i2c3_pins[] = { 69, 70 };
static const unsigned int i2c4_pins[] = { 71, 72 };
static const unsigned int uart0_pins[] = { 73, 74 };
static const unsigned int uart1_pins[] = { 75, 76 };
static const unsigned int uart2_pins[] = { 77, 78 };
static const unsigned int uart3_pins[] = { 79, 80 };
static const unsigned int uart4_pins[] = { 81, 82 };
static const unsigned int uart5_pins[] = { 83, 84 };
static const unsigned int uart6_pins[] = { 85, 86 };
static const unsigned int uart7_pins[] = { 87, 88 };
static const unsigned int uart8_pins[] = { 89, 90 };
static const unsigned int uart9_pins[] = { 91, 92 };
static const unsigned int uart10_pins[] = { 93, 94 };
static const unsigned int uart11_pins[] = { 95, 96 };
static const unsigned int uart12_pins[] = { 73, 74, 75, 76 };
static const unsigned int uart13_pins[] = { 77, 78, 83, 84 };
static const unsigned int uart14_pins[] = { 79, 80, 85, 86 };
static const unsigned int uart15_pins[] = { 81, 82, 87, 88 };
static const unsigned int gpio0_pins[] = { 97 };
static const unsigned int gpio1_pins[] = { 98 };
static const unsigned int gpio2_pins[] = { 99 };
static const unsigned int gpio3_pins[] = { 100 };
static const unsigned int gpio4_pins[] = { 101 };
static const unsigned int gpio5_pins[] = { 102 };
static const unsigned int gpio6_pins[] = { 103 };
static const unsigned int gpio7_pins[] = { 104 };
static const unsigned int gpio8_pins[] = { 105 };
static const unsigned int gpio9_pins[] = { 106 };
static const unsigned int gpio10_pins[] = { 107 };
static const unsigned int gpio11_pins[] = { 108 };
static const unsigned int gpio12_pins[] = { 109 };
static const unsigned int gpio13_pins[] = { 110 };
static const unsigned int gpio14_pins[] = { 43 };
static const unsigned int gpio15_pins[] = { 44 };
static const unsigned int gpio16_pins[] = { 45 };
static const unsigned int gpio17_pins[] = { 46 };
static const unsigned int gpio18_pins[] = { 47 };
static const unsigned int gpio19_pins[] = { 48 };
static const unsigned int gpio20_pins[] = { 49 };
static const unsigned int gpio21_pins[] = { 50 };
static const unsigned int gpio22_pins[] = { 51 };
static const unsigned int gpio23_pins[] = { 52 };
static const unsigned int gpio24_pins[] = { 53 };
static const unsigned int gpio25_pins[] = { 54 };
static const unsigned int gpio26_pins[] = { 55 };
static const unsigned int gpio27_pins[] = { 56 };
static const unsigned int gpio28_pins[] = { 57 };
static const unsigned int gpio29_pins[] = { 58 };
static const unsigned int gpio30_pins[] = { 59 };
static const unsigned int gpio31_pins[] = { 60 };
static const unsigned int gpio32_pins[] = { 61 };
static const unsigned int gpio33_pins[] = { 62 };
static const unsigned int gpio34_pins[] = { 63 };
static const unsigned int gpio35_pins[] = { 64 };
static const unsigned int gpio36_pins[] = { 65 };
static const unsigned int gpio37_pins[] = { 66 };
static const unsigned int gpio38_pins[] = { 67 };
static const unsigned int gpio39_pins[] = { 68 };
static const unsigned int gpio40_pins[] = { 69 };
static const unsigned int gpio41_pins[] = { 70 };
static const unsigned int gpio42_pins[] = { 71 };
static const unsigned int gpio43_pins[] = { 72 };
static const unsigned int gpio44_pins[] = { 73 };
static const unsigned int gpio45_pins[] = { 74 };
static const unsigned int gpio46_pins[] = { 75 };
static const unsigned int gpio47_pins[] = { 76 };
static const unsigned int gpio48_pins[] = { 77 };
static const unsigned int gpio49_pins[] = { 78 };
static const unsigned int gpio50_pins[] = { 79 };
static const unsigned int gpio51_pins[] = { 80 };
static const unsigned int gpio52_pins[] = { 81 };
static const unsigned int gpio53_pins[] = { 82 };
static const unsigned int gpio54_pins[] = { 83 };
static const unsigned int gpio55_pins[] = { 84 };
static const unsigned int gpio56_pins[] = { 85 };
static const unsigned int gpio57_pins[] = { 86 };
static const unsigned int gpio58_pins[] = { 87 };
static const unsigned int gpio59_pins[] = { 88 };
static const unsigned int gpio60_pins[] = { 89 };
static const unsigned int gpio61_pins[] = { 90 };
static const unsigned int gpio62_pins[] = { 91 };
static const unsigned int gpio63_pins[] = { 92 };
static const unsigned int gpio64_pins[] = { 93 };
static const unsigned int gpio65_pins[] = { 94 };
static const unsigned int gpio66_pins[] = { 95 };
static const unsigned int gpio67_pins[] = { 96 };
static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57, 58 };
static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 };
static const unsigned int i2s0_mclkin_pins[] = { 97 };
static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 };
static const unsigned int i2s1_mclkin_pins[] = { 98 };
static const unsigned int spi0_pins[] = { 59, 60, 61, 62 };
#define BM1880_PINCTRL_GRP(nm) \
{ \
.name = #nm "_grp", \
.pins = nm ## _pins, \
.npins = ARRAY_SIZE(nm ## _pins), \
}
static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = {
BM1880_PINCTRL_GRP(nand),
BM1880_PINCTRL_GRP(spi),
BM1880_PINCTRL_GRP(emmc),
BM1880_PINCTRL_GRP(sdio),
BM1880_PINCTRL_GRP(eth0),
BM1880_PINCTRL_GRP(pwm0),
BM1880_PINCTRL_GRP(pwm1),
BM1880_PINCTRL_GRP(pwm2),
BM1880_PINCTRL_GRP(pwm3),
BM1880_PINCTRL_GRP(pwm4),
BM1880_PINCTRL_GRP(pwm5),
BM1880_PINCTRL_GRP(pwm6),
BM1880_PINCTRL_GRP(pwm7),
BM1880_PINCTRL_GRP(pwm8),
BM1880_PINCTRL_GRP(pwm9),
BM1880_PINCTRL_GRP(pwm10),
BM1880_PINCTRL_GRP(pwm11),
BM1880_PINCTRL_GRP(pwm12),
BM1880_PINCTRL_GRP(pwm13),
BM1880_PINCTRL_GRP(pwm14),
BM1880_PINCTRL_GRP(pwm15),
BM1880_PINCTRL_GRP(pwm16),
BM1880_PINCTRL_GRP(pwm17),
BM1880_PINCTRL_GRP(pwm18),
BM1880_PINCTRL_GRP(pwm19),
BM1880_PINCTRL_GRP(pwm20),
BM1880_PINCTRL_GRP(pwm21),
BM1880_PINCTRL_GRP(pwm22),
BM1880_PINCTRL_GRP(pwm23),
BM1880_PINCTRL_GRP(pwm24),
BM1880_PINCTRL_GRP(pwm25),
BM1880_PINCTRL_GRP(pwm26),
BM1880_PINCTRL_GRP(pwm27),
BM1880_PINCTRL_GRP(pwm28),
BM1880_PINCTRL_GRP(pwm29),
BM1880_PINCTRL_GRP(pwm30),
BM1880_PINCTRL_GRP(pwm31),
BM1880_PINCTRL_GRP(pwm32),
BM1880_PINCTRL_GRP(pwm33),
BM1880_PINCTRL_GRP(pwm34),
BM1880_PINCTRL_GRP(pwm35),
BM1880_PINCTRL_GRP(pwm36),
BM1880_PINCTRL_GRP(i2c0),
BM1880_PINCTRL_GRP(i2c1),
BM1880_PINCTRL_GRP(i2c2),
BM1880_PINCTRL_GRP(i2c3),
BM1880_PINCTRL_GRP(i2c4),
BM1880_PINCTRL_GRP(uart0),
BM1880_PINCTRL_GRP(uart1),
BM1880_PINCTRL_GRP(uart2),
BM1880_PINCTRL_GRP(uart3),
BM1880_PINCTRL_GRP(uart4),
BM1880_PINCTRL_GRP(uart5),
BM1880_PINCTRL_GRP(uart6),
BM1880_PINCTRL_GRP(uart7),
BM1880_PINCTRL_GRP(uart8),
BM1880_PINCTRL_GRP(uart9),
BM1880_PINCTRL_GRP(uart10),
BM1880_PINCTRL_GRP(uart11),
BM1880_PINCTRL_GRP(uart12),
BM1880_PINCTRL_GRP(uart13),
BM1880_PINCTRL_GRP(uart14),
BM1880_PINCTRL_GRP(uart15),
BM1880_PINCTRL_GRP(gpio0),
BM1880_PINCTRL_GRP(gpio1),
BM1880_PINCTRL_GRP(gpio2),
BM1880_PINCTRL_GRP(gpio3),
BM1880_PINCTRL_GRP(gpio4),
BM1880_PINCTRL_GRP(gpio5),
BM1880_PINCTRL_GRP(gpio6),
BM1880_PINCTRL_GRP(gpio7),
BM1880_PINCTRL_GRP(gpio8),
BM1880_PINCTRL_GRP(gpio9),
BM1880_PINCTRL_GRP(gpio10),
BM1880_PINCTRL_GRP(gpio11),
BM1880_PINCTRL_GRP(gpio12),
BM1880_PINCTRL_GRP(gpio13),
BM1880_PINCTRL_GRP(gpio14),
BM1880_PINCTRL_GRP(gpio15),
BM1880_PINCTRL_GRP(gpio16),
BM1880_PINCTRL_GRP(gpio17),
BM1880_PINCTRL_GRP(gpio18),
BM1880_PINCTRL_GRP(gpio19),
BM1880_PINCTRL_GRP(gpio20),
BM1880_PINCTRL_GRP(gpio21),
BM1880_PINCTRL_GRP(gpio22),
BM1880_PINCTRL_GRP(gpio23),
BM1880_PINCTRL_GRP(gpio24),
BM1880_PINCTRL_GRP(gpio25),
BM1880_PINCTRL_GRP(gpio26),
BM1880_PINCTRL_GRP(gpio27),
BM1880_PINCTRL_GRP(gpio28),
BM1880_PINCTRL_GRP(gpio29),
BM1880_PINCTRL_GRP(gpio30),
BM1880_PINCTRL_GRP(gpio31),
BM1880_PINCTRL_GRP(gpio32),
BM1880_PINCTRL_GRP(gpio33),
BM1880_PINCTRL_GRP(gpio34),
BM1880_PINCTRL_GRP(gpio35),
BM1880_PINCTRL_GRP(gpio36),
BM1880_PINCTRL_GRP(gpio37),
BM1880_PINCTRL_GRP(gpio38),
BM1880_PINCTRL_GRP(gpio39),
BM1880_PINCTRL_GRP(gpio40),
BM1880_PINCTRL_GRP(gpio41),
BM1880_PINCTRL_GRP(gpio42),
BM1880_PINCTRL_GRP(gpio43),
BM1880_PINCTRL_GRP(gpio44),
BM1880_PINCTRL_GRP(gpio45),
BM1880_PINCTRL_GRP(gpio46),
BM1880_PINCTRL_GRP(gpio47),
BM1880_PINCTRL_GRP(gpio48),
BM1880_PINCTRL_GRP(gpio49),
BM1880_PINCTRL_GRP(gpio50),
BM1880_PINCTRL_GRP(gpio51),
BM1880_PINCTRL_GRP(gpio52),
BM1880_PINCTRL_GRP(gpio53),
BM1880_PINCTRL_GRP(gpio54),
BM1880_PINCTRL_GRP(gpio55),
BM1880_PINCTRL_GRP(gpio56),
BM1880_PINCTRL_GRP(gpio57),
BM1880_PINCTRL_GRP(gpio58),
BM1880_PINCTRL_GRP(gpio59),
BM1880_PINCTRL_GRP(gpio60),
BM1880_PINCTRL_GRP(gpio61),
BM1880_PINCTRL_GRP(gpio62),
BM1880_PINCTRL_GRP(gpio63),
BM1880_PINCTRL_GRP(gpio64),
BM1880_PINCTRL_GRP(gpio65),
BM1880_PINCTRL_GRP(gpio66),
BM1880_PINCTRL_GRP(gpio67),
BM1880_PINCTRL_GRP(eth1),
BM1880_PINCTRL_GRP(i2s0),
BM1880_PINCTRL_GRP(i2s0_mclkin),
BM1880_PINCTRL_GRP(i2s1),
BM1880_PINCTRL_GRP(i2s1_mclkin),
BM1880_PINCTRL_GRP(spi0),
};
static const char * const nand_group[] = { "nand_grp" };
static const char * const spi_group[] = { "spi_grp" };
static const char * const emmc_group[] = { "emmc_grp" };
static const char * const sdio_group[] = { "sdio_grp" };
static const char * const eth0_group[] = { "eth0_grp" };
static const char * const pwm0_group[] = { "pwm0_grp" };
static const char * const pwm1_group[] = { "pwm1_grp" };
static const char * const pwm2_group[] = { "pwm2_grp" };
static const char * const pwm3_group[] = { "pwm3_grp" };
static const char * const pwm4_group[] = { "pwm4_grp" };
static const char * const pwm5_group[] = { "pwm5_grp" };
static const char * const pwm6_group[] = { "pwm6_grp" };
static const char * const pwm7_group[] = { "pwm7_grp" };
static const char * const pwm8_group[] = { "pwm8_grp" };
static const char * const pwm9_group[] = { "pwm9_grp" };
static const char * const pwm10_group[] = { "pwm10_grp" };
static const char * const pwm11_group[] = { "pwm11_grp" };
static const char * const pwm12_group[] = { "pwm12_grp" };
static const char * const pwm13_group[] = { "pwm13_grp" };
static const char * const pwm14_group[] = { "pwm14_grp" };
static const char * const pwm15_group[] = { "pwm15_grp" };
static const char * const pwm16_group[] = { "pwm16_grp" };
static const char * const pwm17_group[] = { "pwm17_grp" };
static const char * const pwm18_group[] = { "pwm18_grp" };
static const char * const pwm19_group[] = { "pwm19_grp" };
static const char * const pwm20_group[] = { "pwm20_grp" };
static const char * const pwm21_group[] = { "pwm21_grp" };
static const char * const pwm22_group[] = { "pwm22_grp" };
static const char * const pwm23_group[] = { "pwm23_grp" };
static const char * const pwm24_group[] = { "pwm24_grp" };
static const char * const pwm25_group[] = { "pwm25_grp" };
static const char * const pwm26_group[] = { "pwm26_grp" };
static const char * const pwm27_group[] = { "pwm27_grp" };
static const char * const pwm28_group[] = { "pwm28_grp" };
static const char * const pwm29_group[] = { "pwm29_grp" };
static const char * const pwm30_group[] = { "pwm30_grp" };
static const char * const pwm31_group[] = { "pwm31_grp" };
static const char * const pwm32_group[] = { "pwm32_grp" };
static const char * const pwm33_group[] = { "pwm33_grp" };
static const char * const pwm34_group[] = { "pwm34_grp" };
static const char * const pwm35_group[] = { "pwm35_grp" };
static const char * const pwm36_group[] = { "pwm36_grp" };
static const char * const pwm37_group[] = { "pwm37_grp" };
static const char * const i2c0_group[] = { "i2c0_grp" };
static const char * const i2c1_group[] = { "i2c1_grp" };
static const char * const i2c2_group[] = { "i2c2_grp" };
static const char * const i2c3_group[] = { "i2c3_grp" };
static const char * const i2c4_group[] = { "i2c4_grp" };
static const char * const uart0_group[] = { "uart0_grp" };
static const char * const uart1_group[] = { "uart1_grp" };
static const char * const uart2_group[] = { "uart2_grp" };
static const char * const uart3_group[] = { "uart3_grp" };
static const char * const uart4_group[] = { "uart4_grp" };
static const char * const uart5_group[] = { "uart5_grp" };
static const char * const uart6_group[] = { "uart6_grp" };
static const char * const uart7_group[] = { "uart7_grp" };
static const char * const uart8_group[] = { "uart8_grp" };
static const char * const uart9_group[] = { "uart9_grp" };
static const char * const uart10_group[] = { "uart10_grp" };
static const char * const uart11_group[] = { "uart11_grp" };
static const char * const uart12_group[] = { "uart12_grp" };
static const char * const uart13_group[] = { "uart13_grp" };
static const char * const uart14_group[] = { "uart14_grp" };
static const char * const uart15_group[] = { "uart15_grp" };
static const char * const gpio0_group[] = { "gpio0_grp" };
static const char * const gpio1_group[] = { "gpio1_grp" };
static const char * const gpio2_group[] = { "gpio2_grp" };
static const char * const gpio3_group[] = { "gpio3_grp" };
static const char * const gpio4_group[] = { "gpio4_grp" };
static const char * const gpio5_group[] = { "gpio5_grp" };
static const char * const gpio6_group[] = { "gpio6_grp" };
static const char * const gpio7_group[] = { "gpio7_grp" };
static const char * const gpio8_group[] = { "gpio8_grp" };
static const char * const gpio9_group[] = { "gpio9_grp" };
static const char * const gpio10_group[] = { "gpio10_grp" };
static const char * const gpio11_group[] = { "gpio11_grp" };
static const char * const gpio12_group[] = { "gpio12_grp" };
static const char * const gpio13_group[] = { "gpio13_grp" };
static const char * const gpio14_group[] = { "gpio14_grp" };
static const char * const gpio15_group[] = { "gpio15_grp" };
static const char * const gpio16_group[] = { "gpio16_grp" };
static const char * const gpio17_group[] = { "gpio17_grp" };
static const char * const gpio18_group[] = { "gpio18_grp" };
static const char * const gpio19_group[] = { "gpio19_grp" };
static const char * const gpio20_group[] = { "gpio20_grp" };
static const char * const gpio21_group[] = { "gpio21_grp" };
static const char * const gpio22_group[] = { "gpio22_grp" };
static const char * const gpio23_group[] = { "gpio23_grp" };
static const char * const gpio24_group[] = { "gpio24_grp" };
static const char * const gpio25_group[] = { "gpio25_grp" };
static const char * const gpio26_group[] = { "gpio26_grp" };
static const char * const gpio27_group[] = { "gpio27_grp" };
static const char * const gpio28_group[] = { "gpio28_grp" };
static const char * const gpio29_group[] = { "gpio29_grp" };
static const char * const gpio30_group[] = { "gpio30_grp" };
static const char * const gpio31_group[] = { "gpio31_grp" };
static const char * const gpio32_group[] = { "gpio32_grp" };
static const char * const gpio33_group[] = { "gpio33_grp" };
static const char * const gpio34_group[] = { "gpio34_grp" };
static const char * const gpio35_group[] = { "gpio35_grp" };
static const char * const gpio36_group[] = { "gpio36_grp" };
static const char * const gpio37_group[] = { "gpio37_grp" };
static const char * const gpio38_group[] = { "gpio38_grp" };
static const char * const gpio39_group[] = { "gpio39_grp" };
static const char * const gpio40_group[] = { "gpio40_grp" };
static const char * const gpio41_group[] = { "gpio41_grp" };
static const char * const gpio42_group[] = { "gpio42_grp" };
static const char * const gpio43_group[] = { "gpio43_grp" };
static const char * const gpio44_group[] = { "gpio44_grp" };
static const char * const gpio45_group[] = { "gpio45_grp" };
static const char * const gpio46_group[] = { "gpio46_grp" };
static const char * const gpio47_group[] = { "gpio47_grp" };
static const char * const gpio48_group[] = { "gpio48_grp" };
static const char * const gpio49_group[] = { "gpio49_grp" };
static const char * const gpio50_group[] = { "gpio50_grp" };
static const char * const gpio51_group[] = { "gpio51_grp" };
static const char * const gpio52_group[] = { "gpio52_grp" };
static const char * const gpio53_group[] = { "gpio53_grp" };
static const char * const gpio54_group[] = { "gpio54_grp" };
static const char * const gpio55_group[] = { "gpio55_grp" };
static const char * const gpio56_group[] = { "gpio56_grp" };
static const char * const gpio57_group[] = { "gpio57_grp" };
static const char * const gpio58_group[] = { "gpio58_grp" };
static const char * const gpio59_group[] = { "gpio59_grp" };
static const char * const gpio60_group[] = { "gpio60_grp" };
static const char * const gpio61_group[] = { "gpio61_grp" };
static const char * const gpio62_group[] = { "gpio62_grp" };
static const char * const gpio63_group[] = { "gpio63_grp" };
static const char * const gpio64_group[] = { "gpio64_grp" };
static const char * const gpio65_group[] = { "gpio65_grp" };
static const char * const gpio66_group[] = { "gpio66_grp" };
static const char * const gpio67_group[] = { "gpio67_grp" };
static const char * const eth1_group[] = { "eth1_grp" };
static const char * const i2s0_group[] = { "i2s0_grp" };
static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" };
static const char * const i2s1_group[] = { "i2s1_grp" };
static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" };
static const char * const spi0_group[] = { "spi0_grp" };
#define BM1880_PINMUX_FUNCTION(fname, mval, mask) \
[F_##fname] = { \
.name = #fname, \
.groups = fname##_group, \
.ngroups = ARRAY_SIZE(fname##_group), \
.mux_val = mval, \
.mux_mask = mask, \
}
#define BM1880_PINMUX_FUNCTION_MUX(fname, mval, mask, offset, shift)\
[F_##fname] = { \
.name = #fname, \
.groups = fname##_group, \
.ngroups = ARRAY_SIZE(fname##_group), \
.mux_val = mval, \
.mux_mask = mask, \
.mux = offset, \
.mux_shift = shift, \
}
static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
BM1880_PINMUX_FUNCTION(nand, 2, 0x03),
BM1880_PINMUX_FUNCTION(spi, 0, 0x03),
BM1880_PINMUX_FUNCTION(emmc, 1, 0x03),
BM1880_PINMUX_FUNCTION(sdio, 0, 0x03),
BM1880_PINMUX_FUNCTION(eth0, 0, 0x03),
BM1880_PINMUX_FUNCTION_MUX(pwm0, 2, 0x0F, 0x50, 0x00),
BM1880_PINMUX_FUNCTION_MUX(pwm1, 2, 0x0F, 0x50, 0x04),
BM1880_PINMUX_FUNCTION_MUX(pwm2, 2, 0x0F, 0x50, 0x08),
BM1880_PINMUX_FUNCTION_MUX(pwm3, 2, 0x0F, 0x50, 0x0C),
BM1880_PINMUX_FUNCTION_MUX(pwm4, 2, 0x0F, 0x50, 0x10),
BM1880_PINMUX_FUNCTION_MUX(pwm5, 2, 0x0F, 0x50, 0x14),
BM1880_PINMUX_FUNCTION_MUX(pwm6, 2, 0x0F, 0x50, 0x18),
BM1880_PINMUX_FUNCTION_MUX(pwm7, 2, 0x0F, 0x50, 0x1C),
BM1880_PINMUX_FUNCTION_MUX(pwm8, 2, 0x0F, 0x54, 0x00),
BM1880_PINMUX_FUNCTION_MUX(pwm9, 2, 0x0F, 0x54, 0x04),
BM1880_PINMUX_FUNCTION_MUX(pwm10, 2, 0x0F, 0x54, 0x08),
BM1880_PINMUX_FUNCTION_MUX(pwm11, 2, 0x0F, 0x54, 0x0C),
BM1880_PINMUX_FUNCTION_MUX(pwm12, 2, 0x0F, 0x54, 0x10),
BM1880_PINMUX_FUNCTION_MUX(pwm13, 2, 0x0F, 0x54, 0x14),
BM1880_PINMUX_FUNCTION_MUX(pwm14, 2, 0x0F, 0x54, 0x18),
BM1880_PINMUX_FUNCTION_MUX(pwm15, 2, 0x0F, 0x54, 0x1C),
BM1880_PINMUX_FUNCTION_MUX(pwm16, 2, 0x0F, 0x58, 0x00),
BM1880_PINMUX_FUNCTION_MUX(pwm17, 2, 0x0F, 0x58, 0x04),
BM1880_PINMUX_FUNCTION_MUX(pwm18, 2, 0x0F, 0x58, 0x08),
BM1880_PINMUX_FUNCTION_MUX(pwm19, 2, 0x0F, 0x58, 0x0C),
BM1880_PINMUX_FUNCTION_MUX(pwm20, 2, 0x0F, 0x58, 0x10),
BM1880_PINMUX_FUNCTION_MUX(pwm21, 2, 0x0F, 0x58, 0x14),
BM1880_PINMUX_FUNCTION_MUX(pwm22, 2, 0x0F, 0x58, 0x18),
BM1880_PINMUX_FUNCTION_MUX(pwm23, 2, 0x0F, 0x58, 0x1C),
BM1880_PINMUX_FUNCTION_MUX(pwm24, 2, 0x0F, 0x5C, 0x00),
BM1880_PINMUX_FUNCTION_MUX(pwm25, 2, 0x0F, 0x5C, 0x04),
BM1880_PINMUX_FUNCTION_MUX(pwm26, 2, 0x0F, 0x5C, 0x08),
BM1880_PINMUX_FUNCTION_MUX(pwm27, 2, 0x0F, 0x5C, 0x0C),
BM1880_PINMUX_FUNCTION_MUX(pwm28, 2, 0x0F, 0x5C, 0x10),
BM1880_PINMUX_FUNCTION_MUX(pwm29, 2, 0x0F, 0x5C, 0x14),
BM1880_PINMUX_FUNCTION_MUX(pwm30, 2, 0x0F, 0x5C, 0x18),
BM1880_PINMUX_FUNCTION_MUX(pwm31, 2, 0x0F, 0x5C, 0x1C),
BM1880_PINMUX_FUNCTION_MUX(pwm32, 2, 0x0F, 0x60, 0x00),
BM1880_PINMUX_FUNCTION_MUX(pwm33, 2, 0x0F, 0x60, 0x04),
BM1880_PINMUX_FUNCTION_MUX(pwm34, 2, 0x0F, 0x60, 0x08),
BM1880_PINMUX_FUNCTION_MUX(pwm35, 2, 0x0F, 0x60, 0x0C),
BM1880_PINMUX_FUNCTION_MUX(pwm36, 2, 0x0F, 0x60, 0x10),
BM1880_PINMUX_FUNCTION_MUX(pwm37, 2, 0x0F, 0x60, 0x1C),
BM1880_PINMUX_FUNCTION(i2c0, 1, 0x03),
BM1880_PINMUX_FUNCTION(i2c1, 1, 0x03),
BM1880_PINMUX_FUNCTION(i2c2, 1, 0x03),
BM1880_PINMUX_FUNCTION(i2c3, 1, 0x03),
BM1880_PINMUX_FUNCTION(i2c4, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart0, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart1, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart2, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart3, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart4, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart5, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart6, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart7, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart8, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart9, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart10, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart11, 1, 0x03),
BM1880_PINMUX_FUNCTION(uart12, 3, 0x03),
BM1880_PINMUX_FUNCTION(uart13, 3, 0x03),
BM1880_PINMUX_FUNCTION(uart14, 3, 0x03),
BM1880_PINMUX_FUNCTION(uart15, 3, 0x03),
BM1880_PINMUX_FUNCTION_MUX(gpio0, 0, 0x03, 0x4E0, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio1, 0, 0x03, 0x4E4, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio2, 0, 0x03, 0x4E4, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio3, 0, 0x03, 0x4E8, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio4, 0, 0x03, 0x4E8, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio5, 0, 0x03, 0x4EC, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio6, 0, 0x03, 0x4EC, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio7, 0, 0x03, 0x4F0, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio8, 0, 0x03, 0x4F0, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio9, 0, 0x03, 0x4F4, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio10, 0, 0x03, 0x4F4, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio11, 0, 0x03, 0x4F8, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio12, 1, 0x03, 0x4F8, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio13, 1, 0x03, 0x4FC, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio14, 0, 0x03, 0x474, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio15, 0, 0x03, 0x478, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio16, 0, 0x03, 0x478, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio17, 0, 0x03, 0x47C, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio18, 0, 0x03, 0x47C, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio19, 0, 0x03, 0x480, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio20, 0, 0x03, 0x480, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio21, 0, 0x03, 0x484, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio22, 0, 0x03, 0x484, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio23, 0, 0x03, 0x488, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio24, 0, 0x03, 0x488, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio25, 0, 0x03, 0x48C, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio26, 0, 0x03, 0x48C, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio27, 0, 0x03, 0x490, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio28, 0, 0x03, 0x490, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio29, 0, 0x03, 0x494, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio30, 0, 0x03, 0x494, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio31, 0, 0x03, 0x498, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio32, 0, 0x03, 0x498, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio33, 0, 0x03, 0x49C, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio34, 0, 0x03, 0x49C, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio35, 0, 0x03, 0x4A0, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio36, 0, 0x03, 0x4A0, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio37, 0, 0x03, 0x4A4, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio38, 0, 0x03, 0x4A4, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio39, 0, 0x03, 0x4A8, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio40, 0, 0x03, 0x4A8, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio41, 0, 0x03, 0x4AC, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio42, 0, 0x03, 0x4AC, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio43, 0, 0x03, 0x4B0, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio44, 0, 0x03, 0x4B0, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio45, 0, 0x03, 0x4B4, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio46, 0, 0x03, 0x4B4, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio47, 0, 0x03, 0x4B8, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio48, 0, 0x03, 0x4B8, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio49, 0, 0x03, 0x4BC, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio50, 0, 0x03, 0x4BC, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio51, 0, 0x03, 0x4C0, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio52, 0, 0x03, 0x4C0, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio53, 0, 0x03, 0x4C4, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio54, 0, 0x03, 0x4C4, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio55, 0, 0x03, 0x4C8, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio56, 0, 0x03, 0x4C8, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio57, 0, 0x03, 0x4CC, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio58, 0, 0x03, 0x4CC, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio59, 0, 0x03, 0x4D0, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio60, 0, 0x03, 0x4D0, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio61, 0, 0x03, 0x4D4, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio62, 0, 0x03, 0x4D4, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio63, 0, 0x03, 0x4D8, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio64, 0, 0x03, 0x4D8, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio65, 0, 0x03, 0x4DC, 0x04),
BM1880_PINMUX_FUNCTION_MUX(gpio66, 0, 0x03, 0x4DC, 0x14),
BM1880_PINMUX_FUNCTION_MUX(gpio67, 0, 0x03, 0x4E0, 0x04),
BM1880_PINMUX_FUNCTION(eth1, 1, 0x03),
BM1880_PINMUX_FUNCTION(i2s0, 2, 0x03),
BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1, 0x03),
BM1880_PINMUX_FUNCTION(i2s1, 2, 0x03),
BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1, 0x03),
BM1880_PINMUX_FUNCTION(spi0, 1, 0x03),
};
static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->ngroups;
}
static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->groups[selector].name;
}
static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->groups[selector].pins;
*num_pins = pctrl->groups[selector].npins;
return 0;
}
static const struct pinctrl_ops bm1880_pctrl_ops = {
.get_groups_count = bm1880_pctrl_get_groups_count,
.get_group_name = bm1880_pctrl_get_group_name,
.get_group_pins = bm1880_pctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
/* pinmux */
static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->nfuncs;
}
static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->funcs[selector].name;
}
static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->funcs[selector].groups;
*num_groups = pctrl->funcs[selector].ngroups;
return 0;
}
static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group];
const struct bm1880_pinmux_function *func = &pctrl->funcs[function];
int i;
if (func->mux) {
u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX +
func->mux);
regval &= ~(func->mux_mask << func->mux_shift);
regval |= func->mux_val << func->mux_shift;
writel_relaxed(regval, pctrl->base + BM1880_REG_MUX +
func->mux);
} else {
for (i = 0; i < pgrp->npins; i++) {
unsigned int pin = pgrp->pins[i];
u32 offset = (pin >> 1) << 2;
u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4);
u32 regval = readl_relaxed(pctrl->base +
BM1880_REG_MUX + offset);
regval &= ~(func->mux_mask << mux_offset);
regval |= func->mux_val << mux_offset;
writel_relaxed(regval, pctrl->base +
BM1880_REG_MUX + offset);
}
}
return 0;
}
static const struct pinmux_ops bm1880_pinmux_ops = {
.get_functions_count = bm1880_pmux_get_functions_count,
.get_function_name = bm1880_pmux_get_function_name,
.get_function_groups = bm1880_pmux_get_function_groups,
.set_mux = bm1880_pinmux_set_mux,
};
static struct pinctrl_desc bm1880_desc = {
.name = "bm1880_pinctrl",
.pins = bm1880_pins,
.npins = ARRAY_SIZE(bm1880_pins),
.pctlops = &bm1880_pctrl_ops,
.pmxops = &bm1880_pinmux_ops,
.owner = THIS_MODULE,
};
static int bm1880_pinctrl_probe(struct platform_device *pdev)
{
struct resource *res;
struct bm1880_pinctrl *pctrl;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pctrl->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pctrl->base))
return PTR_ERR(pctrl->base);
pctrl->groups = bm1880_pctrl_groups;
pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
pctrl->funcs = bm1880_pmux_functions;
pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
pctrl);
if (IS_ERR(pctrl->pctrldev))
return PTR_ERR(pctrl->pctrldev);
platform_set_drvdata(pdev, pctrl);
dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n");
return 0;
}
static const struct of_device_id bm1880_pinctrl_of_match[] = {
{ .compatible = "bitmain,bm1880-pinctrl" },
{ }
};
static struct platform_driver bm1880_pinctrl_driver = {
.driver = {
.name = "pinctrl-bm1880",
.of_match_table = of_match_ptr(bm1880_pinctrl_of_match),
},
.probe = bm1880_pinctrl_probe,
};
static int __init bm1880_pinctrl_init(void)
{
return platform_driver_register(&bm1880_pinctrl_driver);
}
arch_initcall(bm1880_pinctrl_init);

3
drivers/pinctrl/pinctrl-mcp23s08.c
View File

@ -266,7 +266,6 @@ static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
status = (data & BIT(pin)) ? 1 : 0;
break;
default:
dev_err(mcp->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
@ -293,7 +292,7 @@ static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
break;
default:
dev_err(mcp->dev, "Invalid config param %04x\n", param);
dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
}
}

2
drivers/pinctrl/pinctrl-pistachio.c
View File

@ -1367,6 +1367,7 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
if (!of_find_property(child, "gpio-controller", NULL)) {
dev_err(pctl->dev,
"No gpio-controller property for bank %u\n", i);
of_node_put(child);
ret = -ENODEV;
goto err;
}
@ -1374,6 +1375,7 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
irq = irq_of_parse_and_map(child, 0);
if (irq < 0) {
dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);
of_node_put(child);
ret = irq;
goto err;
}

18
drivers/pinctrl/pinctrl-rza1.c
View File

@ -620,14 +620,7 @@ static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
static inline int rza1_pin_get_direction(struct rza1_port *port,
unsigned int pin)
{
unsigned long irqflags;
int input;
spin_lock_irqsave(&port->lock, irqflags);
input = rza1_get_bit(port, RZA1_PM_REG, pin);
spin_unlock_irqrestore(&port->lock, irqflags);
return !!input;
return !!rza1_get_bit(port, RZA1_PM_REG, pin);
}
/**
@ -671,14 +664,7 @@ static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
{
unsigned long irqflags;
int val;
spin_lock_irqsave(&port->lock, irqflags);
val = rza1_get_bit(port, RZA1_PPR_REG, pin);
spin_unlock_irqrestore(&port->lock, irqflags);
return val;
return rza1_get_bit(port, RZA1_PPR_REG, pin);
}
/**

15
drivers/pinctrl/pinctrl-st.c
View File

@ -1170,7 +1170,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
struct property *pp;
struct st_pinconf *conf;
struct device_node *pins;
int i = 0, npins = 0, nr_props;
int i = 0, npins = 0, nr_props, ret = 0;
pins = of_get_child_by_name(np, "st,pins");
if (!pins)
@ -1185,7 +1185,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
npins++;
} else {
pr_warn("Invalid st,pins in %pOFn node\n", np);
return -EINVAL;
ret = -EINVAL;
goto out_put_node;
}
}
@ -1195,8 +1196,10 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
grp->pin_conf = devm_kcalloc(info->dev,
npins, sizeof(*conf), GFP_KERNEL);
if (!grp->pins || !grp->pin_conf)
return -ENOMEM;
if (!grp->pins || !grp->pin_conf) {
ret = -ENOMEM;
goto out_put_node;
}
/* <bank offset mux direction rt_type rt_delay rt_clk> */
for_each_property_of_node(pins, pp) {
@ -1229,9 +1232,11 @@ static int st_pctl_dt_parse_groups(struct device_node *np,
}
i++;
}
out_put_node:
of_node_put(pins);
return 0;
return ret;
}
static int st_pctl_parse_functions(struct device_node *np,

1
drivers/pinctrl/samsung/pinctrl-exynos-arm.c
View File

@ -71,6 +71,7 @@ s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
}
clk_base = of_iomap(np, 0);
of_node_put(np);
if (!clk_base) {
pr_err("%s: failed to map clock registers\n", __func__);
return ERR_PTR(-EINVAL);

204
drivers/pinctrl/sh-pfc/Kconfig
View File

@ -3,201 +3,183 @@
# Renesas SH and SH Mobile PINCTRL drivers
#
if ARCH_RENESAS || SUPERH
config PINCTRL_SH_PFC
bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
default y if ARCH_RENESAS || SUPERH
select PINMUX
select PINCONF
select GENERIC_PINCONF
def_bool y
select PINCTRL_PFC_EMEV2 if ARCH_EMEV2
select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4
select PINCTRL_PFC_R8A7740 if ARCH_R8A7740
select PINCTRL_PFC_R8A7743 if ARCH_R8A7743
select PINCTRL_PFC_R8A7744 if ARCH_R8A7744
select PINCTRL_PFC_R8A7745 if ARCH_R8A7745
select PINCTRL_PFC_R8A77470 if ARCH_R8A77470
select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1
select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0
select PINCTRL_PFC_R8A7778 if ARCH_R8A7778
select PINCTRL_PFC_R8A7779 if ARCH_R8A7779
select PINCTRL_PFC_R8A7790 if ARCH_R8A7790
select PINCTRL_PFC_R8A7791 if ARCH_R8A7791
select PINCTRL_PFC_R8A7792 if ARCH_R8A7792
select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
select PINCTRL_PFC_R8A7796 if ARCH_R8A7796
select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
select PINCTRL_PFC_SH73A0 if ARCH_SH73A0
select PINCTRL_PFC_SH7720 if CPU_SUBTYPE_SH7720
select PINCTRL_PFC_SH7722 if CPU_SUBTYPE_SH7722
select PINCTRL_PFC_SH7723 if CPU_SUBTYPE_SH7723
select PINCTRL_PFC_SH7724 if CPU_SUBTYPE_SH7724
select PINCTRL_PFC_SH7734 if CPU_SUBTYPE_SH7734
select PINCTRL_PFC_SH7757 if CPU_SUBTYPE_SH7757
select PINCTRL_PFC_SH7785 if CPU_SUBTYPE_SH7785
select PINCTRL_PFC_SH7786 if CPU_SUBTYPE_SH7786
select PINCTRL_PFC_SHX3 if CPU_SUBTYPE_SHX3
help
This enables pin control drivers for SH and SH Mobile platforms
This enables pin control drivers for Renesas SuperH and ARM platforms
config PINCTRL_SH_PFC_GPIO
select GPIOLIB
select PINCTRL_SH_PFC
bool
help
This enables pin control and GPIO drivers for SH/SH Mobile platforms
config PINCTRL_SH_FUNC_GPIO
select PINCTRL_SH_PFC_GPIO
bool
help
This enables legacy function GPIOs for SH platforms
config PINCTRL_PFC_EMEV2
def_bool y
depends on ARCH_EMEV2
select PINCTRL_SH_PFC
bool "Emma Mobile AV2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A73A4
def_bool y
depends on ARCH_R8A73A4
bool "R-Mobile APE6 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7740
def_bool y
depends on ARCH_R8A7740
bool "R-Mobile A1 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7743
def_bool y
depends on ARCH_R8A7743
select PINCTRL_SH_PFC
bool "RZ/G1M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7744
def_bool y
depends on ARCH_R8A7744
select PINCTRL_SH_PFC
bool "RZ/G1N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7745
def_bool y
depends on ARCH_R8A7745
select PINCTRL_SH_PFC
bool "RZ/G1E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77470
def_bool y
depends on ARCH_R8A77470
select PINCTRL_SH_PFC
bool "RZ/G1C pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774A1
def_bool y
depends on ARCH_R8A774A1
select PINCTRL_SH_PFC
bool "RZ/G2M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774C0
def_bool y
depends on ARCH_R8A774C0
select PINCTRL_SH_PFC
bool "RZ/G2E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7778
def_bool y
depends on ARCH_R8A7778
select PINCTRL_SH_PFC
bool "R-Car M1A pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7779
def_bool y
depends on ARCH_R8A7779
select PINCTRL_SH_PFC
bool "R-Car H1 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7790
def_bool y
depends on ARCH_R8A7790
select PINCTRL_SH_PFC
bool "R-Car H2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7791
def_bool y
depends on ARCH_R8A7791
select PINCTRL_SH_PFC
bool "R-Car M2-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7792
def_bool y
depends on ARCH_R8A7792
select PINCTRL_SH_PFC
bool "R-Car V2H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7793
def_bool y
depends on ARCH_R8A7793
select PINCTRL_SH_PFC
bool "R-Car M2-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7794
def_bool y
depends on ARCH_R8A7794
select PINCTRL_SH_PFC
bool "R-Car E2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7795
def_bool y
depends on ARCH_R8A7795
select PINCTRL_SH_PFC
bool "R-Car H3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7796
def_bool y
depends on ARCH_R8A7796
select PINCTRL_SH_PFC
bool "R-Car M3-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77965
def_bool y
depends on ARCH_R8A77965
select PINCTRL_SH_PFC
bool "R-Car M3-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77970
def_bool y
depends on ARCH_R8A77970
select PINCTRL_SH_PFC
bool "R-Car V3M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77980
def_bool y
depends on ARCH_R8A77980
select PINCTRL_SH_PFC
bool "R-Car V3H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77990
def_bool y
depends on ARCH_R8A77990
select PINCTRL_SH_PFC
bool "R-Car E3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77995
def_bool y
depends on ARCH_R8A77995
select PINCTRL_SH_PFC
bool "R-Car D3 pin control support" if COMPILE_TEST
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203
select PINCTRL_SH_PFC_GPIO
bool "SH7203 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7264
def_bool y
depends on CPU_SUBTYPE_SH7264
select PINCTRL_SH_PFC_GPIO
bool "SH7264 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7269
def_bool y
depends on CPU_SUBTYPE_SH7269
select PINCTRL_SH_PFC_GPIO
bool "SH7269 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH73A0
def_bool y
depends on ARCH_SH73A0
bool "SH-Mobile AG5 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7720
def_bool y
depends on CPU_SUBTYPE_SH7720
select PINCTRL_SH_PFC_GPIO
bool "SH7720 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7722
def_bool y
depends on CPU_SUBTYPE_SH7722
select PINCTRL_SH_PFC_GPIO
bool "SH7722 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7723
def_bool y
depends on CPU_SUBTYPE_SH7723
select PINCTRL_SH_PFC_GPIO
bool "SH-Mobile R2 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7724
def_bool y
depends on CPU_SUBTYPE_SH7724
select PINCTRL_SH_PFC_GPIO
bool "SH-Mobile R2R pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7734
def_bool y
depends on CPU_SUBTYPE_SH7734
select PINCTRL_SH_PFC_GPIO
bool "SH7734 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7757
def_bool y
depends on CPU_SUBTYPE_SH7757
select PINCTRL_SH_PFC_GPIO
bool "SH7757 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7785
def_bool y
depends on CPU_SUBTYPE_SH7785
select PINCTRL_SH_PFC_GPIO
bool "SH7785 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7786
def_bool y
depends on CPU_SUBTYPE_SH7786
select PINCTRL_SH_PFC_GPIO
bool "SH7786 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SHX3
def_bool y
depends on CPU_SUBTYPE_SHX3
select PINCTRL_SH_PFC_GPIO
endif
bool "SH-X3 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO

15
drivers/pinctrl/sh-pfc/Makefile
View File

@ -38,3 +38,18 @@ obj-$(CONFIG_PINCTRL_PFC_SH7757) += pfc-sh7757.o
obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o
obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o
obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
ifeq ($(CONFIG_COMPILE_TEST),y)
CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7269.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7720.o += -I$(srctree)/arch/sh/include/cpu-sh3
CFLAGS_pfc-sh7722.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7723.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7724.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7734.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7757.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7785.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-sh7786.o += -I$(srctree)/arch/sh/include/cpu-sh4
CFLAGS_pfc-shx3.o += -I$(srctree)/arch/sh/include/cpu-sh4
endif

130
drivers/pinctrl/sh-pfc/core.c
View File

@ -571,6 +571,13 @@ static const struct of_device_id sh_pfc_of_table[] = {
.compatible = "renesas,pfc-r8a7795",
.data = &r8a7795_pinmux_info,
},
#ifdef DEBUG
{
/* For sanity checks only (nothing matches against this) */
.compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */
.data = &r8a7795es1_pinmux_info,
},
#endif /* DEBUG */
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7796
{
@ -709,6 +716,128 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
#define DEV_PM_OPS NULL
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
#ifdef DEBUG
static bool is0s(const u16 *enum_ids, unsigned int n)
{
unsigned int i;
for (i = 0; i < n; i++)
if (enum_ids[i])
return false;
return true;
}
static unsigned int sh_pfc_errors;
static unsigned int sh_pfc_warnings;
static void sh_pfc_check_cfg_reg(const char *drvname,
const struct pinmux_cfg_reg *cfg_reg)
{
unsigned int i, n, rw, fw;
if (cfg_reg->field_width) {
/* Checked at build time */
return;
}
for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
drvname, cfg_reg->reg, rw, rw + fw - 1);
sh_pfc_warnings++;
}
n += 1 << fw;
rw += fw;
}
if (rw != cfg_reg->reg_width) {
pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
sh_pfc_errors++;
}
if (n != cfg_reg->nr_enum_ids) {
pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
sh_pfc_errors++;
}
}
static void sh_pfc_check_info(const struct sh_pfc_soc_info *info)
{
const struct sh_pfc_function *func;
const char *drvname = info->name;
unsigned int *refcnts;
unsigned int i, j, k;
pr_info("Checking %s\n", drvname);
/* Check groups and functions */
refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
if (!refcnts)
return;
for (i = 0; i < info->nr_functions; i++) {
func = &info->functions[i];
for (j = 0; j < func->nr_groups; j++) {
for (k = 0; k < info->nr_groups; k++) {
if (!strcmp(func->groups[j],
info->groups[k].name)) {
refcnts[k]++;
break;
}
}
if (k == info->nr_groups) {
pr_err("%s: function %s: group %s not found\n",
drvname, func->name, func->groups[j]);
sh_pfc_errors++;
}
}
}
for (i = 0; i < info->nr_groups; i++) {
if (!refcnts[i]) {
pr_err("%s: orphan group %s\n", drvname,
info->groups[i].name);
sh_pfc_errors++;
} else if (refcnts[i] > 1) {
pr_err("%s: group %s referred by %u functions\n",
drvname, info->groups[i].name, refcnts[i]);
sh_pfc_warnings++;
}
}
kfree(refcnts);
/* Check config register descriptions */
for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
}
static void sh_pfc_check_driver(const struct platform_driver *pdrv)
{
unsigned int i;
pr_warn("Checking builtin pinmux tables\n");
for (i = 0; pdrv->id_table[i].name[0]; i++)
sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
#ifdef CONFIG_OF
for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
#endif
pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
sh_pfc_warnings);
}
#else /* !DEBUG */
static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
#endif /* !DEBUG */
static int sh_pfc_probe(struct platform_device *pdev)
{
#ifdef CONFIG_OF
@ -840,6 +969,7 @@ static struct platform_driver sh_pfc_driver = {
static int __init sh_pfc_init(void)
{
sh_pfc_check_driver(&sh_pfc_driver);
return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);

8
drivers/pinctrl/sh-pfc/gpio.c
View File

@ -252,7 +252,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
* Function GPIOs
*/
#ifdef CONFIG_SUPERH
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
static bool __print_once;
@ -292,7 +292,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
return 0;
}
#endif
#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
/* -----------------------------------------------------------------------------
* Register/unregister
@ -369,7 +369,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
return 0;
#ifdef CONFIG_SUPERH
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
/*
* Register the GPIO to pin mappings. As pins with GPIO ports
* must come first in the ranges, skip the pins without GPIO
@ -397,7 +397,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
if (IS_ERR(chip))
return PTR_ERR(chip);
#endif /* CONFIG_SUPERH */
#endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
return 0;
}

67
drivers/pinctrl/sh-pfc/pfc-emev2.c
View File

@ -1433,7 +1433,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(
0, PORT31_FN, /* PIN: J18 */
0, PORT30_FN, /* PIN: H18 */
0, PORT29_FN, /* PIN: G18 */
@ -1466,9 +1466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_JT_SEL, PORT2_FN, /* PIN: V9 */
0, PORT1_FN, /* PIN: U10 */
0, PORT0_FN, /* PIN: V10 */
}
))
},
{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(
FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */
FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */
FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */
@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCD3_R2, PORT34_FN, /* PIN: A19 */
FN_LCD3_R1, PORT33_FN, /* PIN: B20 */
FN_LCD3_R0, PORT32_FN, /* PIN: A20 */
}
))
},
{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(
FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */
FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */
FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */
@ -1536,9 +1536,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */
FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */
FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */
}
))
},
{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(
FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */
FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */
FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */
@ -1571,9 +1571,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */
FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */
FN_AB_A20, PORT96_FN, /* PIN: M21 */
}
))
},
{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(
0, 0,
FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */
FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */
@ -1606,11 +1606,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */
FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */
FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 2, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
2, 2),
GROUP(
/* 31 - 12 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1624,11 +1626,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1636,11 +1640,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1648,11 +1654,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* 31 - 14 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1673,11 +1680,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
/* 1 - 0 */
FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
2, 2, 2),
GROUP(
/* 31 - 10 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1692,11 +1701,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
/* 1 - 0 */
FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 2),
GROUP(
/* 31 - 2 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1704,7 +1715,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 1 - 0 */
FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
}
))
},
{ },
};

64
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View File

@ -2284,7 +2284,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(328, 0xe6053148),
PORTCR(329, 0xe6053149),
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
MSEL1CR_31_0, MSEL1CR_31_1,
0, 0,
0, 0,
@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL1CR_02_0, MSEL1CR_02_1,
MSEL1CR_01_0, MSEL1CR_01_1,
MSEL1CR_00_0, MSEL1CR_00_1,
}
))
},
{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
MSEL3CR_31_0, MSEL3CR_31_1,
0, 0,
0, 0,
@ -2352,9 +2352,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MSEL3CR_01_0, MSEL3CR_01_1,
MSEL3CR_00_0, MSEL3CR_00_1,
}
))
},
{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
0, 0,
MSEL4CR_30_0, MSEL4CR_30_1,
MSEL4CR_29_0, MSEL4CR_29_1,
@ -2387,9 +2387,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MSEL4CR_01_0, MSEL4CR_01_1,
0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
MSEL5CR_31_0, MSEL5CR_31_1,
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
@ -2422,9 +2422,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2457,14 +2457,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MSEL8CR_01_0, MSEL8CR_01_1,
MSEL8CR_00_0, MSEL8CR_00_1,
}
))
},
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
@ -2473,9 +2473,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -2484,9 +2484,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, PORT85_DATA, PORT84_DATA,
@ -2495,9 +2495,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
@ -2506,9 +2506,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -2517,9 +2517,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -2528,9 +2528,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
@ -2539,9 +2539,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
0, 0, 0, 0,
0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
@ -2550,9 +2550,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
0, 0, 0, 0,
PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
@ -2561,9 +2561,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, PORT308_DATA,
@ -2572,9 +2572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
}
))
},
{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -2583,7 +2583,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, PORT329_DATA, PORT328_DATA,
PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
}
))
},
{ },
};

56
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -3436,7 +3436,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(210, 0xe60530d2), /* PORT210CR */
PORTCR(211, 0xe60530d3), /* PORT211CR */
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
MSEL1CR_31_0, MSEL1CR_31_1,
MSEL1CR_30_0, MSEL1CR_30_1,
MSEL1CR_29_0, MSEL1CR_29_1,
@ -3461,9 +3461,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL1CR_2_0, MSEL1CR_2_1,
0, 0,
MSEL1CR_0_0, MSEL1CR_0_1,
}
))
},
{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -3474,9 +3474,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL3CR_6_0, MSEL3CR_6_1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -3493,9 +3493,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
MSEL4CR_1_0, MSEL4CR_1_1,
0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
MSEL5CR_31_0, MSEL5CR_31_1,
MSEL5CR_30_0, MSEL5CR_30_1,
MSEL5CR_29_0, MSEL5CR_29_1,
@ -3528,13 +3528,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL5CR_2_0, MSEL5CR_2_1,
0, 0,
MSEL5CR_0_0, MSEL5CR_0_1,
}
))
},
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
@ -3542,9 +3542,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
},
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
@ -3552,9 +3552,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
},
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -3562,9 +3562,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
},
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
@ -3572,9 +3572,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -3582,9 +3582,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
},
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
@ -3592,9 +3592,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
@ -3602,9 +3602,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
@ -3612,9 +3612,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -3622,9 +3622,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
},
{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -3632,7 +3632,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ },
};

136
drivers/pinctrl/sh-pfc/pfc-r8a77470.c
View File

@ -5,6 +5,7 @@
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
@ -2540,7 +2541,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2572,9 +2573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_USB1_OVC,
GP_0_2_FN, FN_USB1_PWEN,
GP_0_1_FN, FN_USB0_OVC,
GP_0_0_FN, FN_USB0_PWEN, }
GP_0_0_FN, FN_USB0_PWEN, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2606,9 +2607,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP1_23_20,
GP_1_2_FN, FN_IP1_19_16,
GP_1_1_FN, FN_IP1_15_12,
GP_1_0_FN, FN_IP1_11_8, }
GP_1_0_FN, FN_IP1_11_8, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP8_3_0,
GP_2_30_FN, FN_IP7_31_28,
GP_2_29_FN, FN_IP7_27_24,
@ -2640,9 +2641,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP4_19_16,
GP_2_2_FN, FN_IP4_15_12,
GP_2_1_FN, FN_IP4_11_8,
GP_2_0_FN, FN_IP4_7_4, }
GP_2_0_FN, FN_IP4_7_4, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
0, 0,
0, 0,
GP_3_29_FN, FN_IP10_19_16,
@ -2674,9 +2675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP8_19_16,
GP_3_2_FN, FN_IP8_15_12,
GP_3_1_FN, FN_IP8_11_8,
GP_3_0_FN, FN_IP8_7_4, }
GP_3_0_FN, FN_IP8_7_4, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2708,9 +2709,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP11_3_0,
GP_4_2_FN, FN_IP10_31_28,
GP_4_1_FN, FN_IP10_27_24,
GP_4_0_FN, FN_IP10_23_20, }
GP_4_0_FN, FN_IP10_23_20, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP17_27_24,
GP_5_30_FN, FN_IP17_23_20,
GP_5_29_FN, FN_IP17_19_16,
@ -2742,10 +2743,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_IP14_11_8,
GP_5_2_FN, FN_IP14_7_4,
GP_5_1_FN, FN_IP14_3_0,
GP_5_0_FN, FN_IP13_31_28, }
GP_5_0_FN, FN_IP13_31_28, ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP0_31_28 [4] */
FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2769,10 +2771,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_3_0 [4] */
FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP1_31_28 [4] */
FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2796,10 +2799,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_3_0 [4] */
FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP2_31_28 [4] */
FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@ -2823,10 +2827,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_3_0 [4] */
FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP3_31_28 [4] */
FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
@ -2851,10 +2856,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP3_3_0 [4] */
FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
0, FN_AVB_AVTP_CAPTURE_A,
0, 0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP4_31_28 [4] */
FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2878,10 +2884,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_3_0 [4] */
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP5_31_28 [4] */
FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@ -2905,10 +2912,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_3_0 [4] */
FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP6_31_28 [4] */
FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
0, 0, 0, 0, 0, 0, 0,
@ -2932,10 +2940,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_3_0 [4] */
FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
0, 0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP7_31_28 [4] */
FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@ -2959,10 +2968,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0,
/* IP7_3_0 [4] */
FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP8_31_28 [4] */
FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@ -2986,10 +2996,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0,
/* IP8_3_0 [4] */
FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP9_31_28 [4] */
FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@ -3013,10 +3024,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0,
/* IP9_3_0 [4] */
FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP10_31_28 [4] */
FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3041,10 +3053,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0,
/* IP10_3_0 [4] */
FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP11_31_28 [4] */
FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3072,10 +3085,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_3_0 [4] */
FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, }
FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP12_31_28 [4] */
FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3099,10 +3113,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP12_3_0 [4] */
FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP13_31_28 [4] */
FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
@ -3127,10 +3142,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_3_0 [4] */
FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP14_31_28 [4] */
FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3154,10 +3170,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP14_3_0 [4] */
FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP15_31_28 [4] */
FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@ -3181,10 +3198,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP15_3_0 [4] */
FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, }
FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP16_31_28 [4] */
FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -3209,10 +3227,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP16_3_0 [4] */
FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
4, 4, 4, 4, 4, 4, 4, 4) {
GROUP(4, 4, 4, 4, 4, 4, 4, 4),
GROUP(
/* IP17_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_27_24 [4] */
@ -3235,11 +3254,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_3_0 [4] */
FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, }
FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3,
1, 2, 3, 3, 1) {
GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
3, 3, 1, 2, 3, 3, 1),
GROUP(
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
@ -3282,11 +3302,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
FN_SEL_I2C00_4, 0, 0, 0,
/* SEL_AVB [1] */
FN_SEL_AVB_0, FN_SEL_AVB_1, }
FN_SEL_AVB_0, FN_SEL_AVB_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
1, 3, 3, 2, 2, 1, 2, 2,
2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) {
GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
1, 1, 2, 1, 1, 2, 2, 1),
GROUP(
/* SEL_SCIFCLK [1] */
FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
/* SEL_SCIF5 [3] */
@ -3328,11 +3349,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_HSCIF1 [2] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
/* SEL_HSCIF0 [1] */
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,}
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
@ -3374,7 +3396,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SSI1 [2] */
FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
/* SEL_SSI0 [2] */
FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, }
FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
},
{ },
};

101
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View File

@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
GP_0_31_FN, FN_IP1_14_11,
GP_0_30_FN, FN_IP1_10_8,
GP_0_29_FN, FN_IP1_7_5,
@ -2136,9 +2136,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP0_4_2,
GP_0_2_FN, FN_PENC1,
GP_0_1_FN, FN_PENC0,
GP_0_0_FN, FN_IP0_1_0 }
GP_0_0_FN, FN_IP0_1_0 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
GP_1_31_FN, FN_IP4_6_4,
GP_1_30_FN, FN_IP4_3_1,
GP_1_29_FN, FN_IP4_0,
@ -2170,9 +2170,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP1_27_25,
GP_1_2_FN, FN_IP1_24,
GP_1_1_FN, FN_WE0,
GP_1_0_FN, FN_IP1_23_21 }
GP_1_0_FN, FN_IP1_23_21 ))
},
{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7,
GP_2_30_FN, FN_IP6_6_5,
GP_2_29_FN, FN_IP6_4_2,
@ -2204,9 +2204,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP4_12_11,
GP_2_2_FN, FN_IP4_10_9,
GP_2_1_FN, FN_IP4_8,
GP_2_0_FN, FN_IP4_7 }
GP_2_0_FN, FN_IP4_7 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
GP_3_31_FN, FN_IP8_10_9,
GP_3_30_FN, FN_IP8_8_6,
GP_3_29_FN, FN_IP8_5_3,
@ -2238,9 +2238,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP6_10,
GP_3_2_FN, FN_SSI_SCK34,
GP_3_1_FN, FN_IP6_9,
GP_3_0_FN, FN_IP6_8 }
GP_3_0_FN, FN_IP6_8 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2272,12 +2272,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP8_21_19,
GP_4_2_FN, FN_IP8_18_16,
GP_4_1_FN, FN_IP8_15_14,
GP_4_0_FN, FN_IP8_13_11 }
GP_4_0_FN, FN_IP8_13_11 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30 [1] */
@ -2328,10 +2329,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TX2_E, FN_SDA2_B, 0, 0,
/* IP0_1_0 [2] */
FN_PRESETOUT, 0, FN_PWM1, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
3, 1, 1),
GROUP(
/* IP1_31 [1] */
0, 0,
/* IP1_30 [1] */
@ -2371,11 +2374,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A21, FN_HSPI_CLK1_B,
/* IP1_0 [1] */
FN_A20, FN_HSPI_CS1_B,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 3, 2, 3, 3, 3, 3),
GROUP(
/* IP2_31 [1] */
FN_MLB_CLK, FN_IRQ1_A,
/* IP2_30 [1] */
@ -2423,11 +2427,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP2_2_0 [3] */
FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
FN_EX_CS2, 0, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
1, 1, 1, 1, 1, 3, 3, 2,
3, 3, 3, 2, 3, 3, 2) {
GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
3, 3, 2),
GROUP(
/* IP3_31 [1] */
FN_DU0_DR6, FN_LCDOUT6,
/* IP3_30 [1] */
@ -2465,10 +2470,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SDSELF_B, 0, 0, 0,
/* IP3_1_0 [2] */
FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
3, 3, 1),
GROUP(
/* IP4_31 [1] */
0, 0,
/* IP4_30_29 [2] */
@ -2507,10 +2514,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
/* IP4_0 [1] */
FN_DU0_DR7, FN_LCDOUT7,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
1, 2, 2, 2),
GROUP(
/* IP5_31 [1] */
0, 0,
@ -2551,11 +2560,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
/* IP5_1_0 [2] */
FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
1, 2, 1, 1, 1, 1, 2, 3, 2) {
GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
1, 1, 1, 1, 2, 3, 2),
GROUP(
/* IP6_31_30 [2] */
FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
/* IP6_29_28 [2] */
@ -2602,10 +2612,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP6_1_0 [2] */
FN_SSI_SCK6, FN_HSPI_RX2_A,
FN_FMCLK_B, FN_CAN1_TX_B,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
GROUP(
/* IP7_31_29 [3] */
FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
@ -2641,10 +2652,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SD0_CD, 0, FN_TX5_A, 0,
/* IP7_1_0 [2] */
FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30 [1] */
@ -2681,10 +2693,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP8_2_0 [3] */
FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
0, FN_HSPI_TX1_A, FN_TX3_B, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP9_31 [1] */
0, 0,
/* IP9_30 [1] */
@ -2723,10 +2736,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP9_2_0 [3] */
FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
0, FN_HRTS1_B, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
3, 3, 3),
GROUP(
/* IP10_31 [1] */
0, 0,
@ -2772,11 +2787,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ATARD1, FN_ETH_MDC,
FN_SDA1_B, 0,
0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* SEL 31 [1] */
0, 0,
@ -2835,11 +2851,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
/* SEL_0 (WAIT1) [1] */
FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
}
))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
GROUP(
/* SEL_31 [1] */
0, 0,
@ -2899,7 +2916,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C2_C, 0,
/* SEL_0 (I2C1) [1] */
FN_SEL_I2C1_A, FN_SEL_I2C1_B,
}
))
},
{ },
};

235
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View File

@ -1595,6 +1595,92 @@ static const unsigned int ether_magic_pins[] = {
static const unsigned int ether_magic_mux[] = {
ETH_MAGIC_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21)
};
static const unsigned int hscif0_data_mux[] = {
HTX0_MARK, HRX0_MARK
};
static const unsigned int hscif0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13)
};
static const unsigned int hscif0_data_b_mux[] = {
HTX0_B_MARK, HRX0_B_MARK
};
static const unsigned int hscif0_ctrl_pins[] = {
/* CTS, RTS */
RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19)
};
static const unsigned int hscif0_ctrl_mux[] = {
HCTS0_MARK, HRTS0_MARK
};
static const unsigned int hscif0_ctrl_b_pins[] = {
/* CTS, RTS */
RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10)
};
static const unsigned int hscif0_ctrl_b_mux[] = {
HCTS0_B_MARK, HRTS0_B_MARK
};
static const unsigned int hscif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(4, 17)
};
static const unsigned int hscif0_clk_mux[] = {
HSCK0_MARK
};
static const unsigned int hscif0_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(3, 11)
};
static const unsigned int hscif0_clk_b_mux[] = {
HSCK0_B_MARK
};
/* - HSCIF1 ----------------------------------------------------------------- */
static const unsigned int hscif1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20)
};
static const unsigned int hscif1_data_mux[] = {
HTX1_MARK, HRX1_MARK
};
static const unsigned int hscif1_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3)
};
static const unsigned int hscif1_data_b_mux[] = {
HTX1_B_MARK, HRX1_B_MARK
};
static const unsigned int hscif1_ctrl_pins[] = {
/* CTS, RTS */
RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22)
};
static const unsigned int hscif1_ctrl_mux[] = {
HCTS1_MARK, HRTS1_MARK
};
static const unsigned int hscif1_ctrl_b_pins[] = {
/* CTS, RTS */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6)
};
static const unsigned int hscif1_ctrl_b_mux[] = {
HCTS1_B_MARK, HRTS1_B_MARK
};
static const unsigned int hscif1_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(0, 18)
};
static const unsigned int hscif1_clk_mux[] = {
HSCK1_MARK
};
static const unsigned int hscif1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(2, 4)
};
static const unsigned int hscif1_clk_b_mux[] = {
HSCK1_B_MARK
};
/* - HSPI0 ------------------------------------------------------------------ */
static const unsigned int hspi0_pins[] = {
/* CLK, CS, RX, TX */
@ -2618,6 +2704,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ether_rmii),
SH_PFC_PIN_GROUP(ether_link),
SH_PFC_PIN_GROUP(ether_magic),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_data_b),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(hscif0_ctrl_b),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_clk_b),
SH_PFC_PIN_GROUP(hscif1_data),
SH_PFC_PIN_GROUP(hscif1_data_b),
SH_PFC_PIN_GROUP(hscif1_ctrl),
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
SH_PFC_PIN_GROUP(hscif1_clk),
SH_PFC_PIN_GROUP(hscif1_clk_b),
SH_PFC_PIN_GROUP(hspi0),
SH_PFC_PIN_GROUP(hspi1),
SH_PFC_PIN_GROUP(hspi1_b),
@ -2783,6 +2881,24 @@ static const char * const ether_groups[] = {
"ether_magic",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_data_b",
"hscif0_ctrl",
"hscif0_ctrl_b",
"hscif0_clk",
"hscif0_clk_b",
};
static const char * const hscif1_groups[] = {
"hscif1_data",
"hscif1_data_b",
"hscif1_ctrl",
"hscif1_ctrl_b",
"hscif1_clk",
"hscif1_clk_b",
};
static const char * const hspi0_groups[] = {
"hspi0",
};
@ -3005,6 +3121,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(ether),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hspi0),
SH_PFC_FUNCTION(hspi1),
SH_PFC_FUNCTION(hspi2),
@ -3036,7 +3154,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
GP_0_31_FN, FN_IP3_31_29,
GP_0_30_FN, FN_IP3_26_24,
GP_0_29_FN, FN_IP3_22_21,
@ -3068,9 +3186,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_A17,
GP_0_2_FN, FN_IP0_7_6,
GP_0_1_FN, FN_AVS2,
GP_0_0_FN, FN_AVS1 }
GP_0_0_FN, FN_AVS1 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
GP_1_31_FN, FN_IP5_23_21,
GP_1_30_FN, FN_IP5_20_17,
GP_1_29_FN, FN_IP5_16_15,
@ -3102,9 +3220,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP4_10_8,
GP_1_2_FN, FN_IP4_7_5,
GP_1_1_FN, FN_IP4_4_2,
GP_1_0_FN, FN_IP4_1_0 }
GP_1_0_FN, FN_IP4_1_0 ))
},
{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
GP_2_31_FN, FN_IP10_28_26,
GP_2_30_FN, FN_IP10_25_24,
GP_2_29_FN, FN_IP10_23_21,
@ -3136,9 +3254,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP8_24_23,
GP_2_2_FN, FN_IP8_22_21,
GP_2_1_FN, FN_IP8_20,
GP_2_0_FN, FN_IP5_27_24 }
GP_2_0_FN, FN_IP5_27_24 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
GP_3_31_FN, FN_IP6_3_2,
GP_3_30_FN, FN_IP6_1_0,
GP_3_29_FN, FN_IP5_30_29,
@ -3170,9 +3288,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP11_8_6,
GP_3_2_FN, FN_IP11_5_3,
GP_3_1_FN, FN_IP11_2_0,
GP_3_0_FN, FN_IP10_31_29 }
GP_3_0_FN, FN_IP10_31_29 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
GP_4_31_FN, FN_IP8_19,
GP_4_30_FN, FN_IP8_18,
GP_4_29_FN, FN_IP8_17_16,
@ -3204,9 +3322,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP6_11_9,
GP_4_2_FN, FN_IP6_8,
GP_4_1_FN, FN_IP6_7_6,
GP_4_0_FN, FN_IP6_5_4 }
GP_4_0_FN, FN_IP6_5_4 ))
},
{ PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1, GROUP(
GP_5_31_FN, FN_IP3_5,
GP_5_30_FN, FN_IP3_4,
GP_5_29_FN, FN_IP3_3,
@ -3238,9 +3356,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_A4,
GP_5_2_FN, FN_A3,
GP_5_1_FN, FN_A2,
GP_5_0_FN, FN_A1 }
GP_5_0_FN, FN_A1 ))
},
{ PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -3255,11 +3373,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, FN_IP3_15,
GP_6_2_FN, FN_IP3_8,
GP_6_1_FN, FN_IP3_7,
GP_6_0_FN, FN_IP3_6 }
GP_6_0_FN, FN_IP3_6 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
GROUP(1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30_28 [3] */
@ -3294,10 +3413,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
/* IP0_2_0 [3] */
FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
FN_SCIF_CLK, FN_TCLK0_C, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
GROUP(3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
GROUP(
/* IP1_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_28_25 [4] */
@ -3332,10 +3452,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP1_3_2 [2] */
FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
/* IP1_1_0 [2] */
FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
GROUP(1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
GROUP(
/* IP2_31 [1] */
0, 0,
/* IP2_30_28 [3] */
@ -3378,11 +3499,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
GROUP(3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1,
3, 3, 1, 1, 1, 1, 1, 1, 3),
GROUP(
/* IP3_31_29 [3] */
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
FN_SCL2_C, FN_REMOCON, 0, 0,
@ -3429,11 +3551,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DG2, FN_LCDOUT10,
/* IP3_2_0 [3] */
FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
FN_AUDATA3, 0, 0, 0 }
FN_AUDATA3, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3, 1, 1, 1, 1, 1, 1, 3, 3,
1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
GROUP(3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
1, 1, 1, 3, 3, 3, 2),
GROUP(
/* IP4_31_29 [3] */
FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
FN_TX5, FN_SCK0_D, 0, 0,
@ -3477,11 +3600,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
/* IP4_1_0 [2] */
FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
1, 2, 1, 4, 3, 4, 2, 2,
2, 2, 1, 1, 1, 1, 1, 1, 3) {
GROUP(1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
1, 1, 1, 1, 3),
GROUP(
/* IP5_31 [1] */
0, 0,
/* IP5_30_29 [2] */
@ -3523,10 +3647,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU1_DB2, FN_VI2_R4,
/* IP5_2_0 [3] */
FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
FN_RX5, FN_RTS0_D_TANS_D, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
GROUP(1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
2, 2, 2),
GROUP(
/* IP6_31 [1] */
0, 0,
/* IP6_30_29 [2] */
@ -3560,10 +3686,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP6_3_2 [2] */
FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
/* IP6_1_0 [2] */
FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
GROUP(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
3, 2, 2),
GROUP(
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
@ -3596,10 +3724,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_3_2 [2] */
FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
/* IP7_1_0 [2] */
FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
GROUP(1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30_28 [3] */
@ -3639,11 +3768,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
FN_CC5_STATE36, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2, 2, 2, 2, 2, 3, 3, 2, 2,
2, 2, 1, 1, 1, 1, 2, 2) {
GROUP(2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
1, 1, 1, 2, 2),
GROUP(
/* IP9_31_30 [2] */
0, 0, 0, 0,
/* IP9_29_28 [2] */
@ -3679,10 +3809,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP9_3_2 [2] */
FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
/* IP9_1_0 [2] */
FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP10_31_29 [3] */
FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
@ -3714,10 +3845,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DACK0_C, FN_DRACK0_C, 0, 0,
/* IP10_2_0 [3] */
FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP11_31_30 [2] */
0, 0, 0, 0,
/* IP11_29_27 [3] */
@ -3749,10 +3881,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ADICS_B_SAMP_B, 0, 0, 0,
/* IP11_2_0 [3] */
FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
FN_ADICLK_B, 0, 0, 0 }
FN_ADICLK_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
GROUP(4, 4, 4, 2, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP12_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -3781,11 +3914,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCL1_C, FN_HTX0_B, 0, 0,
/* IP12_2_0 [3] */
FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
FN_SCK2, FN_HSCK0_B, 0, 0 }
FN_SCK2, FN_HSCK0_B, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
2, 2, 3, 3, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
GROUP(2, 2, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1,
1, 1, 1, 1, 2, 1, 2),
GROUP(
/* SEL_SCIF5 [2] */
FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
/* SEL_SCIF4 [2] */
@ -3825,11 +3959,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_EXBUS1 [1] */
FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
/* SEL_EXBUS0 [2] */
FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
2, 2, 2, 2, 1, 1, 1, 3, 1,
2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, 2, 2, 2,
2, 1, 1, 2, 1, 2, 2),
GROUP(
/* SEL_TMU1 [2] */
FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
/* SEL_TMU0 [2] */
@ -3868,7 +4003,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_I2C2 [2] */
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 ))
},
{ },
};

132
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

@ -8,6 +8,7 @@
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*/
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
@ -4744,7 +4745,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP3_17_15,
GP_0_30_FN, FN_IP3_14_12,
GP_0_29_FN, FN_IP3_11_8,
@ -4776,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP0_11_9,
GP_0_2_FN, FN_IP0_8_6,
GP_0_1_FN, FN_IP0_5_3,
GP_0_0_FN, FN_IP0_2_0 }
GP_0_0_FN, FN_IP0_2_0 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
GP_1_29_FN, FN_IP6_13_11,
@ -4810,9 +4811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP3_28_26,
GP_1_2_FN, FN_IP3_25_23,
GP_1_1_FN, FN_IP3_22_20,
GP_1_0_FN, FN_IP3_19_18, }
GP_1_0_FN, FN_IP3_19_18, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
0, 0,
0, 0,
GP_2_29_FN, FN_IP7_15_13,
@ -4844,9 +4845,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP8_3_2,
GP_2_2_FN, FN_IP8_1_0,
GP_2_1_FN, FN_IP7_30_29,
GP_2_0_FN, FN_IP7_28_27 }
GP_2_0_FN, FN_IP7_28_27 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP11_21_18,
GP_3_30_FN, FN_IP11_17_15,
GP_3_29_FN, FN_IP11_14_13,
@ -4878,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP9_3_2,
GP_3_2_FN, FN_IP9_1_0,
GP_3_1_FN, FN_IP8_30_29,
GP_3_0_FN, FN_IP8_28 }
GP_3_0_FN, FN_IP8_28 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP14_18_16,
GP_4_30_FN, FN_IP14_15_12,
GP_4_29_FN, FN_IP14_11_9,
@ -4912,9 +4913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP11_31_30,
GP_4_2_FN, FN_IP11_29_27,
GP_4_1_FN, FN_IP11_26_24,
GP_4_0_FN, FN_IP11_23_22 }
GP_4_0_FN, FN_IP11_23_22 ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP7_24_22,
GP_5_30_FN, FN_IP7_21_19,
GP_5_29_FN, FN_IP7_18_16,
@ -4946,10 +4947,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_IP14_30_28,
GP_5_2_FN, FN_IP14_27_25,
GP_5_1_FN, FN_IP14_24_22,
GP_5_0_FN, FN_IP14_21_19 }
GP_5_0_FN, FN_IP14_21_19 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30_27 [4] */
@ -4982,10 +4984,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* IP0_2_0 [3] */
FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
0, 0, 0, }
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
GROUP(
/* IP1_31_30 [2] */
0, 0, 0, 0,
/* IP1_29_28 [2] */
@ -5019,10 +5022,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP1_3_0 [4] */
FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
0, 0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP2_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_28_26 [3] */
@ -5048,10 +5052,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP2_5_3 [3] */
FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
/* IP2_2_0 [3] */
FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
GROUP(
/* IP3_31_29 [3] */
FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
0, 0, 0,
@ -5081,10 +5086,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP3_3_0 [4] */
FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP4_31_30 [2] */
0, 0, 0, 0,
/* IP4_29_27 [3] */
@ -5114,10 +5120,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
/* IP4_2_0 [3] */
FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
}
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
GROUP(
/* IP5_31_30 [2] */
0, 0, 0, 0,
/* IP5_29_27 [3] */
@ -5151,10 +5158,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_INTC_EN0_N, FN_I2C1_SCL,
/* IP5_2_0 [3] */
FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
FN_VI2_R3, 0, 0, }
FN_VI2_R3, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
GROUP(
/* IP6_31_29 [3] */
FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
@ -5187,10 +5195,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
/* IP6_2_0 [3] */
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
GROUP(
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
@ -5222,11 +5231,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_MDIO, 0, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2) {
GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30_29 [2] */
@ -5263,10 +5273,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP8_3_2 [2] */
FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
/* IP8_1_0 [2] */
FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
GROUP(
/* IP9_31_28 [4] */
FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
@ -5298,10 +5309,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP9_3_2 [2] */
FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
/* IP9_1_0 [2] */
FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
2, 4, 3, 4, 4, 4, 4, 3, 4) {
GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
GROUP(
/* IP10_31_30 [2] */
0, 0, 0, 0,
/* IP10_29_26 [4] */
@ -5337,10 +5349,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP10_3_0 [4] */
FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
GROUP(
/* IP11_31_30 [2] */
FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
/* IP11_29_27 [3] */
@ -5372,10 +5385,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP11_3_0 [4] */
FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
GROUP(
/* IP12_31 [1] */
0, 0,
/* IP12_30_28 [3] */
@ -5411,10 +5425,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP12_3_2 [2] */
FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
/* IP12_1_0 [2] */
FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30_29 [2] */
@ -5447,10 +5462,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_2_0 [3] */
FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
GROUP(
/* IP14_30 [1] */
0, 0,
/* IP14_30_28 [3] */
@ -5485,10 +5501,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP14_2_0 [3] */
FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
FN_REMOCON, 0, }
FN_REMOCON, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_29_28 [2] */
@ -5520,10 +5537,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_IIC2_SCL, FN_I2C2_SCL, 0,
/* IP15_2_0 [3] */
FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -5551,11 +5569,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
/* IP16_2_0 [3] */
FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
1, 1, 1, 2, 1, 1, 2, 1, 1),
GROUP(
/* SEL_SCIF1 [3] */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF1_4, 0, 0, 0,
@ -5601,11 +5620,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SOF3 [1] */
FN_SEL_SOF3_0, FN_SEL_SOF3_1,
/* SEL_SOF0 [1] */
FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
3, 1, 1, 1, 2, 1, 2, 1, 2,
1, 1, 1, 3, 3, 2, 3, 2, 2) {
GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
3, 3, 2, 3, 2, 2),
GROUP(
/* RESERVED [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL_TMU1 [1] */
@ -5643,11 +5663,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SIM [2] */
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
/* SEL_SSI8 [2] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
1, 1, 2, 4, 4, 2, 2,
4, 2, 3, 2, 3, 2) {
GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
GROUP(
/* SEL_IICDVFS [1] */
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
/* SEL_IIC0 [1] */
@ -5678,7 +5698,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
FN_SEL_I2C2_4, 0, 0, 0,
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
},
{ },
};

156
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

@ -6,6 +6,7 @@
* Copyright (C) 2014-2017 Cogent Embedded, Inc.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
@ -5427,7 +5428,7 @@ static const struct {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP1_22_20,
GP_0_30_FN, FN_IP1_19_17,
GP_0_29_FN, FN_IP1_16_14,
@ -5459,9 +5460,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
GP_0_0_FN, FN_IP0_0, }
GP_0_0_FN, FN_IP0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5493,9 +5494,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP2_2_0,
GP_1_2_FN, FN_IP1_31_29,
GP_1_1_FN, FN_IP1_28_26,
GP_1_0_FN, FN_IP1_25_23, }
GP_1_0_FN, FN_IP1_25_23, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7_6,
GP_2_30_FN, FN_IP6_5_3,
GP_2_29_FN, FN_IP6_2_0,
@ -5527,9 +5528,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP4_4_2,
GP_2_2_FN, FN_IP4_1_0,
GP_2_1_FN, FN_IP3_30_28,
GP_2_0_FN, FN_IP3_27_25 }
GP_2_0_FN, FN_IP3_27_25 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP9_18_17,
GP_3_30_FN, FN_IP9_16,
GP_3_29_FN, FN_IP9_15_13,
@ -5561,9 +5562,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP7_12_11,
GP_3_2_FN, FN_IP7_10_9,
GP_3_1_FN, FN_IP7_8_6,
GP_3_0_FN, FN_IP7_5_3 }
GP_3_0_FN, FN_IP7_5_3 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP15_5_4,
GP_4_30_FN, FN_IP15_3_2,
GP_4_29_FN, FN_IP15_1_0,
@ -5595,9 +5596,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP9_24_23,
GP_4_2_FN, FN_IP9_22_21,
GP_4_1_FN, FN_IP9_20_19,
GP_4_0_FN, FN_VI0_CLK }
GP_4_0_FN, FN_VI0_CLK ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
GP_5_31_FN, FN_IP3_24_22,
GP_5_30_FN, FN_IP13_9_7,
GP_5_29_FN, FN_IP13_6_5,
@ -5629,9 +5630,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_IP11_18_17,
GP_5_2_FN, FN_IP11_16_15,
GP_5_1_FN, FN_IP11_14_12,
GP_5_0_FN, FN_IP11_11_9 }
GP_5_0_FN, FN_IP11_11_9 ))
},
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
GP_6_31_FN, FN_DU0_DOTCLKIN,
GP_6_30_FN, FN_USB1_OVC,
GP_6_29_FN, FN_IP14_31_29,
@ -5663,9 +5664,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, FN_IP13_13,
GP_6_2_FN, FN_IP13_12,
GP_6_1_FN, FN_IP13_11,
GP_6_0_FN, FN_IP13_10 }
GP_6_0_FN, FN_IP13_10 ))
},
{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5697,11 +5698,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_3_FN, FN_IP15_26_24,
GP_7_2_FN, FN_IP15_23_21,
GP_7_1_FN, FN_IP15_20_18,
GP_7_0_FN, FN_IP15_17_15 }
GP_7_0_FN, FN_IP15_17_15 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP0_31 [1] */
0, 0,
/* IP0_30_29 [2] */
@ -5756,10 +5758,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP0_1 [1] */
FN_D1, 0,
/* IP0_0 [1] */
FN_D0, 0, }
FN_D0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
GROUP(
/* IP1_31_29 [3] */
FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
0, 0, 0,
@ -5792,10 +5795,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
/* IP1_1_0 [2] */
FN_A7, FN_MSIOF1_SYNC,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
GROUP(
/* IP2_31_30 [2] */
0, 0, 0, 0,
/* IP2_29_27 [3] */
@ -5828,10 +5832,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_A20, FN_SPCLK, 0, 0,
/* IP2_2_0 [3] */
FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
GROUP(
/* IP3_31 [1] */
0, 0,
/* IP3_30_28 [3] */
@ -5866,10 +5871,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
/* IP3_2_0 [3] */
FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
0, 0, 0, }
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
3, 3, 2),
GROUP(
/* IP4_31 [1] */
0, 0,
/* IP4_30_28 [3] */
@ -5908,10 +5915,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
0, 0, 0,
/* IP4_1_0 [2] */
FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
GROUP(
/* IP5_31_29 [3] */
FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
0, 0, 0, 0, 0,
@ -5946,10 +5955,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP5_2_0 [3] */
FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
FN_MSIOF2_TXD_D, FN_VI1_R3_B,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
GROUP(
/* IP6_31_30 [2] */
0, 0, 0, 0,
/* IP6_29_27 [3] */
@ -5986,10 +5996,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP6_2_0 [3] */
FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
GROUP(
/* IP7_31_30 [2] */
0, 0, 0, 0,
/* IP7_29_27 [3] */
@ -6027,10 +6038,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_2_0 [3] */
FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
FN_SCIF_CLK_B, FN_GPS_MAG_D,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP8_31 [1] */
0, 0,
/* IP8_30_28 [3] */
@ -6070,10 +6082,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
/* IP8_2_0 [3] */
FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
0, 0, 0, }
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
1, 1, 3, 3),
GROUP(
/* IP9_31_29 [3] */
FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
@ -6113,10 +6127,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* IP9_2_0 [3] */
FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
0, 0, 0, }
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
GROUP(
/* IP10_31_29 [3] */
FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
0, 0, 0,
@ -6150,11 +6165,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
/* IP10_2_0 [3] */
FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3, 3, 3, 3, 3) {
GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
2, 3, 3, 3, 3, 3),
GROUP(
/* IP11_31_30 [2] */
FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
/* IP11_29_28 [2] */
@ -6197,10 +6213,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0,
/* IP11_2_0 [3] */
FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
FN_I2C1_SDA_D, 0, 0, 0, }
FN_I2C1_SDA_D, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_29_27 [3] */
@ -6238,11 +6255,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP12_3_2 [2] */
FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
/* IP12_1_0 [2] */
FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
3, 2, 2, 3) {
GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
1, 1, 1, 3, 2, 2, 3),
GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30_28 [3] */
@ -6289,10 +6307,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP13_2_0 [3] */
FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
FN_ADICLK_B, FN_MSIOF0_SS1_C,
0, 0, 0, }
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
1, 1, 2),
GROUP(
/* IP14_31_29 [3] */
FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
@ -6332,10 +6352,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP14_2 [1] */
FN_SD2_CLK, FN_MMC_CLK,
/* IP14_1_0 [2] */
FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
GROUP(
/* IP15_31_30 [2] */
0, 0, 0, 0,
/* IP15_29_27 [3] */
@ -6373,10 +6394,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP15_3_2 [2] */
FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
/* IP15_1_0 [2] */
FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
GROUP(
/* IP16_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -6405,11 +6427,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP16_2_0 [3] */
FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
FN_GLO_SDATA_C, FN_VI1_DATA6_C,
0, 0, 0, }
0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
3, 2, 2, 2, 1, 2, 2, 2) {
GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
2, 2, 1, 2, 2, 2),
GROUP(
/* RESERVED [1] */
0, 0,
/* SEL_SCIF1 [2] */
@ -6450,11 +6473,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_TSIF0 [2] */
FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
/* SEL_SOF0 [2] */
FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
3, 1, 1, 3, 2, 1, 1, 2, 2,
1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
1, 2, 2, 2, 1, 1, 1),
GROUP(
/* SEL_SCIF0 [3] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
@ -6498,11 +6522,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* RESERVED [1] */
0, 0,
/* SEL_SSI8 [1] */
FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
2, 2, 2, 2, 2, 2, 2, 2,
1, 1, 2, 2, 3, 2, 2, 2, 1) {
GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
3, 2, 2, 2, 1),
GROUP(
/* SEL_HSCIF2 [2] */
FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
@ -6540,11 +6565,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [1] */
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
3, 2, 2, 1, 1, 1, 1, 3, 2,
2, 3, 1, 1, 1, 2, 2, 2, 2) {
GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
1, 1, 2, 2, 2, 2),
GROUP(
/* SEL_SOF1 [3] */
FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
FN_SEL_SOF1_4,
@ -6586,7 +6612,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* RESERVED [2] */
0, 0, 0, 0,
/* RESERVED [2] */
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ },
};

134
drivers/pinctrl/sh-pfc/pfc-r8a7792.c
View File

@ -1988,7 +1988,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2020,9 +2020,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP0_3,
GP_0_2_FN, FN_IP0_2,
GP_0_1_FN, FN_IP0_1,
GP_0_0_FN, FN_IP0_0 }
GP_0_0_FN, FN_IP0_0 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2054,9 +2054,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP1_8,
GP_1_2_FN, FN_IP1_7,
GP_1_1_FN, FN_IP1_6,
GP_1_0_FN, FN_IP1_5, }
GP_1_0_FN, FN_IP1_5, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_A15,
GP_2_30_FN, FN_A14,
GP_2_29_FN, FN_A13,
@ -2088,9 +2088,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_D3,
GP_2_2_FN, FN_D2,
GP_2_1_FN, FN_D1,
GP_2_0_FN, FN_D0 }
GP_2_0_FN, FN_D0 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2122,9 +2122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_A19,
GP_3_2_FN, FN_A18,
GP_3_1_FN, FN_A17,
GP_3_0_FN, FN_A16 }
GP_3_0_FN, FN_A16 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2156,9 +2156,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_VI0_VSYNC_N,
GP_4_2_FN, FN_VI0_HSYNC_N,
GP_4_1_FN, FN_VI0_CLKENB,
GP_4_0_FN, FN_VI0_CLK }
GP_4_0_FN, FN_VI0_CLK ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2190,9 +2190,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_VI1_VSYNC_N,
GP_5_2_FN, FN_VI1_HSYNC_N,
GP_5_1_FN, FN_VI1_CLKENB,
GP_5_0_FN, FN_VI1_CLK }
GP_5_0_FN, FN_VI1_CLK ))
},
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2224,9 +2224,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, FN_IP2_3,
GP_6_2_FN, FN_IP2_2,
GP_6_1_FN, FN_IP2_1,
GP_6_0_FN, FN_IP2_0 }
GP_6_0_FN, FN_IP2_0 ))
},
{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2258,9 +2258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_3_FN, FN_IP3_3,
GP_7_2_FN, FN_IP3_2,
GP_7_1_FN, FN_IP3_1,
GP_7_0_FN, FN_IP3_0 }
GP_7_0_FN, FN_IP3_0 ))
},
{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2292,9 +2292,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_8_3_FN, FN_IP4_3_2,
GP_8_2_FN, FN_IP4_1,
GP_8_1_FN, FN_IP4_0,
GP_8_0_FN, FN_VI4_CLK }
GP_8_0_FN, FN_VI4_CLK ))
},
{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2326,9 +2326,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_9_3_FN, FN_IP5_2,
GP_9_2_FN, FN_IP5_1,
GP_9_1_FN, FN_IP5_0,
GP_9_0_FN, FN_VI5_CLK }
GP_9_0_FN, FN_VI5_CLK ))
},
{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
GP_10_31_FN, FN_CAN1_RX,
GP_10_30_FN, FN_CAN1_TX,
GP_10_29_FN, FN_CAN_CLK,
@ -2360,9 +2360,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_10_3_FN, FN_IP6_2,
GP_10_2_FN, FN_HRTS0_N,
GP_10_1_FN, FN_IP6_1,
GP_10_0_FN, FN_IP6_0 }
GP_10_0_FN, FN_IP6_0 ))
},
{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
0, 0,
0, 0,
GP_11_29_FN, FN_AVS2,
@ -2394,13 +2394,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_11_3_FN, FN_IP7_6,
GP_11_2_FN, FN_IP7_5_4,
GP_11_1_FN, FN_IP7_3_2,
GP_11_0_FN, FN_IP7_1_0 }
GP_11_0_FN, FN_IP7_1_0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP0_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP0_27_24 [4] */
@ -2452,13 +2453,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP0_1 [1] */
FN_DU0_DR1_DATA1, 0,
/* IP0_0 [1] */
FN_DU0_DR0_DATA0, 0 }
FN_DU0_DR0_DATA0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP1_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP1_27_24 [4] */
@ -2510,13 +2512,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP1_1 [1] */
FN_DU0_EXVSYNC_DU0_VSYNC, 0,
/* IP1_0 [1] */
FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
4, 4,
4, 3, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 3, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP2_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP2_27_24 [4] */
@ -2558,13 +2561,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP2_1 [1] */
FN_VI2_CLKENB, FN_AVB_RX_DV,
/* IP2_0 [1] */
FN_VI2_CLK, FN_AVB_RX_CLK }
FN_VI2_CLK, FN_AVB_RX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
4, 4,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 4,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP3_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP3_27_24 [4] */
@ -2604,12 +2608,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP3_1 [1] */
FN_VI3_CLKENB, FN_AVB_TXD4,
/* IP3_0 [1] */
FN_VI3_CLK, FN_AVB_TX_CLK }
FN_VI3_CLK, FN_AVB_TX_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
4, 3, 1,
1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 1, 2, 1, 1) {
GROUP(4, 3, 1,
1, 1, 1, 2, 2, 2,
2, 2, 2, 2, 2, 1, 2, 1, 1),
GROUP(
/* IP4_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP4_27_25 [3] */
@ -2645,13 +2650,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP4_1 [1] */
FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
/* IP4_0 [1] */
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
4, 4,
4, 4,
4, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 4,
4, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP5_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP5_27_24 [4] */
@ -2685,13 +2691,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP5_1 [1] */
FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
/* IP5_0 [1] */
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
4, 4,
4, 1, 2, 1,
2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4,
4, 1, 2, 1,
2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP6_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP6_27_24 [4] */
@ -2727,13 +2734,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP6_1 [1] */
FN_MSIOF0_SYNC, FN_HCTS0_N,
/* IP6_0 [1] */
FN_MSIOF0_SCK, FN_HSCK0 }
FN_MSIOF0_SCK, FN_HSCK0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
4, 4,
3, 1, 1, 1, 1, 1,
2, 2, 2, 2,
1, 1, 2, 2, 2) {
GROUP(4, 4,
3, 1, 1, 1, 1, 1,
2, 2, 2, 2,
1, 1, 2, 2, 2),
GROUP(
/* IP7_31_28 [4] */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP7_27_24 [4] */
@ -2767,7 +2775,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_3_2 [2] */
FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
/* IP7_1_0 [2] */
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
{ },
};

127
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
View File

@ -7,6 +7,7 @@
* Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
@ -4617,7 +4618,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
GP_0_31_FN, FN_IP2_17_16,
GP_0_30_FN, FN_IP2_15_14,
GP_0_29_FN, FN_IP2_13_12,
@ -4649,9 +4650,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP0_27_26,
GP_0_2_FN, FN_IP0_25,
GP_0_1_FN, FN_IP0_24,
GP_0_0_FN, FN_IP0_23_22, }
GP_0_0_FN, FN_IP0_23_22, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4683,9 +4684,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP2_29_27,
GP_1_2_FN, FN_IP2_26_24,
GP_1_1_FN, FN_IP2_23_21,
GP_1_0_FN, FN_IP2_20_18, }
GP_1_0_FN, FN_IP2_20_18, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP6_7_6,
GP_2_30_FN, FN_IP6_5_4,
GP_2_29_FN, FN_IP6_3_2,
@ -4717,9 +4718,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP4_11_10,
GP_2_2_FN, FN_IP4_9_8,
GP_2_1_FN, FN_IP4_7_5,
GP_2_0_FN, FN_IP4_4_2 }
GP_2_0_FN, FN_IP4_4_2 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
GP_3_31_FN, FN_IP8_22_20,
GP_3_30_FN, FN_IP8_19_17,
GP_3_29_FN, FN_IP8_16_15,
@ -4751,9 +4752,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP6_11,
GP_3_2_FN, FN_IP6_10,
GP_3_1_FN, FN_IP6_9,
GP_3_0_FN, FN_IP6_8 }
GP_3_0_FN, FN_IP6_8 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
GP_4_31_FN, FN_IP11_17_16,
GP_4_30_FN, FN_IP11_15_14,
GP_4_29_FN, FN_IP11_13_11,
@ -4785,9 +4786,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP9_2_0,
GP_4_2_FN, FN_IP8_31_29,
GP_4_1_FN, FN_IP8_28_26,
GP_4_0_FN, FN_IP8_25_23 }
GP_4_0_FN, FN_IP8_25_23 ))
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4819,9 +4820,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_IP11_29_27,
GP_5_2_FN, FN_IP11_26_24,
GP_5_1_FN, FN_IP11_23_21,
GP_5_0_FN, FN_IP11_20_18 }
GP_5_0_FN, FN_IP11_20_18 ))
},
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4853,11 +4854,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, FN_SD0_DATA1,
GP_6_2_FN, FN_SD0_DATA0,
GP_6_1_FN, FN_SD0_CMD,
GP_6_0_FN, FN_SD0_CLK }
GP_6_0_FN, FN_SD0_CLK ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
2, 1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* IP0_31_30 [2] */
FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
/* IP0_29_28 [2] */
@ -4907,11 +4909,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP0_1 [1] */
0, 0,
/* IP0_0 [1] */
FN_SD1_CD, FN_CAN0_RX, }
FN_SD1_CD, FN_CAN0_RX, ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
2, 2) {
GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
3, 2, 2, 2, 2),
GROUP(
/* IP1_31_30 [2] */
FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
/* IP1_29_28 [2] */
@ -4947,10 +4950,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP1_3_2 [2] */
FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
/* IP1_1_0 [2] */
FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* IP2_31_30 [2] */
FN_A20, FN_SPCLK, 0, 0,
/* IP2_29_27 [3] */
@ -4982,10 +4986,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP2_3_2 [2] */
FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
/* IP2_1_0 [2] */
FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
2, 2, 2, 2),
GROUP(
/* IP3_31 [1] */
FN_RD_WR_N, FN_ATAG1_N,
/* IP3_30 [1] */
@ -5022,10 +5028,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP3_3_2 [2] */
FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
/* IP3_1_0 [2] */
FN_A21, FN_MOSI_IO0, 0, 0, }
FN_A21, FN_MOSI_IO0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
GROUP(
/* IP4_31_30 [2] */
FN_DU0_DG4, FN_LCDOUT12, 0, 0,
/* IP4_29_28 [2] */
@ -5057,10 +5064,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
0, 0, 0, 0,
/* IP4_1_0 [2] */
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
2, 2, 2),
GROUP(
/* IP5_31_30 [2] */
FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
/* IP5_29_28 [2] */
@ -5092,11 +5101,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP5_3_2 [2] */
FN_DU0_DG6, FN_LCDOUT14, 0, 0,
/* IP5_1_0 [2] */
FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
2, 2) {
GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
1, 1, 2, 2, 2, 2),
GROUP(
/* IP6_31_29 [3] */
FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
@ -5138,10 +5148,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
0,
/* IP6_1_0 [2] */
FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP7_31 [1] */
FN_DREQ0_N, FN_SCIFB1_RXD,
/* IP7_30 [1] */
@ -5175,10 +5186,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AVB_TXD1, FN_ADICLK, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
GROUP(
/* IP8_31_29 [3] */
FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
@ -5210,10 +5222,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
/* IP8_2_0 [3] */
FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
GROUP(
/* IP9_31 [1] */
0, 0,
/* IP9_30_28 [3] */
@ -5246,10 +5259,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, FN_TPUTO1_C, 0, 0,
/* IP9_2_0 [3] */
FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP10_31_30 [2] */
FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
/* IP10_29_27 [3] */
@ -5281,10 +5295,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
/* IP10_2_0 [3] */
FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
GROUP(
/* IP11_31_30 [2] */
0, 0, 0, 0,
/* IP11_29_27 [3] */
@ -5316,10 +5331,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
/* IP11_2_0 [3] */
FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
GROUP(
/* IP12_31_30 [2] */
0, 0, 0, 0,
/* IP12_29_27 [3] */
@ -5351,10 +5367,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
/* IP12_2_0 [3] */
FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
0, FN_DREQ1_N_B, 0, 0, }
0, FN_DREQ1_N_B, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP13_31 [1] */
0, 0,
/* IP13_30 [1] */
@ -5391,11 +5408,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
/* IP13_2_0 [3] */
FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
2, 1) {
GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
GROUP(
/* SEL_ADG [2] */
FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
/* RESERVED [1] */
@ -5429,11 +5446,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_I2C05 [2] */
FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
/* RESERVED [1] */
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
2, 2, 2, 1, 1, 2) {
GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
GROUP(
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_IIC0 [2] */
@ -5480,11 +5498,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_HSCIF1 [1] */
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
/* RESERVED [2] */
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* SEL_SCIF0 [2] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
/* SEL_SCIF1 [2] */
@ -5537,7 +5556,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* RESERVED [1] */
0, 0,
/* RESERVED [1] */
0, 0, }
0, 0, ))
},
{ },
};

222
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
View File

@ -5,6 +5,7 @@
* Copyright (C) 2015-2017 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
@ -153,11 +154,11 @@
#define GPSR5_11 F_(RX2_A, IP12_7_4)
#define GPSR5_10 F_(TX2_A, IP12_3_0)
#define GPSR5_9 F_(SCK2, IP11_31_28)
#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
#define GPSR5_8 F_(RTS1_N, IP11_27_24)
#define GPSR5_7 F_(CTS1_N, IP11_23_20)
#define GPSR5_6 F_(TX1_A, IP11_19_16)
#define GPSR5_5 F_(RX1_A, IP11_15_12)
#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
#define GPSR5_4 F_(RTS0_N, IP11_11_8)
#define GPSR5_3 F_(CTS0_N, IP11_7_4)
#define GPSR5_2 F_(TX0, IP11_3_0)
#define GPSR5_1 F_(RX0, IP10_31_28)
@ -198,8 +199,8 @@
#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
/* GPSR7 */
#define GPSR7_3 FM(HDMI1_CEC)
#define GPSR7_2 FM(HDMI0_CEC)
#define GPSR7_3 FM(GP7_03)
#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
@ -210,7 +211,7 @@
#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -232,7 +233,7 @@
#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -248,7 +249,7 @@
#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -261,7 +262,7 @@
#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -299,11 +300,11 @@
#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -339,7 +340,7 @@
#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -576,8 +577,8 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@ -616,7 +617,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
@ -756,7 +757,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_7_4, A10),
PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
PINMUX_IPSR_GPSR(IP3_11_8, A11),
@ -859,7 +860,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
@ -940,7 +941,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
PINMUX_IPSR_GPSR(IP6_31_28, D12),
@ -1112,7 +1113,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
@ -1141,7 +1142,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
@ -1358,7 +1359,6 @@ static const u16 pinmux_data[] = {
/* IPSR16 */
PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
@ -2071,22 +2071,6 @@ static const unsigned int du_disp_pins[] = {
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HDMI ------------------------------------------------------------------- */
static const unsigned int hdmi0_cec_pins[] = {
/* HDMI0_CEC */
RCAR_GP_PIN(7, 2),
};
static const unsigned int hdmi0_cec_mux[] = {
HDMI0_CEC_MARK,
};
static const unsigned int hdmi1_cec_pins[] = {
/* HDMI1_CEC */
RCAR_GP_PIN(7, 3),
};
static const unsigned int hdmi1_cec_mux[] = {
HDMI1_CEC_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@ -3235,7 +3219,7 @@ static const unsigned int scif0_ctrl_pins[] = {
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_TANS_MARK, CTS0_N_MARK,
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
@ -3257,7 +3241,7 @@ static const unsigned int scif1_ctrl_pins[] = {
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_TANS_MARK, CTS1_N_MARK,
RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
@ -3309,7 +3293,7 @@ static const unsigned int scif3_ctrl_pins[] = {
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_TANS_MARK, CTS3_N_MARK,
RTS3_N_MARK, CTS3_N_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
/* RX, TX */
@ -3338,7 +3322,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
};
static const unsigned int scif4_ctrl_a_mux[] = {
RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
RTS4_N_A_MARK, CTS4_N_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
/* RX, TX */
@ -3359,7 +3343,7 @@ static const unsigned int scif4_ctrl_b_pins[] = {
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
};
static const unsigned int scif4_ctrl_b_mux[] = {
RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
RTS4_N_B_MARK, CTS4_N_B_MARK,
};
static const unsigned int scif4_data_c_pins[] = {
/* RX, TX */
@ -3380,7 +3364,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
};
static const unsigned int scif4_ctrl_c_mux[] = {
RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
RTS4_N_C_MARK, CTS4_N_C_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
static const unsigned int scif5_data_pins[] = {
@ -3944,8 +3928,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@ -4299,14 +4281,6 @@ static const char * const du_groups[] = {
"du_disp",
};
static const char * const hdmi0_groups[] = {
"hdmi0_cec",
};
static const char * const hdmi1_groups[] = {
"hdmi1_cec",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@ -4694,8 +4668,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@ -4745,7 +4717,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4777,9 +4749,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4811,9 +4783,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4845,9 +4817,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4879,9 +4851,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4913,9 +4885,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4947,9 +4919,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
@ -4981,9 +4953,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, }
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5015,14 +4987,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, }
GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -5030,9 +5002,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -5040,9 +5012,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -5050,9 +5022,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -5060,9 +5032,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -5070,9 +5042,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -5080,9 +5052,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -5090,9 +5062,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -5100,9 +5072,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_15_12
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -5110,9 +5082,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@ -5120,9 +5092,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 }
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@ -5130,9 +5102,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 }
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@ -5140,9 +5112,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 }
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@ -5150,9 +5122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 }
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@ -5160,9 +5132,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP13_15_12
IP13_11_8
IP13_7_4
IP13_3_0 }
IP13_3_0 ))
},
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@ -5170,9 +5142,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP14_15_12
IP14_11_8
IP14_7_4
IP14_3_0 }
IP14_3_0 ))
},
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@ -5180,9 +5152,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP15_15_12
IP15_11_8
IP15_7_4
IP15_3_0 }
IP15_3_0 ))
},
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
@ -5190,9 +5162,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP16_15_12
IP16_11_8
IP16_7_4
IP16_3_0 }
IP16_3_0 ))
},
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
/* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -5200,7 +5172,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP17_7_4
IP17_3_0 }
IP17_3_0 ))
},
#undef F_
#undef FM
@ -5208,8 +5180,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
GROUP(
0, 0, /* RESERVED 31 */
MOD_SEL0_30_29
MOD_SEL0_28_27
@ -5232,11 +5205,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_5_4
MOD_SEL0_3
MOD_SEL0_2_1
0, 0, /* RESERVED 0 */ }
0, 0, /* RESERVED 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2, 3, 1, 2, 3, 1, 1, 2, 1,
2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
@ -5259,11 +5233,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
MOD_SEL1_0 }
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
1, 1, 1, 1, 4, 4, 4,
4, 4, 4, 1, 2, 1) {
GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
@ -5291,7 +5265,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
/* RESERVED 2, 1 */
0, 0, 0, 0,
MOD_SEL2_0 }
MOD_SEL2_0 ))
},
{ },
};
@ -5412,8 +5386,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
} },
@ -5474,11 +5448,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
} },
{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
{ RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
{ RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
{ RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
{ RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
{ RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
{ RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
{ RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
{ RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
@ -5547,10 +5521,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
enum ioctrl_regs {
POCCTRL,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@ -5668,8 +5644,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
[29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
} },
@ -5724,11 +5700,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[13] = RCAR_GP_PIN(5, 1), /* RX0 */
[14] = RCAR_GP_PIN(5, 2), /* TX0 */
[15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
[16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
[17] = RCAR_GP_PIN(5, 5), /* RX1_A */
[18] = RCAR_GP_PIN(5, 6), /* TX1_A */
[19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
[20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
[21] = RCAR_GP_PIN(5, 9), /* SCK2 */
[22] = RCAR_GP_PIN(5, 10), /* TX2_A */
[23] = RCAR_GP_PIN(5, 11), /* RX2_A */

201
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View File

@ -2,9 +2,10 @@
/*
* R8A7795 ES2.0+ processor support - PFC hardware block.
*
* Copyright (C) 2015-2017 Renesas Electronics Corporation
* Copyright (C) 2015-2019 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/sys_soc.h>
@ -200,8 +201,8 @@
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
/* GPSR7 */
#define GPSR7_3 FM(HDMI1_CEC)
#define GPSR7_2 FM(HDMI0_CEC)
#define GPSR7_3 FM(GP7_03)
#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
@ -350,7 +351,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@ -461,7 +462,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@ -497,8 +498,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
@ -590,8 +591,8 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@ -1129,7 +1130,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@ -1162,7 +1163,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@ -1221,7 +1222,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@ -1268,7 +1269,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@ -1277,7 +1278,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@ -1408,10 +1409,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@ -2131,22 +2131,6 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HDMI ------------------------------------------------------------------- */
static const unsigned int hdmi0_cec_pins[] = {
/* HDMI0_CEC */
RCAR_GP_PIN(7, 2),
};
static const unsigned int hdmi0_cec_mux[] = {
HDMI0_CEC_MARK,
};
static const unsigned int hdmi1_cec_pins[] = {
/* HDMI1_CEC */
RCAR_GP_PIN(7, 3),
};
static const unsigned int hdmi1_cec_mux[] = {
HDMI1_CEC_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@ -4225,8 +4209,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@ -4611,14 +4593,6 @@ static const char * const du_groups[] = {
"du_disp",
};
static const char * const hdmi0_groups[] = {
"hdmi0_cec",
};
static const char * const hdmi1_groups[] = {
"hdmi1_cec",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@ -5037,8 +5011,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@ -5088,7 +5060,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5120,9 +5092,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5154,9 +5126,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5188,9 +5160,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5222,9 +5194,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5256,9 +5228,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5290,9 +5262,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
@ -5324,9 +5296,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, }
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5358,14 +5330,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, }
GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -5373,9 +5345,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -5383,9 +5355,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -5393,9 +5365,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -5403,9 +5375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -5413,9 +5385,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -5423,9 +5395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -5433,9 +5405,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -5443,9 +5415,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -5453,9 +5425,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@ -5463,9 +5435,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 }
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@ -5473,9 +5445,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 }
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@ -5483,9 +5455,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 }
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@ -5493,9 +5465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 }
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@ -5503,9 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP13_15_12
IP13_11_8
IP13_7_4
IP13_3_0 }
IP13_3_0 ))
},
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@ -5513,9 +5485,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP14_15_12
IP14_11_8
IP14_7_4
IP14_3_0 }
IP14_3_0 ))
},
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@ -5523,9 +5495,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP15_15_12
IP15_11_8
IP15_7_4
IP15_3_0 }
IP15_3_0 ))
},
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
@ -5533,9 +5505,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP16_15_12
IP16_11_8
IP16_7_4
IP16_3_0 }
IP16_3_0 ))
},
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
@ -5543,9 +5515,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_15_12
IP17_11_8
IP17_7_4
IP17_3_0 }
IP17_3_0 ))
},
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -5553,7 +5525,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
IP18_3_0 }
IP18_3_0 ))
},
#undef F_
#undef FM
@ -5561,8 +5533,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
1, 1, 1, 2, 2, 1, 2, 3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@ -5583,11 +5556,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2, 3, 1, 2, 3, 1, 1, 2, 1,
2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
@ -5610,11 +5584,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
MOD_SEL1_0 }
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4, 4, 4, 3, 1) {
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
1, 4, 4, 4, 3, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
@ -5641,7 +5616,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
MOD_SEL2_0 }
MOD_SEL2_0 ))
},
{ },
};
@ -5762,8 +5737,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
} },
@ -5897,10 +5872,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
enum ioctrl_regs {
POCCTRL,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@ -6017,8 +5994,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
[29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
} },

225
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View File

@ -2,7 +2,7 @@
/*
* R8A7796 processor support - PFC hardware block.
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
*
@ -11,6 +11,7 @@
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
@ -206,7 +207,7 @@
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
#define GPSR7_2 FM(HDMI0_CEC)
#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
@ -355,7 +356,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@ -466,7 +467,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@ -499,12 +500,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
@ -597,7 +598,7 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@ -1021,35 +1022,35 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
@ -1115,28 +1116,28 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@ -1169,7 +1170,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@ -1228,7 +1229,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@ -1274,8 +1275,8 @@ static const u16 pinmux_data[] = {
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@ -1284,7 +1285,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@ -1412,10 +1413,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@ -1499,11 +1499,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
/* I2C */
PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
@ -2140,15 +2135,6 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HDMI ------------------------------------------------------------------- */
static const unsigned int hdmi0_cec_pins[] = {
/* HDMI0_CEC */
RCAR_GP_PIN(7, 2),
};
static const unsigned int hdmi0_cec_mux[] = {
HDMI0_CEC_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@ -4124,8 +4110,8 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[310];
struct sh_pfc_pin_group automotive[33];
struct sh_pfc_pin_group common[312];
struct sh_pfc_pin_group automotive[30];
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
@ -4160,6 +4146,9 @@ static const struct {
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
@ -4168,7 +4157,6 @@ static const struct {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@ -4440,9 +4428,6 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clk),
},
.automotive = {
SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
@ -4585,10 +4570,6 @@ static const char * const du_groups[] = {
"du_disp",
};
static const char * const hdmi0_groups[] = {
"hdmi0_cec",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@ -4982,8 +4963,8 @@ static const char * const vin5_groups[] = {
};
static const struct {
struct sh_pfc_function common[48];
struct sh_pfc_function automotive[6];
struct sh_pfc_function common[49];
struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@ -4991,8 +4972,9 @@ static const struct {
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@ -5036,8 +5018,6 @@ static const struct {
SH_PFC_FUNCTION(vin5),
},
.automotive = {
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
@ -5048,7 +5028,7 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5080,9 +5060,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5114,9 +5094,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5148,9 +5128,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5182,9 +5162,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5216,9 +5196,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5250,9 +5230,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
@ -5284,9 +5264,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, }
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5318,14 +5298,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, }
GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -5333,9 +5313,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -5343,9 +5323,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -5353,9 +5333,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -5363,9 +5343,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -5373,9 +5353,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -5383,9 +5363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -5393,9 +5373,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -5403,9 +5383,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -5413,9 +5393,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@ -5423,9 +5403,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 }
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@ -5433,9 +5413,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 }
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@ -5443,9 +5423,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 }
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@ -5453,9 +5433,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 }
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@ -5463,9 +5443,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP13_15_12
IP13_11_8
IP13_7_4
IP13_3_0 }
IP13_3_0 ))
},
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@ -5473,9 +5453,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP14_15_12
IP14_11_8
IP14_7_4
IP14_3_0 }
IP14_3_0 ))
},
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@ -5483,9 +5463,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP15_15_12
IP15_11_8
IP15_7_4
IP15_3_0 }
IP15_3_0 ))
},
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
@ -5493,9 +5473,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP16_15_12
IP16_11_8
IP16_7_4
IP16_3_0 }
IP16_3_0 ))
},
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
@ -5503,9 +5483,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_15_12
IP17_11_8
IP17_7_4
IP17_3_0 }
IP17_3_0 ))
},
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -5513,7 +5493,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
IP18_3_0 }
IP18_3_0 ))
},
#undef F_
#undef FM
@ -5521,8 +5501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
1, 1, 1, 2, 2, 1, 2, 3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@ -5543,11 +5524,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2, 3, 1, 2, 3, 1, 1, 2, 1,
2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
@ -5570,11 +5552,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
MOD_SEL1_0 }
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4, 4, 4, 3, 1) {
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
1, 4, 4, 4, 3, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
@ -5600,7 +5583,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
MOD_SEL2_0 }
MOD_SEL2_0 ))
},
{ },
};
@ -5721,7 +5704,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@ -5855,10 +5838,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
enum ioctrl_regs {
POCCTRL,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@ -5975,7 +5960,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */

294
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
View File

@ -3,7 +3,7 @@
* R8A77965 processor support - PFC hardware block.
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
@ -12,6 +12,7 @@
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
@ -207,7 +208,7 @@
/* GPSR7 */
#define GPSR7_3 FM(GP7_03)
#define GPSR7_2 FM(HDMI0_CEC)
#define GPSR7_2 FM(GP7_02)
#define GPSR7_1 FM(AVS2)
#define GPSR7_0 FM(AVS1)
@ -356,7 +357,7 @@
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
@ -467,7 +468,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@ -500,12 +501,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
#define PINMUX_MOD_SELS \
@ -557,6 +558,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
enum {
PINMUX_RESERVED = 0,
@ -582,6 +586,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
@ -594,7 +599,7 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(GP7_03),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(GP7_02),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@ -619,13 +624,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@ -678,14 +685,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@ -1016,35 +1025,35 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
@ -1111,26 +1120,28 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
@ -1163,7 +1174,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
@ -1222,7 +1233,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
@ -1268,8 +1279,8 @@ static const u16 pinmux_data[] = {
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
@ -1278,7 +1289,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
@ -1407,10 +1418,9 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
@ -1494,11 +1504,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
/* I2C */
PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
/*
* Static pins can not be muxed between different functions but
* still need mark entries in the pinmux list. Add each static
@ -2478,52 +2483,92 @@ static const unsigned int hscif4_data_b_mux[] = {
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
};
static const unsigned int i2c0_mux[] = {
SCL0_MARK, SDA0_MARK,
};
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
};
static const unsigned int i2c1_a_mux[] = {
SDA1_A_MARK, SCL1_A_MARK,
};
static const unsigned int i2c1_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
};
static const unsigned int i2c1_b_mux[] = {
SDA1_B_MARK, SCL1_B_MARK,
};
static const unsigned int i2c2_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
};
static const unsigned int i2c2_a_mux[] = {
SDA2_A_MARK, SCL2_A_MARK,
};
static const unsigned int i2c2_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
static const unsigned int i2c2_b_mux[] = {
SDA2_B_MARK, SCL2_B_MARK,
};
static const unsigned int i2c3_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int i2c3_mux[] = {
SCL3_MARK, SDA3_MARK,
};
static const unsigned int i2c5_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
};
static const unsigned int i2c5_mux[] = {
SCL5_MARK, SDA5_MARK,
};
static const unsigned int i2c6_a_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int i2c6_a_mux[] = {
SDA6_A_MARK, SCL6_A_MARK,
};
static const unsigned int i2c6_b_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int i2c6_b_mux[] = {
SDA6_B_MARK, SCL6_B_MARK,
};
static const unsigned int i2c6_c_pins[] = {
/* SDA, SCL */
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
};
static const unsigned int i2c6_c_mux[] = {
SDA6_C_MARK, SCL6_C_MARK,
};
@ -4413,10 +4458,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
@ -4807,6 +4855,10 @@ static const char * const hscif4_groups[] = {
"hscif4_data_b",
};
static const char * const i2c0_groups[] = {
"i2c0",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@ -4817,6 +4869,14 @@ static const char * const i2c2_groups[] = {
"i2c2_b",
};
static const char * const i2c3_groups[] = {
"i2c3",
};
static const char * const i2c5_groups[] = {
"i2c5",
};
static const char * const i2c6_groups[] = {
"i2c6_a",
"i2c6_b",
@ -5166,8 +5226,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
@ -5205,7 +5268,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5237,9 +5300,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5271,9 +5334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5305,9 +5368,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5339,9 +5402,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5373,9 +5436,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5407,9 +5470,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
GP_6_31_FN, GPSR6_31,
GP_6_30_FN, GPSR6_30,
GP_6_29_FN, GPSR6_29,
@ -5441,9 +5504,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, }
GP_6_0_FN, GPSR6_0, ))
},
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
{ PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -5475,14 +5538,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
GP_7_0_FN, GPSR7_0, }
GP_7_0_FN, GPSR7_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -5490,9 +5553,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -5500,9 +5563,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -5510,9 +5573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -5520,9 +5583,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -5530,9 +5593,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -5540,9 +5603,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -5550,9 +5613,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -5560,9 +5623,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -5570,9 +5633,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@ -5580,9 +5643,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 }
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@ -5590,9 +5653,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 }
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@ -5600,9 +5663,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 }
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@ -5610,9 +5673,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 }
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@ -5620,9 +5683,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP13_15_12
IP13_11_8
IP13_7_4
IP13_3_0 }
IP13_3_0 ))
},
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@ -5630,9 +5693,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP14_15_12
IP14_11_8
IP14_7_4
IP14_3_0 }
IP14_3_0 ))
},
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@ -5640,9 +5703,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP15_15_12
IP15_11_8
IP15_7_4
IP15_3_0 }
IP15_3_0 ))
},
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
IP16_31_28
IP16_27_24
IP16_23_20
@ -5650,9 +5713,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP16_15_12
IP16_11_8
IP16_7_4
IP16_3_0 }
IP16_3_0 ))
},
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
IP17_31_28
IP17_27_24
IP17_23_20
@ -5660,9 +5723,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_15_12
IP17_11_8
IP17_7_4
IP17_3_0 }
IP17_3_0 ))
},
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
{ PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
/* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -5670,7 +5733,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP18_7_4
IP18_3_0 }
IP18_3_0 ))
},
#undef F_
#undef FM
@ -5678,8 +5741,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
1, 1, 1, 2, 2, 1, 2, 3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
MOD_SEL0_26_25_24
@ -5700,11 +5764,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_5
MOD_SEL0_4_3
/* RESERVED 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2, 3, 1, 2, 3, 1, 1, 2, 1,
2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
MOD_SEL1_26
@ -5727,11 +5792,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_3
MOD_SEL1_2
MOD_SEL1_1
MOD_SEL1_0 }
MOD_SEL1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4, 4, 4, 3, 1) {
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
1, 4, 4, 4, 3, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
MOD_SEL2_29
@ -5757,7 +5823,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1 */
0, 0, 0, 0, 0, 0, 0, 0,
MOD_SEL2_0 }
MOD_SEL2_0 ))
},
{ },
};
@ -5878,7 +5944,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
@ -6012,10 +6078,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
enum ioctrl_regs {
POCCTRL,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@ -6132,7 +6200,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[25] = RCAR_GP_PIN(0, 15), /* D15 */
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */

123
drivers/pinctrl/sh-pfc/pfc-r8a77970.c
View File

@ -12,6 +12,7 @@
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
@ -171,19 +172,19 @@
#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -198,18 +199,18 @@
#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -470,7 +471,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
@ -496,7 +496,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
@ -527,7 +527,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
@ -617,7 +617,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS),
PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
PINMUX_IPSR_GPSR(IP6_23_20, D12),
PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
@ -664,7 +664,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
@ -1468,7 +1468,7 @@ static const unsigned int scif0_ctrl_pins[] = {
RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_TANS_MARK, CTS0_N_MARK,
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
@ -1491,7 +1491,7 @@ static const unsigned int scif1_ctrl_pins[] = {
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_TANS_MARK, CTS1_N_MARK,
RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX, TX */
@ -1521,7 +1521,7 @@ static const unsigned int scif3_ctrl_pins[] = {
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
};
static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_TANS_MARK, CTS3_N_MARK,
RTS3_N_MARK, CTS3_N_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
@ -1544,7 +1544,7 @@ static const unsigned int scif4_ctrl_pins[] = {
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
};
static const unsigned int scif4_ctrl_mux[] = {
RTS4_N_TANS_MARK, CTS4_N_MARK,
RTS4_N_MARK, CTS4_N_MARK,
};
/* - TMU -------------------------------------------------------------------- */
@ -2072,7 +2072,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2104,9 +2104,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2138,9 +2138,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2172,9 +2172,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2206,9 +2206,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2240,9 +2240,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2274,14 +2274,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -2289,9 +2289,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -2299,9 +2299,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -2309,9 +2309,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -2319,9 +2319,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -2329,9 +2329,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -2339,9 +2339,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -2349,9 +2349,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -2359,9 +2359,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_15_12
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -2369,7 +2369,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
#undef F_
#undef FM
@ -2377,8 +2377,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4, 4, 4, 4, 4,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* RESERVED 31, 30, 29, 28 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 27, 26, 25, 24 */
@ -2400,21 +2401,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1
MOD_SEL0_0 }
MOD_SEL0_0 ))
},
{ },
};
enum ioctrl_regs {
IOCTRL30,
IOCTRL31,
IOCTRL32,
POCCTRL0,
POCCTRL1,
POCCTRL2,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[IOCTRL30] = { 0xe6060380 },
[IOCTRL31] = { 0xe6060384 },
[IOCTRL32] = { 0xe6060388 },
[POCCTRL0] = { 0xe6060380 },
[POCCTRL1] = { 0xe6060384 },
[POCCTRL2] = { 0xe6060388 },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@ -2423,13 +2426,13 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
{
int bit = pin & 0x1f;
*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
return bit;
if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
return bit + 22;
*pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
return bit - 10;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))

135
drivers/pinctrl/sh-pfc/pfc-r8a77980.c
View File

@ -12,6 +12,7 @@
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
@ -186,7 +187,7 @@
#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(DU_DR6) FM(RTS4_N_TANS) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -204,19 +205,19 @@
#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -242,7 +243,7 @@
#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -469,7 +470,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP0_15_12, A3),
PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N_TANS),
PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
PINMUX_IPSR_GPSR(IP0_19_16, A4),
@ -554,7 +555,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
@ -580,7 +580,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS),
PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
@ -609,7 +609,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS),
PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
@ -728,7 +728,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS),
PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
@ -1726,11 +1726,11 @@ static const unsigned int scif0_clk_mux[] = {
SCK0_MARK,
};
static const unsigned int scif0_ctrl_pins[] = {
/* RTS0#/TANS, CTS0# */
/* RTS0#, CTS0# */
RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_TANS_MARK, CTS0_N_MARK,
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
@ -1749,11 +1749,11 @@ static const unsigned int scif1_clk_mux[] = {
SCK1_MARK,
};
static const unsigned int scif1_ctrl_pins[] = {
/* RTS1#/TANS, CTS1# */
/* RTS1#, CTS1# */
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_TANS_MARK, CTS1_N_MARK,
RTS1_N_MARK, CTS1_N_MARK,
};
static const unsigned int scif1_data_b_pins[] = {
/* RX1, TX1 */
@ -1779,11 +1779,11 @@ static const unsigned int scif3_clk_mux[] = {
SCK3_MARK,
};
static const unsigned int scif3_ctrl_pins[] = {
/* RTS3#/TANS, CTS3# */
/* RTS3#, CTS3# */
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
};
static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_TANS_MARK, CTS3_N_MARK,
RTS3_N_MARK, CTS3_N_MARK,
};
/* - SCIF4 ------------------------------------------------------------------ */
@ -1802,11 +1802,11 @@ static const unsigned int scif4_clk_mux[] = {
SCK4_MARK,
};
static const unsigned int scif4_ctrl_pins[] = {
/* RTS4#/TANS, CTS4# */
/* RTS4#, CTS4# */
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
};
static const unsigned int scif4_ctrl_mux[] = {
RTS4_N_TANS_MARK, CTS4_N_MARK,
RTS4_N_MARK, CTS4_N_MARK,
};
/* - SCIF Clock ------------------------------------------------------------- */
@ -2474,7 +2474,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2506,9 +2506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2540,9 +2540,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
GP_2_29_FN, GPSR2_29,
@ -2574,9 +2574,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2608,9 +2608,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2642,9 +2642,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2676,14 +2676,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -2691,9 +2691,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -2701,9 +2701,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -2711,9 +2711,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -2721,9 +2721,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -2731,9 +2731,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -2741,9 +2741,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -2751,9 +2751,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -2761,9 +2761,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_15_12
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -2771,9 +2771,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@ -2781,9 +2781,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 }
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@ -2791,7 +2791,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 }
IP10_3_0 ))
},
#undef F_
#undef FM
@ -2799,8 +2799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4, 4, 4, 4, 4,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1),
GROUP(
/* RESERVED 31, 30, 29, 28 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 27, 26, 25, 24 */
@ -2822,23 +2823,25 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MOD_SEL0_2
MOD_SEL0_1
MOD_SEL0_0 }
MOD_SEL0_0 ))
},
{ },
};
enum ioctrl_regs {
IOCTRL30,
IOCTRL31,
IOCTRL32,
IOCTRL33,
POCCTRL0,
POCCTRL1,
POCCTRL2,
POCCTRL3,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[IOCTRL30] = { 0xe6060380, },
[IOCTRL31] = { 0xe6060384, },
[IOCTRL32] = { 0xe6060388, },
[IOCTRL33] = { 0xe606038c, },
[POCCTRL0] = { 0xe6060380, },
[POCCTRL1] = { 0xe6060384, },
[POCCTRL2] = { 0xe6060388, },
[POCCTRL3] = { 0xe606038c, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@ -2847,20 +2850,20 @@ static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
{
int bit = pin & 0x1f;
*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
return bit;
else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
return bit + 22;
*pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
return bit - 10;
if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
(pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
return bit + 7;
*pocctrl = pinmux_ioctrl_regs[IOCTRL32].reg;
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
return pin - 25;

214
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
View File

@ -2,7 +2,7 @@
/*
* R8A77990 processor support - PFC hardware block.
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
*
@ -11,6 +11,7 @@
* Copyright (C) 2016-2017 Renesas Electronics Corp.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
@ -165,7 +166,7 @@
#define GPSR5_7 F_(SCK2_A, IP12_7_4)
#define GPSR5_6 F_(TX1, IP12_3_0)
#define GPSR5_5 F_(RX1, IP11_31_28)
#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
#define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
#define GPSR5_2 F_(TX0_A, IP11_15_12)
#define GPSR5_1 F_(RX0_A, IP11_11_8)
@ -219,7 +220,7 @@
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -240,10 +241,10 @@
#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -289,8 +290,8 @@
#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
@ -414,7 +415,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
@ -429,8 +430,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@ -451,8 +450,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define PINMUX_MOD_SELS \
\
MOD_SEL1_31 \
MOD_SEL0_30_29 MOD_SEL1_30 \
MOD_SEL0_30_29 \
MOD_SEL1_29 \
MOD_SEL0_28 MOD_SEL1_28 \
MOD_SEL0_27_26 \
@ -671,7 +669,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
PINMUX_IPSR_GPSR(IP3_15_12, A4),
PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
@ -821,7 +819,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
PINMUX_IPSR_GPSR(IP5_31_28, D2),
@ -845,7 +843,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
@ -984,23 +982,23 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
/* IPSR9 */
PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
@ -1037,57 +1035,57 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
@ -1096,7 +1094,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
@ -1180,7 +1178,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
@ -1248,7 +1246,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
@ -2839,7 +2837,7 @@ static const unsigned int scif0_ctrl_a_pins[] = {
};
static const unsigned int scif0_ctrl_a_mux[] = {
RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
RTS0_N_A_MARK, CTS0_N_A_MARK,
};
static const unsigned int scif0_data_b_pins[] = {
@ -2885,7 +2883,7 @@ static const unsigned int scif1_ctrl_pins[] = {
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_TANS_MARK, CTS1_N_MARK,
RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
@ -2941,7 +2939,7 @@ static const unsigned int scif3_ctrl_a_pins[] = {
};
static const unsigned int scif3_ctrl_a_mux[] = {
RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
RTS3_N_A_MARK, CTS3_N_A_MARK,
};
static const unsigned int scif3_data_b_pins[] = {
@ -2996,7 +2994,7 @@ static const unsigned int scif4_ctrl_a_pins[] = {
};
static const unsigned int scif4_ctrl_a_mux[] = {
RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
RTS4_N_A_MARK, CTS4_N_A_MARK,
};
static const unsigned int scif4_data_b_pins[] = {
@ -3032,7 +3030,7 @@ static const unsigned int scif4_ctrl_c_pins[] = {
};
static const unsigned int scif4_ctrl_c_mux[] = {
RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
RTS4_N_C_MARK, CTS4_N_C_MARK,
};
/* - SCIF5 ------------------------------------------------------------------ */
@ -3766,8 +3764,8 @@ static const unsigned int vin5_clk_b_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[245];
struct sh_pfc_pin_group automotive[23];
struct sh_pfc_pin_group common[247];
struct sh_pfc_pin_group automotive[21];
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a),
@ -3798,6 +3796,8 @@ static const struct {
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_in_0),
@ -4017,8 +4017,6 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clk_b),
},
.automotive = {
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(drif0_data1_a),
@ -4465,8 +4463,8 @@ static const char * const vin5_groups[] = {
};
static const struct {
struct sh_pfc_function common[45];
struct sh_pfc_function automotive[6];
struct sh_pfc_function common[47];
struct sh_pfc_function automotive[4];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
@ -4474,6 +4472,8 @@ static const struct {
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
@ -4516,8 +4516,6 @@ static const struct {
SH_PFC_FUNCTION(vin5),
},
.automotive = {
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
@ -4528,7 +4526,7 @@ static const struct {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4560,9 +4558,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4594,9 +4592,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4628,9 +4626,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4662,9 +4660,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4696,9 +4694,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4730,9 +4728,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4764,14 +4762,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, }
GP_6_0_FN, GPSR6_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -4779,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -4789,9 +4787,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -4799,9 +4797,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -4809,9 +4807,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -4819,9 +4817,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -4829,9 +4827,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -4839,9 +4837,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -4849,9 +4847,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_15_12
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -4859,9 +4857,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@ -4869,9 +4867,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 }
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@ -4879,9 +4877,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 }
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@ -4889,9 +4887,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 }
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@ -4899,9 +4897,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 }
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
IP13_31_28
IP13_27_24
IP13_23_20
@ -4909,9 +4907,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP13_15_12
IP13_11_8
IP13_7_4
IP13_3_0 }
IP13_3_0 ))
},
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
IP14_31_28
IP14_27_24
IP14_23_20
@ -4919,9 +4917,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP14_15_12
IP14_11_8
IP14_7_4
IP14_3_0 }
IP14_3_0 ))
},
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
IP15_31_28
IP15_27_24
IP15_23_20
@ -4929,7 +4927,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP15_15_12
IP15_11_8
IP15_7_4
IP15_3_0 }
IP15_3_0 ))
},
#undef F_
#undef FM
@ -4937,8 +4935,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
GROUP(
/* RESERVED 31 */
0, 0,
MOD_SEL0_30_29
@ -4962,13 +4961,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_4
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1_0 }
MOD_SEL0_1_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
1, 2, 2, 2, 1, 1, 2, 1, 4) {
MOD_SEL1_31
MOD_SEL1_30
GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
2, 2, 2, 1, 1, 2, 1, 4),
GROUP(
/* RESERVED 31, 30 */
0, 0, 0, 0,
MOD_SEL1_29
MOD_SEL1_28
/* RESERVED 27 */
@ -4989,17 +4989,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_6_5
MOD_SEL1_4
/* RESERVED 3, 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ },
};
enum ioctrl_regs {
IOCTRL30,
POCCTRL0,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[IOCTRL30] = { 0xe6060380, },
[POCCTRL0] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@ -5008,7 +5010,7 @@ static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
{
int bit = -EINVAL;
*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
bit = pin & 0x1f;
@ -5124,7 +5126,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
} },
{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
[0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
[1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */
[1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
[2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
[3] = RCAR_GP_PIN(5, 2), /* TX0_A */
[4] = RCAR_GP_PIN(5, 1), /* RX0_A */

120
drivers/pinctrl/sh-pfc/pfc-r8a77995.c
View File

@ -11,6 +11,7 @@
* Copyright (C) 2015 Renesas Electronics Corporation
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
@ -287,7 +288,7 @@
#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -298,7 +299,7 @@
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -857,7 +858,7 @@ static const u16 pinmux_data[] = {
/* IPSR11 */
PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
@ -892,7 +893,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
@ -1704,7 +1705,7 @@ static const unsigned int scif0_ctrl_pins[] = {
RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
};
static const unsigned int scif0_ctrl_mux[] = {
RTS0_N_TANS_MARK, CTS0_N_MARK,
RTS0_N_MARK, CTS0_N_MARK,
};
/* - SCIF1 ------------------------------------------------------------------ */
static const unsigned int scif1_data_a_pins[] = {
@ -1740,7 +1741,7 @@ static const unsigned int scif1_ctrl_pins[] = {
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
};
static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_TANS_MARK, CTS1_N_MARK,
RTS1_N_MARK, CTS1_N_MARK,
};
/* - SCIF2 ------------------------------------------------------------------ */
@ -2374,7 +2375,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2406,9 +2407,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, GPSR0_3,
GP_0_2_FN, GPSR0_2,
GP_0_1_FN, GPSR0_1,
GP_0_0_FN, GPSR0_0, }
GP_0_0_FN, GPSR0_0, ))
},
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
GP_1_31_FN, GPSR1_31,
GP_1_30_FN, GPSR1_30,
GP_1_29_FN, GPSR1_29,
@ -2440,9 +2441,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, GPSR1_3,
GP_1_2_FN, GPSR1_2,
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, }
GP_1_0_FN, GPSR1_0, ))
},
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
GP_2_31_FN, GPSR2_31,
GP_2_30_FN, GPSR2_30,
GP_2_29_FN, GPSR2_29,
@ -2474,9 +2475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, GPSR2_3,
GP_2_2_FN, GPSR2_2,
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, }
GP_2_0_FN, GPSR2_0, ))
},
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2508,9 +2509,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, GPSR3_3,
GP_3_2_FN, GPSR3_2,
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, }
GP_3_0_FN, GPSR3_0, ))
},
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
GP_4_31_FN, GPSR4_31,
GP_4_30_FN, GPSR4_30,
GP_4_29_FN, GPSR4_29,
@ -2542,9 +2543,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, GPSR4_3,
GP_4_2_FN, GPSR4_2,
GP_4_1_FN, GPSR4_1,
GP_4_0_FN, GPSR4_0, }
GP_4_0_FN, GPSR4_0, ))
},
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2576,9 +2577,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, GPSR5_3,
GP_5_2_FN, GPSR5_2,
GP_5_1_FN, GPSR5_1,
GP_5_0_FN, GPSR5_0, }
GP_5_0_FN, GPSR5_0, ))
},
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2610,14 +2611,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_3_FN, GPSR6_3,
GP_6_2_FN, GPSR6_2,
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, }
GP_6_0_FN, GPSR6_0, ))
},
#undef F_
#undef FM
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
IP0_31_28
IP0_27_24
IP0_23_20
@ -2625,9 +2626,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP0_15_12
IP0_11_8
IP0_7_4
IP0_3_0 }
IP0_3_0 ))
},
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
IP1_31_28
IP1_27_24
IP1_23_20
@ -2635,9 +2636,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP1_15_12
IP1_11_8
IP1_7_4
IP1_3_0 }
IP1_3_0 ))
},
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
IP2_31_28
IP2_27_24
IP2_23_20
@ -2645,9 +2646,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP2_15_12
IP2_11_8
IP2_7_4
IP2_3_0 }
IP2_3_0 ))
},
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
IP3_31_28
IP3_27_24
IP3_23_20
@ -2655,9 +2656,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP3_15_12
IP3_11_8
IP3_7_4
IP3_3_0 }
IP3_3_0 ))
},
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
IP4_31_28
IP4_27_24
IP4_23_20
@ -2665,9 +2666,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP4_15_12
IP4_11_8
IP4_7_4
IP4_3_0 }
IP4_3_0 ))
},
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
IP5_31_28
IP5_27_24
IP5_23_20
@ -2675,9 +2676,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP5_15_12
IP5_11_8
IP5_7_4
IP5_3_0 }
IP5_3_0 ))
},
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
IP6_31_28
IP6_27_24
IP6_23_20
@ -2685,9 +2686,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_15_12
IP6_11_8
IP6_7_4
IP6_3_0 }
IP6_3_0 ))
},
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
@ -2695,9 +2696,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_15_12
IP7_11_8
IP7_7_4
IP7_3_0 }
IP7_3_0 ))
},
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
IP8_31_28
IP8_27_24
IP8_23_20
@ -2705,9 +2706,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP8_15_12
IP8_11_8
IP8_7_4
IP8_3_0 }
IP8_3_0 ))
},
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
IP9_31_28
IP9_27_24
IP9_23_20
@ -2715,9 +2716,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP9_15_12
IP9_11_8
IP9_7_4
IP9_3_0 }
IP9_3_0 ))
},
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
IP10_31_28
IP10_27_24
IP10_23_20
@ -2725,9 +2726,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP10_15_12
IP10_11_8
IP10_7_4
IP10_3_0 }
IP10_3_0 ))
},
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
IP11_31_28
IP11_27_24
IP11_23_20
@ -2735,9 +2736,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP11_15_12
IP11_11_8
IP11_7_4
IP11_3_0 }
IP11_3_0 ))
},
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
IP12_31_28
IP12_27_24
IP12_23_20
@ -2745,9 +2746,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP12_15_12
IP12_11_8
IP12_7_4
IP12_3_0 }
IP12_3_0 ))
},
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
/* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -2755,7 +2756,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP13_7_4
IP13_3_0 }
IP13_3_0 ))
},
#undef F_
#undef FM
@ -2763,8 +2764,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
GROUP(
/* RESERVED 31 */
0, 0,
MOD_SEL0_30
@ -2792,11 +2794,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_3
MOD_SEL0_2
MOD_SEL0_1
MOD_SEL0_0 }
MOD_SEL0_0 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
1, 1, 1, 1, 1, 1, 2, 4, 4,
4, 4, 4, 4) {
GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
GROUP(
MOD_SEL1_31
MOD_SEL1_30
MOD_SEL1_29
@ -2816,7 +2818,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* RESERVED 7, 6, 5, 4 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* RESERVED 3, 2, 1, 0 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ },
};
@ -2833,6 +2835,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
return bit;
}
enum ioctrl_regs {
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
};
@ -2852,6 +2863,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

152
drivers/pinctrl/sh-pfc/pfc-sh7203.c
View File

@ -1073,7 +1073,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
{ PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -1089,9 +1089,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
0, 0 }
0, 0 ))
},
{ PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4) {
{ PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1099,9 +1099,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4) {
{ PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4, GROUP(
PB11MD_0, PB11MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1112,9 +1112,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PB8MD_00, PB8MD_01, PB8MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4) {
{ PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4, GROUP(
PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1125,9 +1125,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4) {
{ PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4, GROUP(
PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1138,9 +1138,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4) {
{ PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1148,9 +1148,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1) {
{ PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1, GROUP(
0, 0,
PC14_IN, PC14_OUT,
PC13_IN, PC13_OUT,
@ -1166,9 +1166,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC3_IN, PC3_OUT,
PC2_IN, PC2_OUT,
PC1_IN, PC1_OUT,
PC0_IN, PC0_OUT }
PC0_IN, PC0_OUT ))
},
{ PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4) {
{ PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC14MD_0, PC14MD_1,
@ -1178,9 +1178,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC12MD_0, PC12MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4) {
{ PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4, GROUP(
PC11MD_00, PC11MD_01, PC11MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1191,9 +1191,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC8MD_0, PC8MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4) {
{ PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4, GROUP(
PC7MD_0, PC7MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1204,9 +1204,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC4MD_0, PC4MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4) {
{ PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4, GROUP(
PC3MD_0, PC3MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1217,9 +1217,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC0MD_00, PC0MD_01, PC0MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1) {
{ PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1, GROUP(
PD15_IN, PD15_OUT,
PD14_IN, PD14_OUT,
PD13_IN, PD13_OUT,
@ -1235,9 +1235,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD3_IN, PD3_OUT,
PD2_IN, PD2_OUT,
PD1_IN, PD1_OUT,
PD0_IN, PD0_OUT }
PD0_IN, PD0_OUT ))
},
{ PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4) {
{ PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4, GROUP(
PD15MD_000, PD15MD_001, PD15MD_010, 0,
PD15MD_100, PD15MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1252,9 +1252,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD12MD_000, PD12MD_001, PD12MD_010, 0,
PD12MD_100, PD12MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4) {
{ PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4, GROUP(
PD11MD_000, PD11MD_001, PD11MD_010, 0,
PD11MD_100, PD11MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1269,9 +1269,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD8MD_000, PD8MD_001, PD8MD_010, 0,
PD8MD_100, PD8MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4) {
{ PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4, GROUP(
PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011,
PD7MD_100, PD7MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1286,9 +1286,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011,
PD4MD_100, PD4MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4) {
{ PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4, GROUP(
PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011,
PD3MD_100, PD3MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1303,9 +1303,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011,
PD0MD_100, PD0MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1) {
{ PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1, GROUP(
PE15_IN, PE15_OUT,
PE14_IN, PE14_OUT,
PE13_IN, PE13_OUT,
@ -1321,9 +1321,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE3_IN, PE3_OUT,
PE2_IN, PE2_OUT,
PE1_IN, PE1_OUT,
PE0_IN, PE0_OUT }
PE0_IN, PE0_OUT ))
},
{ PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4) {
{ PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4, GROUP(
PE15MD_00, PE15MD_01, 0, PE15MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1334,9 +1334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PE12MD_00, 0, 0, PE12MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4) {
{ PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4, GROUP(
PE11MD_000, PE11MD_001, PE11MD_010, 0,
PE11MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1349,9 +1349,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4) {
{ PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4, GROUP(
PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011,
PE7MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1366,9 +1366,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011,
PE4MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4) {
{ PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4, GROUP(
PE3MD_00, PE3MD_01, 0, PE3MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1380,9 +1380,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE0MD_000, PE0MD_001, 0, PE0MD_011,
PE0MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1) {
{ PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1, GROUP(
0, 0,
PF30_IN, PF30_OUT,
PF29_IN, PF29_OUT,
@ -1398,9 +1398,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF19_IN, PF19_OUT,
PF18_IN, PF18_OUT,
PF17_IN, PF17_OUT,
PF16_IN, PF16_OUT }
PF16_IN, PF16_OUT ))
},
{ PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1) {
{ PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1, GROUP(
PF15_IN, PF15_OUT,
PF14_IN, PF14_OUT,
PF13_IN, PF13_OUT,
@ -1416,9 +1416,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF3_IN, PF3_OUT,
PF2_IN, PF2_OUT,
PF1_IN, PF1_OUT,
PF0_IN, PF0_OUT }
PF0_IN, PF0_OUT ))
},
{ PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4) {
{ PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF30MD_0, PF30MD_1,
@ -1428,9 +1428,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF28MD_0, PF28MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4) {
{ PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4, GROUP(
PF27MD_0, PF27MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1441,9 +1441,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF24MD_0, PF24MD_1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4) {
{ PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4, GROUP(
PF23MD_00, PF23MD_01, PF23MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1454,9 +1454,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF20MD_00, PF20MD_01, PF20MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4) {
{ PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4, GROUP(
PF19MD_00, PF19MD_01, PF19MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1467,9 +1467,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF16MD_00, PF16MD_01, PF16MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4) {
{ PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4, GROUP(
PF15MD_00, PF15MD_01, PF15MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1480,9 +1480,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF12MD_00, PF12MD_01, PF12MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4) {
{ PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4, GROUP(
PF11MD_00, PF11MD_01, PF11MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1493,9 +1493,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF8MD_00, PF8MD_01, PF8MD_10, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4) {
{ PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4, GROUP(
PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1506,9 +1506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4) {
{ PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4, GROUP(
PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1519,53 +1519,53 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
},
{ PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16) {
{ PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16, GROUP(
0, 0, 0, PB12_DATA,
PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
},
{ PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16) {
{ PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16, GROUP(
0, PC14_DATA, PC13_DATA, PC12_DATA,
PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
},
{ PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16) {
{ PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16, GROUP(
PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
},
{ PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16) {
{ PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16, GROUP(
PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
},
{ PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16) {
{ PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16, GROUP(
0, PF30_DATA, PF29_DATA, PF28_DATA,
PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA }
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
},
{ PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16) {
{ PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16, GROUP(
PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
},
{ },
};

232
drivers/pinctrl/sh-pfc/pfc-sh7264.c
View File

@ -1466,17 +1466,17 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PA3_IN, PA3_OUT,
PA2_IN, PA2_OUT,
PA1_IN, PA1_OUT,
PA0_IN, PA0_OUT }
PA0_IN, PA0_OUT ))
},
{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
@ -1484,10 +1484,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB20MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
{ PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4, GROUP(
0, PB19MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB18MD_01, 0, 0, 0, 0, 0, 0,
@ -1495,9 +1495,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PB17MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB16MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
{ PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4, GROUP(
0, PB15MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB14MD_01, 0, 0, 0, 0, 0, 0,
@ -1505,9 +1505,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PB13MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB12MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
{ PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4, GROUP(
0, PB11MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB10MD_01, 0, 0, 0, 0, 0, 0,
@ -1515,9 +1515,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PB9MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB8MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
{ PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4, GROUP(
0, PB7MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB6MD_01, 0, 0, 0, 0, 0, 0,
@ -1525,9 +1525,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PB5MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB4MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
0, PB3MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB2MD_1, 0, 0, 0, 0, 0, 0,
@ -1535,10 +1535,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PB1MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
@ -1548,10 +1548,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB19_IN, PB19_OUT,
PB18_IN, PB18_OUT,
PB17_IN, PB17_OUT,
PB16_IN, PB16_OUT }
PB16_IN, PB16_OUT ))
},
{ PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
{ PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1, GROUP(
PB15_IN, PB15_OUT,
PB14_IN, PB14_OUT,
PB13_IN, PB13_OUT,
@ -1567,10 +1567,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB3_IN, PB3_OUT,
PB2_IN, PB2_OUT,
PB1_IN, PB1_OUT,
0, 0 }
0, 0 ))
},
{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
@ -1578,9 +1578,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) {
{ PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4, GROUP(
PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0,
@ -1588,9 +1588,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) {
{ PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4, GROUP(
PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0,
@ -1598,10 +1598,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC10_IN, PC10_OUT,
PC9_IN, PC9_OUT,
@ -1614,10 +1614,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC2_IN, PC2_OUT,
PC1_IN, PC1_OUT,
PC0_IN, PC0_OUT
}
))
},
{ PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) {
{ PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4, GROUP(
0, PD15MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD14MD_01, 0, 0, 0, 0, 0, 0,
@ -1625,9 +1625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PD13MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD12MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) {
{ PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4, GROUP(
0, PD11MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD10MD_01, 0, 0, 0, 0, 0, 0,
@ -1635,9 +1635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PD9MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD8MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) {
{ PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4, GROUP(
0, PD7MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD6MD_01, 0, 0, 0, 0, 0, 0,
@ -1645,9 +1645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PD5MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD4MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) {
{ PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4, GROUP(
0, PD3MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD2MD_01, 0, 0, 0, 0, 0, 0,
@ -1655,10 +1655,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, PD1MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD0MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) {
{ PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1, GROUP(
PD15_IN, PD15_OUT,
PD14_IN, PD14_OUT,
PD13_IN, PD13_OUT,
@ -1674,10 +1674,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD3_IN, PD3_OUT,
PD2_IN, PD2_OUT,
PD1_IN, PD1_OUT,
PD0_IN, PD0_OUT }
PD0_IN, PD0_OUT ))
},
{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) {
{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1685,10 +1685,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) {
{ PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4, GROUP(
PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0,
@ -1697,10 +1697,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE1MD_100, PE1MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) {
{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
@ -1709,19 +1709,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE3_IN, PE3_OUT,
PE2_IN, PE2_OUT,
PE1_IN, PE1_OUT,
PE0_IN, PE0_OUT }
PE0_IN, PE0_OUT ))
},
{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF12MD_000, PF12MD_001, 0, PF12MD_011,
PF12MD_100, PF12MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) {
{ PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4, GROUP(
PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
PF11MD_100, PF11MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1732,10 +1732,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF9MD_100, PF9MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) {
{ PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4, GROUP(
PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
PF7MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1747,10 +1747,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
PF4MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) {
{ PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4, GROUP(
PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
PF3MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1762,10 +1762,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
PF0MD_100, PF0MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {
{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1, GROUP(
0, 0, 0, 0, 0, 0,
PF12_IN, PF12_OUT,
PF11_IN, PF11_OUT,
@ -1779,10 +1779,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF3_IN, PF3_OUT,
PF2_IN, PF2_OUT,
PF1_IN, PF1_OUT,
PF0_IN, PF0_OUT }
PF0_IN, PF0_OUT ))
},
{ PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4) {
{ PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1791,10 +1791,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
PG0MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) {
{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1802,10 +1802,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) {
{ PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4, GROUP(
PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0,
@ -1814,10 +1814,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
PG20MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) {
{ PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4, GROUP(
PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
PG19MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1829,10 +1829,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
PG16MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) {
{ PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4, GROUP(
PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
PG15MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1844,9 +1844,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG12MD_000, PG12MD_001, PG12MD_010, 0,
PG12MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) {
{ PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4, GROUP(
PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
PG11MD_100, PG11MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1858,10 +1858,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
PG8MD_100, PG8MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) {
{ PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4, GROUP(
PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0,
@ -1869,9 +1869,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) {
{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
@ -1879,9 +1879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) {
{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
PG24_IN, PG24_OUT,
@ -1892,10 +1892,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG19_IN, PG19_OUT,
PG18_IN, PG18_OUT,
PG17_IN, PG17_OUT,
PG16_IN, PG16_OUT }
PG16_IN, PG16_OUT ))
},
{ PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) {
{ PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1, GROUP(
PG15_IN, PG15_OUT,
PG14_IN, PG14_OUT,
PG13_IN, PG13_OUT,
@ -1912,10 +1912,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG2_IN, PG2_OUT,
PG1_IN, PG1_OUT,
PG0_IN, PG0_OUT
}
))
},
{ PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) {
{ PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4, GROUP(
PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0,
@ -1923,10 +1923,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) {
{ PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4, GROUP(
PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0,
@ -1934,10 +1934,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) {
{ PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4, GROUP(
PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0,
@ -1945,9 +1945,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) {
{ PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4, GROUP(
PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0,
@ -1955,9 +1955,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) {
{ PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4, GROUP(
PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
@ -1968,9 +1968,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
PJ0MD_100, PJ0MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
0, 0, 0, 0, 0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) {
{ PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PJ11_IN, PJ11_OUT,
PJ10_IN, PJ10_OUT,
@ -1983,10 +1983,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ3_IN, PJ3_OUT,
PJ2_IN, PJ2_OUT,
PJ1_IN, PJ1_OUT,
PJ0_IN, PJ0_OUT }
PJ0_IN, PJ0_OUT ))
},
{ PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4) {
{ PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4, GROUP(
PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0,
@ -1994,10 +1994,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4) {
{ PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4, GROUP(
PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK6MD_00, PK6MD_01, PK6MD_10, 0, 0, 0, 0, 0,
@ -2005,9 +2005,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4) {
{ PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4, GROUP(
PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0,
@ -2015,10 +2015,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1) {
{ PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PJ11_IN, PJ11_OUT,
PJ10_IN, PJ10_OUT,
@ -2031,85 +2031,85 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ3_IN, PJ3_OUT,
PJ2_IN, PJ2_OUT,
PJ1_IN, PJ1_OUT,
PJ0_IN, PJ0_OUT }
PJ0_IN, PJ0_OUT ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, PA3_DATA,
0, 0, 0, 0, 0, 0, 0, PA2_DATA }
0, 0, 0, 0, 0, 0, 0, PA2_DATA ))
},
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, PB22_DATA, PB21_DATA, PB20_DATA,
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
},
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, 0 }
PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
},
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
0, 0, 0, 0,
0, PC10_DATA, PC9_DATA, PC8_DATA,
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, PE5_DATA, PE4_DATA,
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
0, 0, 0, PF12_DATA,
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, PG24_DATA,
PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
},
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
},
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
0, 0, 0, PJ12_DATA,
PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
},
{ PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) {
{ PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16, GROUP(
0, 0, 0, PK12_DATA,
PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
},
{ }
};

252
drivers/pinctrl/sh-pfc/pfc-sh7269.c
View File

@ -1951,13 +1951,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* where Field_Width is 1 for single mode registers or 4 for upto 16
mode registers and modes are described in assending order [0..16] */
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, PA1_IN, PA1_OUT,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT }
0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT ))
},
{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011,
@ -1969,9 +1969,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011,
PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
{ PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4, GROUP(
PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011,
PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -1986,9 +1986,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011,
PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
{ PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4, GROUP(
PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011,
PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2002,9 +2002,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
{ PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4, GROUP(
PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2015,9 +2015,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
{ PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4, GROUP(
PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2028,9 +2028,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4, GROUP(
PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2040,10 +2040,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
@ -2053,9 +2053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB19_IN, PB19_OUT,
PB18_IN, PB18_OUT,
PB17_IN, PB17_OUT,
PB16_IN, PB16_OUT }
PB16_IN, PB16_OUT ))
},
{ PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
{ PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1, GROUP(
PB15_IN, PB15_OUT,
PB14_IN, PB14_OUT,
PB13_IN, PB13_OUT,
@ -2071,10 +2071,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB3_IN, PB3_OUT,
PB2_IN, PB2_OUT,
PB1_IN, PB1_OUT,
0, 0 }
0, 0 ))
},
{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -2083,9 +2083,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011,
PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) {
{ PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4, GROUP(
PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011,
PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2099,9 +2099,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) {
{ PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4, GROUP(
PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2112,10 +2112,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC8_IN, PC8_OUT,
PC7_IN, PC7_OUT,
@ -2125,10 +2125,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC3_IN, PC3_OUT,
PC2_IN, PC2_OUT,
PC1_IN, PC1_OUT,
PC0_IN, PC0_OUT }
PC0_IN, PC0_OUT ))
},
{ PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) {
{ PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4, GROUP(
PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2139,9 +2139,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) {
{ PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4, GROUP(
PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2152,9 +2152,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) {
{ PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4, GROUP(
PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2165,9 +2165,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) {
{ PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4, GROUP(
PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2178,10 +2178,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) {
{ PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1, GROUP(
PD15_IN, PD15_OUT,
PD14_IN, PD14_OUT,
PD13_IN, PD13_OUT,
@ -2197,10 +2197,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD3_IN, PD3_OUT,
PD2_IN, PD2_OUT,
PD1_IN, PD1_OUT,
PD0_IN, PD0_OUT }
PD0_IN, PD0_OUT ))
},
{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) {
{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4, GROUP(
PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2211,9 +2211,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) {
{ PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4, GROUP(
PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011,
PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2227,9 +2227,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) {
{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE7_IN, PE7_OUT,
@ -2239,10 +2239,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE3_IN, PE3_OUT,
PE2_IN, PE2_OUT,
PE1_IN, PE1_OUT,
PE0_IN, PE0_OUT }
PE0_IN, PE0_OUT ))
},
{ PINMUX_CFG_REG("PFCR6", 0xfffe38a2, 16, 4) {
{ PINMUX_CFG_REG("PFCR6", 0xfffe38a2, 16, 4, GROUP(
PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011,
PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2257,9 +2257,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011,
PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR5", 0xfffe38a4, 16, 4) {
{ PINMUX_CFG_REG("PFCR5", 0xfffe38a4, 16, 4, GROUP(
PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011,
PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2274,9 +2274,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011,
PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4) {
{ PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -2285,9 +2285,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011,
PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011,
@ -2300,9 +2300,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) {
{ PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4, GROUP(
PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011,
PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) {
{ PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4, GROUP(
PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2334,9 +2334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) {
{ PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4, GROUP(
PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2351,10 +2351,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1) {
{ PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF23_IN, PF23_OUT,
@ -2364,9 +2364,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF19_IN, PF19_OUT,
PF18_IN, PF18_OUT,
PF17_IN, PF17_OUT,
PF16_IN, PF16_OUT }
PF16_IN, PF16_OUT ))
},
{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {
{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1, GROUP(
PF15_IN, PF15_OUT,
PF14_IN, PF14_OUT,
PF13_IN, PF13_OUT,
@ -2382,10 +2382,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF3_IN, PF3_OUT,
PF2_IN, PF2_OUT,
PF1_IN, PF1_OUT,
PF0_IN, PF0_OUT }
PF0_IN, PF0_OUT ))
},
{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) {
{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4, GROUP(
PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2396,9 +2396,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) {
{ PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4, GROUP(
PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011,
PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2413,9 +2413,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) {
{ PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4, GROUP(
PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2428,9 +2428,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) {
{ PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4, GROUP(
PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2441,9 +2441,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) {
{ PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4, GROUP(
PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2458,10 +2458,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) {
{ PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4, GROUP(
PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011,
PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2476,9 +2476,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011,
PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) {
{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4, GROUP(
PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011,
PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2493,10 +2493,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) {
{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PG27_IN, PG27_OUT,
PG26_IN, PG26_OUT,
@ -2509,9 +2509,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG19_IN, PG19_OUT,
PG18_IN, PG18_OUT,
PG17_IN, PG17_OUT,
PG16_IN, PG16_OUT }
PG16_IN, PG16_OUT ))
},
{ PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) {
{ PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1, GROUP(
PG15_IN, PG15_OUT,
PG14_IN, PG14_OUT,
PG13_IN, PG13_OUT,
@ -2527,10 +2527,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG3_IN, PG3_OUT,
PG2_IN, PG2_OUT,
PG1_IN, PG1_OUT,
PG0_IN, PG0_OUT }
PG0_IN, PG0_OUT ))
},
{ PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) {
{ PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4, GROUP(
PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2541,10 +2541,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) {
{ PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4, GROUP(
PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2555,10 +2555,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR7", 0xfffe3900, 16, 4) {
{ PINMUX_CFG_REG("PJCR7", 0xfffe3900, 16, 4, GROUP(
PJ31MD_0, PJ31MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2572,9 +2572,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011,
PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR6", 0xfffe3902, 16, 4) {
{ PINMUX_CFG_REG("PJCR6", 0xfffe3902, 16, 4, GROUP(
PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011,
PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2589,9 +2589,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011,
PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR5", 0xfffe3904, 16, 4) {
{ PINMUX_CFG_REG("PJCR5", 0xfffe3904, 16, 4, GROUP(
PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011,
PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2606,9 +2606,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011,
PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR4", 0xfffe3906, 16, 4) {
{ PINMUX_CFG_REG("PJCR4", 0xfffe3906, 16, 4, GROUP(
PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011,
PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2623,9 +2623,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011,
PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR3", 0xfffe3908, 16, 4) {
{ PINMUX_CFG_REG("PJCR3", 0xfffe3908, 16, 4, GROUP(
PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011,
PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2640,9 +2640,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011,
PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) {
{ PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4, GROUP(
PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011,
PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2657,9 +2657,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011,
PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) {
{ PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4, GROUP(
PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011,
PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2674,9 +2674,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011,
PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) {
{ PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4, GROUP(
PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011,
PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2691,10 +2691,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
0, 0, 0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PJIOR1", 0xfffe3910, 16, 1) {
{ PINMUX_CFG_REG("PJIOR1", 0xfffe3910, 16, 1, GROUP(
PJ31_IN, PJ31_OUT,
PJ30_IN, PJ30_OUT,
PJ29_IN, PJ29_OUT,
@ -2710,9 +2710,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ19_IN, PJ19_OUT,
PJ18_IN, PJ18_OUT,
PJ17_IN, PJ17_OUT,
PJ16_IN, PJ16_OUT }
PJ16_IN, PJ16_OUT ))
},
{ PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) {
{ PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1, GROUP(
PJ15_IN, PJ15_OUT,
PJ14_IN, PJ14_OUT,
PJ13_IN, PJ13_OUT,
@ -2728,86 +2728,86 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ3_IN, PJ3_OUT,
PJ2_IN, PJ2_OUT,
PJ1_IN, PJ1_OUT,
PJ0_IN, PJ0_OUT }
PJ0_IN, PJ0_OUT ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
0, 0, 0, 0, 0, 0, 0, PA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
0, PB22_DATA, PB21_DATA, PB20_DATA,
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA ))
},
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16, GROUP(
PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, 0 }
PB3_DATA, PB2_DATA, PB1_DATA, 0 ))
},
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16, GROUP(
0, 0, 0, 0,
0, 0, 0, PC8_DATA,
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16, GROUP(
PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16) {
{ PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA }
PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA ))
},
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16, GROUP(
PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16, GROUP(
0, 0, 0, 0,
PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA,
PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA ))
},
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16, GROUP(
PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
},
{ PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16) {
{ PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16, GROUP(
PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA,
PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA,
PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA,
PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA }
PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA ))
},
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16, GROUP(
PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA,
PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
},
{ }

52
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@ -3971,7 +3971,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(308, 0xe6052134), /* PORT308CR */
PORTCR(309, 0xe6052135), /* PORT309CR */
{ PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
{ PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4004,9 +4004,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
}
))
},
{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -4039,9 +4039,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
0, 0,
0, 0,
}
))
},
{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
0, 0,
0, 0,
MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
@ -4074,13 +4074,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
0, 0,
}
))
},
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
@ -4088,9 +4088,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
},
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
@ -4098,9 +4098,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
},
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
@ -4108,9 +4108,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
},
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
{ PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
@ -4118,9 +4118,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
},
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
@ -4128,9 +4128,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
},
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -4138,9 +4138,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, PORT164_DATA,
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
},
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
{ PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
@ -4148,9 +4148,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
},
{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
@ -4158,9 +4158,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
},
{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
0, 0, 0, 0,
0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
@ -4168,9 +4168,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
},
{ PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
{ PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, PORT309_DATA, PORT308_DATA,
@ -4178,7 +4178,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
},
{ },
};

144
drivers/pinctrl/sh-pfc/pfc-sh7720.c
View File

@ -925,7 +925,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
PTA7_FN, PTA7_OUT, 0, PTA7_IN,
PTA6_FN, PTA6_OUT, 0, PTA6_IN,
PTA5_FN, PTA5_OUT, 0, PTA5_IN,
@ -933,9 +933,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTA3_FN, PTA3_OUT, 0, PTA3_IN,
PTA2_FN, PTA2_OUT, 0, PTA2_IN,
PTA1_FN, PTA1_OUT, 0, PTA1_IN,
PTA0_FN, PTA0_OUT, 0, PTA0_IN }
PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
PTB7_FN, PTB7_OUT, 0, PTB7_IN,
PTB6_FN, PTB6_OUT, 0, PTB6_IN,
PTB5_FN, PTB5_OUT, 0, PTB5_IN,
@ -943,9 +943,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTB3_FN, PTB3_OUT, 0, PTB3_IN,
PTB2_FN, PTB2_OUT, 0, PTB2_IN,
PTB1_FN, PTB1_OUT, 0, PTB1_IN,
PTB0_FN, PTB0_OUT, 0, PTB0_IN }
PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
},
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
PTC7_FN, PTC7_OUT, 0, PTC7_IN,
PTC6_FN, PTC6_OUT, 0, PTC6_IN,
PTC5_FN, PTC5_OUT, 0, PTC5_IN,
@ -953,9 +953,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTC3_FN, PTC3_OUT, 0, PTC3_IN,
PTC2_FN, PTC2_OUT, 0, PTC2_IN,
PTC1_FN, PTC1_OUT, 0, PTC1_IN,
PTC0_FN, PTC0_OUT, 0, PTC0_IN }
PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
},
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
PTD7_FN, PTD7_OUT, 0, PTD7_IN,
PTD6_FN, PTD6_OUT, 0, PTD6_IN,
PTD5_FN, PTD5_OUT, 0, PTD5_IN,
@ -963,9 +963,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTD3_FN, PTD3_OUT, 0, PTD3_IN,
PTD2_FN, PTD2_OUT, 0, PTD2_IN,
PTD1_FN, PTD1_OUT, 0, PTD1_IN,
PTD0_FN, PTD0_OUT, 0, PTD0_IN }
PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
},
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
0, 0, 0, 0,
PTE6_FN, 0, 0, PTE6_IN,
PTE5_FN, 0, 0, PTE5_IN,
@ -973,9 +973,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTE3_FN, PTE3_OUT, 0, PTE3_IN,
PTE2_FN, PTE2_OUT, 0, PTE2_IN,
PTE1_FN, PTE1_OUT, 0, PTE1_IN,
PTE0_FN, PTE0_OUT, 0, PTE0_IN }
PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
},
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
0, 0, 0, 0,
PTF6_FN, 0, 0, PTF6_IN,
PTF5_FN, 0, 0, PTF5_IN,
@ -983,9 +983,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTF3_FN, 0, 0, PTF3_IN,
PTF2_FN, 0, 0, PTF2_IN,
PTF1_FN, 0, 0, PTF1_IN,
PTF0_FN, 0, 0, PTF0_IN }
PTF0_FN, 0, 0, PTF0_IN ))
},
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
0, 0, 0, 0,
PTG6_FN, PTG6_OUT, 0, PTG6_IN,
PTG5_FN, PTG5_OUT, 0, PTG5_IN,
@ -993,9 +993,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTG3_FN, PTG3_OUT, 0, PTG3_IN,
PTG2_FN, PTG2_OUT, 0, PTG2_IN,
PTG1_FN, PTG1_OUT, 0, PTG1_IN,
PTG0_FN, PTG0_OUT, 0, PTG0_IN }
PTG0_FN, PTG0_OUT, 0, PTG0_IN ))
},
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
0, 0, 0, 0,
PTH6_FN, PTH6_OUT, 0, PTH6_IN,
PTH5_FN, PTH5_OUT, 0, PTH5_IN,
@ -1003,9 +1003,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTH3_FN, PTH3_OUT, 0, PTH3_IN,
PTH2_FN, PTH2_OUT, 0, PTH2_IN,
PTH1_FN, PTH1_OUT, 0, PTH1_IN,
PTH0_FN, PTH0_OUT, 0, PTH0_IN }
PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
},
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
0, 0, 0, 0,
PTJ6_FN, PTJ6_OUT, 0, PTJ6_IN,
PTJ5_FN, PTJ5_OUT, 0, PTJ5_IN,
@ -1013,9 +1013,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN }
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
},
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1023,9 +1023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTK3_FN, PTK3_OUT, 0, PTK3_IN,
PTK2_FN, PTK2_OUT, 0, PTK2_IN,
PTK1_FN, PTK1_OUT, 0, PTK1_IN,
PTK0_FN, PTK0_OUT, 0, PTK0_IN }
PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
},
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
PTL7_FN, PTL7_OUT, 0, PTL7_IN,
PTL6_FN, PTL6_OUT, 0, PTL6_IN,
PTL5_FN, PTL5_OUT, 0, PTL5_IN,
@ -1033,9 +1033,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTL3_FN, PTL3_OUT, 0, PTL3_IN,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
PTM7_FN, PTM7_OUT, 0, PTM7_IN,
PTM6_FN, PTM6_OUT, 0, PTM6_IN,
PTM5_FN, PTM5_OUT, 0, PTM5_IN,
@ -1043,9 +1043,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTM3_FN, PTM3_OUT, 0, PTM3_IN,
PTM2_FN, PTM2_OUT, 0, PTM2_IN,
PTM1_FN, PTM1_OUT, 0, PTM1_IN,
PTM0_FN, PTM0_OUT, 0, PTM0_IN }
PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
},
{ PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) {
{ PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1053,9 +1053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTP3_FN, PTP3_OUT, 0, PTP3_IN,
PTP2_FN, PTP2_OUT, 0, PTP2_IN,
PTP1_FN, PTP1_OUT, 0, PTP1_IN,
PTP0_FN, PTP0_OUT, 0, PTP0_IN }
PTP0_FN, PTP0_OUT, 0, PTP0_IN ))
},
{ PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) {
{ PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2, GROUP(
PTR7_FN, PTR7_OUT, 0, PTR7_IN,
PTR6_FN, PTR6_OUT, 0, PTR6_IN,
PTR5_FN, PTR5_OUT, 0, PTR5_IN,
@ -1063,9 +1063,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTR3_FN, PTR3_OUT, 0, PTR3_IN,
PTR2_FN, PTR2_OUT, 0, PTR2_IN,
PTR1_FN, PTR1_OUT, 0, PTR1_IN,
PTR0_FN, PTR0_OUT, 0, PTR0_IN }
PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
},
{ PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) {
{ PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1073,9 +1073,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTS3_FN, PTS3_OUT, 0, PTS3_IN,
PTS2_FN, PTS2_OUT, 0, PTS2_IN,
PTS1_FN, PTS1_OUT, 0, PTS1_IN,
PTS0_FN, PTS0_OUT, 0, PTS0_IN }
PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
},
{ PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) {
{ PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1083,9 +1083,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTT3_FN, PTT3_OUT, 0, PTT3_IN,
PTT2_FN, PTT2_OUT, 0, PTT2_IN,
PTT1_FN, PTT1_OUT, 0, PTT1_IN,
PTT0_FN, PTT0_OUT, 0, PTT0_IN }
PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
},
{ PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) {
{ PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1093,9 +1093,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTU3_FN, PTU3_OUT, 0, PTU3_IN,
PTU2_FN, PTU2_OUT, 0, PTU2_IN,
PTU1_FN, PTU1_OUT, 0, PTU1_IN,
PTU0_FN, PTU0_OUT, 0, PTU0_IN }
PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
},
{ PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) {
{ PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1103,83 +1103,83 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTV3_FN, PTV3_OUT, 0, PTV3_IN,
PTV2_FN, PTV2_OUT, 0, PTV2_IN,
PTV1_FN, PTV1_OUT, 0, PTV1_IN,
PTV0_FN, PTV0_OUT, 0, PTV0_IN }
PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
{ PINMUX_DATA_REG("PADR", 0xa4050140, 8, GROUP(
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xa4050142, 8) {
{ PINMUX_DATA_REG("PBDR", 0xa4050142, 8, GROUP(
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xa4050144, 8) {
{ PINMUX_DATA_REG("PCDR", 0xa4050144, 8, GROUP(
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xa4050148, 8) {
{ PINMUX_DATA_REG("PEDR", 0xa4050148, 8, GROUP(
0, PTE6_DATA, PTE5_DATA, PTE4_DATA,
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR", 0xa405014a, 8) {
{ PINMUX_DATA_REG("PFDR", 0xa405014a, 8, GROUP(
0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xa405014c, 8) {
{ PINMUX_DATA_REG("PGDR", 0xa405014c, 8, GROUP(
0, PTG6_DATA, PTG5_DATA, PTG4_DATA,
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
},
{ PINMUX_DATA_REG("PHDR", 0xa405014e, 8) {
{ PINMUX_DATA_REG("PHDR", 0xa405014e, 8, GROUP(
0, PTH6_DATA, PTH5_DATA, PTH4_DATA,
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xa4050150, 8) {
{ PINMUX_DATA_REG("PJDR", 0xa4050150, 8, GROUP(
0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
},
{ PINMUX_DATA_REG("PKDR", 0xa4050152, 8) {
{ PINMUX_DATA_REG("PKDR", 0xa4050152, 8, GROUP(
0, 0, 0, 0,
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
},
{ PINMUX_DATA_REG("PLDR", 0xa4050154, 8) {
{ PINMUX_DATA_REG("PLDR", 0xa4050154, 8, GROUP(
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
PTL3_DATA, 0, 0, 0 }
PTL3_DATA, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PMDR", 0xa4050156, 8) {
{ PINMUX_DATA_REG("PMDR", 0xa4050156, 8, GROUP(
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
},
{ PINMUX_DATA_REG("PPDR", 0xa4050158, 8) {
{ PINMUX_DATA_REG("PPDR", 0xa4050158, 8, GROUP(
0, 0, 0, PTP4_DATA,
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
},
{ PINMUX_DATA_REG("PRDR", 0xa405015a, 8) {
{ PINMUX_DATA_REG("PRDR", 0xa405015a, 8, GROUP(
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
},
{ PINMUX_DATA_REG("PSDR", 0xa405015c, 8) {
{ PINMUX_DATA_REG("PSDR", 0xa405015c, 8, GROUP(
0, 0, 0, PTS4_DATA,
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
},
{ PINMUX_DATA_REG("PTDR", 0xa405015e, 8) {
{ PINMUX_DATA_REG("PTDR", 0xa405015e, 8, GROUP(
0, 0, 0, PTT4_DATA,
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
},
{ PINMUX_DATA_REG("PUDR", 0xa4050160, 8) {
{ PINMUX_DATA_REG("PUDR", 0xa4050160, 8, GROUP(
0, 0, 0, PTU4_DATA,
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
},
{ PINMUX_DATA_REG("PVDR", 0xa4050162, 8) {
{ PINMUX_DATA_REG("PVDR", 0xa4050162, 8, GROUP(
0, 0, 0, PTV4_DATA,
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
},
{ },
};

220
drivers/pinctrl/sh-pfc/pfc-sh7722.c
View File

@ -1237,7 +1237,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN,
VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN,
VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN,
@ -1245,9 +1245,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
VIO_D3, 0, 0, PTA3_IN,
VIO_D2, 0, 0, PTA2_IN,
VIO_D1, 0, 0, PTA1_IN,
VIO_D0_LCDLCLK, 0, 0, PTA0_IN }
VIO_D0_LCDLCLK, 0, 0, PTA0_IN ))
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
HPD55, PTB7_OUT, 0, PTB7_IN,
HPD54, PTB6_OUT, 0, PTB6_IN,
HPD53, PTB5_OUT, 0, PTB5_IN,
@ -1255,9 +1255,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
HPD51, PTB3_OUT, 0, PTB3_IN,
HPD50, PTB2_OUT, 0, PTB2_IN,
HPD49, PTB1_OUT, 0, PTB1_IN,
HPD48, PTB0_OUT, 0, PTB0_IN }
HPD48, PTB0_OUT, 0, PTB0_IN ))
},
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
0, 0, 0, PTC7_IN,
0, 0, 0, 0,
IOIS16, 0, 0, PTC5_IN,
@ -1265,9 +1265,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
HPDQM6, PTC3_OUT, 0, PTC3_IN,
HPDQM5, PTC2_OUT, 0, PTC2_IN,
0, 0, 0, 0,
HPDQM4, PTC0_OUT, 0, PTC0_IN }
HPDQM4, PTC0_OUT, 0, PTC0_IN ))
},
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
SDHICD, 0, 0, PTD7_IN,
SDHIWP, PTD6_OUT, 0, PTD6_IN,
SDHID3, PTD5_OUT, 0, PTD5_IN,
@ -1275,9 +1275,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
SDHID1, PTD3_OUT, 0, PTD3_IN,
SDHID0, PTD2_OUT, 0, PTD2_IN,
SDHICMD, PTD1_OUT, 0, PTD1_IN,
SDHICLK, PTD0_OUT, 0, 0 }
SDHICLK, PTD0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
A25, PTE7_OUT, 0, PTE7_IN,
A24, PTE6_OUT, 0, PTE6_IN,
A23, PTE5_OUT, 0, PTE5_IN,
@ -1285,9 +1285,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
IRQ5, PTE1_OUT, 0, PTE1_IN,
IRQ4_BS, PTE0_OUT, 0, PTE0_IN }
IRQ4_BS, PTE0_OUT, 0, PTE0_IN ))
},
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
0, 0, 0, 0,
PTF6, PTF6_OUT, 0, PTF6_IN,
SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN,
@ -1295,9 +1295,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN,
SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN,
SIORXD_SIUBISLD, 0, 0, PTF1_IN,
SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 }
SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1305,9 +1305,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
AUDATA3, PTG3_OUT, 0, 0,
AUDATA2, PTG2_OUT, 0, 0,
AUDATA1, PTG1_OUT, 0, 0,
AUDATA0, PTG0_OUT, 0, 0 }
AUDATA0, PTG0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0,
LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN,
LCDVSYN, PTH5_OUT, 0, PTH5_IN,
@ -1315,9 +1315,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
LCDHSYN_LCDCS, PTH3_OUT, 0, 0,
LCDDON_LCDDON2, PTH2_OUT, 0, 0,
LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN,
LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN }
LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN ))
},
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
STATUS0, PTJ7_OUT, 0, 0,
0, PTJ6_OUT, 0, 0,
PDSTATUS, PTJ5_OUT, 0, 0,
@ -1325,9 +1325,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
IRQ1, PTJ1_OUT, 0, PTJ1_IN,
IRQ0, PTJ0_OUT, 0, PTJ0_IN }
IRQ0, PTJ0_OUT, 0, PTJ0_IN ))
},
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
0, 0, 0, 0,
SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN,
SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN,
@ -1335,9 +1335,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN,
SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN,
SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0,
PTK0, PTK0_OUT, 0, PTK0_IN }
PTK0, PTK0_OUT, 0, PTK0_IN ))
},
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN,
LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN,
LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN,
@ -1345,9 +1345,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN,
LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN,
LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN,
LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN }
LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN ))
},
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN,
LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN,
LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN,
@ -1355,9 +1355,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN,
LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN,
LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN,
LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN }
LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN ))
},
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
HPD63, PTN7_OUT, 0, PTN7_IN,
HPD62, PTN6_OUT, 0, PTN6_IN,
HPD61, PTN5_OUT, 0, PTN5_IN,
@ -1365,9 +1365,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
HPD59, PTN3_OUT, 0, PTN3_IN,
HPD58, PTN2_OUT, 0, PTN2_IN,
HPD57, PTN1_OUT, 0, PTN1_IN,
HPD56, PTN0_OUT, 0, PTN0_IN }
HPD56, PTN0_OUT, 0, PTN0_IN ))
},
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
0, 0, 0, 0,
SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0,
SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN,
@ -1375,9 +1375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN,
PTQ2, 0, 0, PTQ2_IN,
PTQ1, PTQ1_OUT, 0, 0,
PTQ0, PTQ0_OUT, 0, PTQ0_IN }
PTQ0, PTQ0_OUT, 0, PTQ0_IN ))
},
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1385,9 +1385,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
WAIT, 0, 0, PTR2_IN,
LCDDCK_LCDWR, PTR1_OUT, 0, 0,
LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 }
LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1395,9 +1395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN,
SCIF0_RXD, 0, 0, PTS1_IN,
SCIF0_TXD, PTS0_OUT, 0, 0 }
SCIF0_TXD, PTS0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1405,9 +1405,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FWE, PTT3_OUT, 0, PTT3_IN,
FSC, PTT2_OUT, 0, PTT2_IN,
DREQ0, 0, 0, PTT1_IN,
FCDE, PTT0_OUT, 0, 0 }
FCDE, PTT0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1415,9 +1415,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN,
NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN,
FRB_VIO_CLK2, 0, 0, PTU1_IN,
FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN }
FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN ))
},
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1425,9 +1425,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN,
NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN,
NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN,
NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN }
NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN ))
},
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
0, 0, 0, 0,
VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN,
VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0,
@ -1435,9 +1435,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN,
VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN,
VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN,
VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN }
VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN ))
},
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
0, 0, 0, 0,
CS6A_CE2B, PTX6_OUT, 0, PTX6_IN,
LCDD23, PTX5_OUT, 0, PTX5_IN,
@ -1445,9 +1445,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
LCDD21, PTX3_OUT, 0, PTX3_IN,
LCDD20, PTX2_OUT, 0, PTX2_IN,
LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN,
LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN }
LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN ))
},
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN,
@ -1455,9 +1455,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
KEYOUT3, PTY3_OUT, 0, PTY3_IN,
KEYOUT2, PTY2_OUT, 0, PTY2_IN,
KEYOUT1, PTY1_OUT, 0, 0,
KEYOUT0, PTY0_OUT, 0, PTY0_IN }
KEYOUT0, PTY0_OUT, 0, PTY0_IN ))
},
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
KEYIN4_IRQ7, 0, 0, PTZ5_IN,
@ -1465,9 +1465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
KEYIN2, 0, 0, PTZ3_IN,
KEYIN1, 0, 0, PTZ2_IN,
KEYIN0_IRQ6, 0, 0, PTZ1_IN,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
PSA15_KEYIN0, PSA15_IRQ6,
PSA14_KEYIN4, PSA14_IRQ7,
0, 0,
@ -1483,9 +1483,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
0, 0 }
0, 0 ))
},
{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
PSB15_SIOTXD, PSB15_SIUBOSLD,
PSB14_SIORXD, PSB14_SIUBISLD,
PSB13_SIOD, PSB13_SIUBILR,
@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSB3_SIOF0_SS1, PSB3_TS_SPSYNC,
PSB2_SIOF0_SS2, PSB2_SIM_RST,
PSB1_SIUMCKA, PSB1_SIOF1_MCK,
PSB0_SIUAOSLD, PSB0_SIOF1_TXD }
PSB0_SIUAOSLD, PSB0_SIOF1_TXD ))
},
{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
PSC15_SIUAISLD, PSC15_SIOF1_RXD,
PSC14_SIUAOBT, PSC14_SIOF1_SCK,
PSC13_SIUAOLR, PSC13_SIOF1_SYNC,
@ -1519,9 +1519,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
PSC0_NAF, PSC0_VIO }
PSC0_NAF, PSC0_VIO ))
},
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
0, 0,
0, 0,
PSD13_VIO, PSD13_SCIF2,
@ -1537,9 +1537,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
PSD2_LCDDON, PSD2_LCDDON2,
0, 0,
PSD0_LCDD19_LCDD0, PSD0_DV }
PSD0_LCDD19_LCDD0, PSD0_DV ))
},
{ PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
{ PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT,
@ -1555,9 +1555,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSE3_FLCTL, PSE3_VIO,
PSE2_NAF2, PSE2_VIO_D10,
PSE1_NAF1, PSE1_VIO_D9,
PSE0_NAF0, PSE0_VIO_D8 }
PSE0_NAF0, PSE0_VIO_D8 ))
},
{ PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1) {
{ PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1, GROUP(
0, 0,
HIZA14_KEYSC, HIZA14_HIZ,
0, 0,
@ -1573,9 +1573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
0, 0 }
0, 0 ))
},
{ PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1) {
{ PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -1591,9 +1591,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
HIZB1_VIO, HIZB1_HIZ,
HIZB0_VIO, HIZB0_HIZ }
HIZB0_VIO, HIZB0_HIZ ))
},
{ PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1) {
{ PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1, GROUP(
HIZC15_IRQ7, HIZC15_HIZ,
HIZC14_IRQ6, HIZC14_HIZ,
HIZC13_IRQ5, HIZC13_HIZ,
@ -1609,9 +1609,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
0, 0 }
0, 0 ))
},
{ PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1) {
{ PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -1627,103 +1627,103 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
0, 0 }
0, 0 ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
PTC7_DATA, 0, PTC5_DATA, PTC4_DATA,
PTC3_DATA, PTC2_DATA, 0, PTC0_DATA }
PTC3_DATA, PTC2_DATA, 0, PTC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
0, 0, PTE1_DATA, PTE0_DATA }
0, 0, PTE1_DATA, PTE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
0, 0, 0, PTG4_DATA,
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
},
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
0, 0, PTJ1_DATA, PTJ0_DATA }
0, 0, PTJ1_DATA, PTJ0_DATA ))
},
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
0, PTK6_DATA, PTK5_DATA, PTK4_DATA,
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
},
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
},
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
},
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
},
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
},
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
0, 0, 0, PTR4_DATA,
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
},
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
0, 0, 0, PTS4_DATA,
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
},
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
0, 0, 0, PTT4_DATA,
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
},
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
0, 0, 0, PTU4_DATA,
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
},
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
0, 0, 0, PTV4_DATA,
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
},
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
0, PTW6_DATA, PTW5_DATA, PTW4_DATA,
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
},
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
0, PTX6_DATA, PTX5_DATA, PTX4_DATA,
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
},
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
0, PTY6_DATA, PTY5_DATA, PTY4_DATA,
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
},
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
0, 0, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
{ },
};

200
drivers/pinctrl/sh-pfc/pfc-sh7723.c
View File

@ -1507,7 +1507,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
PTA7_FN, PTA7_OUT, 0, PTA7_IN,
PTA6_FN, PTA6_OUT, 0, PTA6_IN,
PTA5_FN, PTA5_OUT, 0, PTA5_IN,
@ -1515,9 +1515,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTA3_FN, PTA3_OUT, 0, PTA3_IN,
PTA2_FN, PTA2_OUT, 0, PTA2_IN,
PTA1_FN, PTA1_OUT, 0, PTA1_IN,
PTA0_FN, PTA0_OUT, 0, PTA0_IN }
PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
PTB7_FN, PTB7_OUT, 0, PTB7_IN,
PTB6_FN, PTB6_OUT, 0, PTB6_IN,
PTB5_FN, PTB5_OUT, 0, PTB5_IN,
@ -1525,9 +1525,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTB3_FN, PTB3_OUT, 0, PTB3_IN,
PTB2_FN, PTB2_OUT, 0, PTB2_IN,
PTB1_FN, PTB1_OUT, 0, PTB1_IN,
PTB0_FN, PTB0_OUT, 0, PTB0_IN }
PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
},
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
PTC7_FN, PTC7_OUT, 0, PTC7_IN,
PTC6_FN, PTC6_OUT, 0, PTC6_IN,
PTC5_FN, PTC5_OUT, 0, PTC5_IN,
@ -1535,9 +1535,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTC3_FN, PTC3_OUT, 0, PTC3_IN,
PTC2_FN, PTC2_OUT, 0, PTC2_IN,
PTC1_FN, PTC1_OUT, 0, PTC1_IN,
PTC0_FN, PTC0_OUT, 0, PTC0_IN }
PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
},
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
PTD7_FN, PTD7_OUT, 0, PTD7_IN,
PTD6_FN, PTD6_OUT, 0, PTD6_IN,
PTD5_FN, PTD5_OUT, 0, PTD5_IN,
@ -1545,9 +1545,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTD3_FN, PTD3_OUT, 0, PTD3_IN,
PTD2_FN, PTD2_OUT, 0, PTD2_IN,
PTD1_FN, PTD1_OUT, 0, PTD1_IN,
PTD0_FN, PTD0_OUT, 0, PTD0_IN }
PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
},
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PTE5_FN, PTE5_OUT, 0, PTE5_IN,
@ -1555,9 +1555,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTE3_FN, PTE3_OUT, 0, PTE3_IN,
PTE2_FN, PTE2_OUT, 0, PTE2_IN,
PTE1_FN, PTE1_OUT, 0, PTE1_IN,
PTE0_FN, PTE0_OUT, 0, PTE0_IN }
PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
},
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
PTF7_FN, PTF7_OUT, 0, PTF7_IN,
PTF6_FN, PTF6_OUT, 0, PTF6_IN,
PTF5_FN, PTF5_OUT, 0, PTF5_IN,
@ -1565,9 +1565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTF3_FN, PTF3_OUT, 0, PTF3_IN,
PTF2_FN, PTF2_OUT, 0, PTF2_IN,
PTF1_FN, PTF1_OUT, 0, PTF1_IN,
PTF0_FN, PTF0_OUT, 0, PTF0_IN }
PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
},
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PTG5_FN, PTG5_OUT, 0, 0,
@ -1575,9 +1575,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTG3_FN, PTG3_OUT, 0, 0,
PTG2_FN, PTG2_OUT, 0, 0,
PTG1_FN, PTG1_OUT, 0, 0,
PTG0_FN, PTG0_OUT, 0, 0 }
PTG0_FN, PTG0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
PTH7_FN, PTH7_OUT, 0, PTH7_IN,
PTH6_FN, PTH6_OUT, 0, PTH6_IN,
PTH5_FN, PTH5_OUT, 0, PTH5_IN,
@ -1585,9 +1585,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTH3_FN, PTH3_OUT, 0, PTH3_IN,
PTH2_FN, PTH2_OUT, 0, PTH2_IN,
PTH1_FN, PTH1_OUT, 0, PTH1_IN,
PTH0_FN, PTH0_OUT, 0, PTH0_IN }
PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
},
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
PTJ7_FN, PTJ7_OUT, 0, 0,
0, 0, 0, 0,
PTJ5_FN, PTJ5_OUT, 0, 0,
@ -1595,9 +1595,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN }
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
},
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
PTK7_FN, PTK7_OUT, 0, PTK7_IN,
PTK6_FN, PTK6_OUT, 0, PTK6_IN,
PTK5_FN, PTK5_OUT, 0, PTK5_IN,
@ -1605,9 +1605,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTK3_FN, PTK3_OUT, 0, PTK3_IN,
PTK2_FN, PTK2_OUT, 0, PTK2_IN,
PTK1_FN, PTK1_OUT, 0, PTK1_IN,
PTK0_FN, PTK0_OUT, 0, PTK0_IN }
PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
},
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
PTL7_FN, PTL7_OUT, 0, PTL7_IN,
PTL6_FN, PTL6_OUT, 0, PTL6_IN,
PTL5_FN, PTL5_OUT, 0, PTL5_IN,
@ -1615,9 +1615,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTL3_FN, PTL3_OUT, 0, PTL3_IN,
PTL2_FN, PTL2_OUT, 0, PTL2_IN,
PTL1_FN, PTL1_OUT, 0, PTL1_IN,
PTL0_FN, PTL0_OUT, 0, PTL0_IN }
PTL0_FN, PTL0_OUT, 0, PTL0_IN ))
},
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
PTM7_FN, PTM7_OUT, 0, PTM7_IN,
PTM6_FN, PTM6_OUT, 0, PTM6_IN,
PTM5_FN, PTM5_OUT, 0, PTM5_IN,
@ -1625,9 +1625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTM3_FN, PTM3_OUT, 0, PTM3_IN,
PTM2_FN, PTM2_OUT, 0, PTM2_IN,
PTM1_FN, PTM1_OUT, 0, PTM1_IN,
PTM0_FN, PTM0_OUT, 0, PTM0_IN }
PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
},
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
PTN7_FN, PTN7_OUT, 0, PTN7_IN,
PTN6_FN, PTN6_OUT, 0, PTN6_IN,
PTN5_FN, PTN5_OUT, 0, PTN5_IN,
@ -1635,9 +1635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTN3_FN, PTN3_OUT, 0, PTN3_IN,
PTN2_FN, PTN2_OUT, 0, PTN2_IN,
PTN1_FN, PTN1_OUT, 0, PTN1_IN,
PTN0_FN, PTN0_OUT, 0, PTN0_IN }
PTN0_FN, PTN0_OUT, 0, PTN0_IN ))
},
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1645,9 +1645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTQ3_FN, 0, 0, PTQ3_IN,
PTQ2_FN, 0, 0, PTQ2_IN,
PTQ1_FN, 0, 0, PTQ1_IN,
PTQ0_FN, 0, 0, PTQ0_IN }
PTQ0_FN, 0, 0, PTQ0_IN ))
},
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
PTR7_FN, PTR7_OUT, 0, PTR7_IN,
PTR6_FN, PTR6_OUT, 0, PTR6_IN,
PTR5_FN, PTR5_OUT, 0, PTR5_IN,
@ -1655,9 +1655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTR3_FN, 0, 0, PTR3_IN,
PTR2_FN, 0, 0, PTR2_IN,
PTR1_FN, PTR1_OUT, 0, PTR1_IN,
PTR0_FN, PTR0_OUT, 0, PTR0_IN }
PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
},
{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
PTS7_FN, PTS7_OUT, 0, PTS7_IN,
PTS6_FN, PTS6_OUT, 0, PTS6_IN,
PTS5_FN, PTS5_OUT, 0, PTS5_IN,
@ -1665,9 +1665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTS3_FN, PTS3_OUT, 0, PTS3_IN,
PTS2_FN, PTS2_OUT, 0, PTS2_IN,
PTS1_FN, PTS1_OUT, 0, PTS1_IN,
PTS0_FN, PTS0_OUT, 0, PTS0_IN }
PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
},
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PTT5_FN, PTT5_OUT, 0, PTT5_IN,
@ -1675,9 +1675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTT3_FN, PTT3_OUT, 0, PTT3_IN,
PTT2_FN, PTT2_OUT, 0, PTT2_IN,
PTT1_FN, PTT1_OUT, 0, PTT1_IN,
PTT0_FN, PTT0_OUT, 0, PTT0_IN }
PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
},
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PTU5_FN, PTU5_OUT, 0, PTU5_IN,
@ -1685,9 +1685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTU3_FN, PTU3_OUT, 0, PTU3_IN,
PTU2_FN, PTU2_OUT, 0, PTU2_IN,
PTU1_FN, PTU1_OUT, 0, PTU1_IN,
PTU0_FN, PTU0_OUT, 0, PTU0_IN }
PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
},
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
PTV7_FN, PTV7_OUT, 0, PTV7_IN,
PTV6_FN, PTV6_OUT, 0, PTV6_IN,
PTV5_FN, PTV5_OUT, 0, PTV5_IN,
@ -1695,9 +1695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTV3_FN, PTV3_OUT, 0, PTV3_IN,
PTV2_FN, PTV2_OUT, 0, PTV2_IN,
PTV1_FN, PTV1_OUT, 0, PTV1_IN,
PTV0_FN, PTV0_OUT, 0, PTV0_IN }
PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
},
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
PTW7_FN, PTW7_OUT, 0, PTW7_IN,
PTW6_FN, PTW6_OUT, 0, PTW6_IN,
PTW5_FN, PTW5_OUT, 0, PTW5_IN,
@ -1705,9 +1705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTW3_FN, PTW3_OUT, 0, PTW3_IN,
PTW2_FN, PTW2_OUT, 0, PTW2_IN,
PTW1_FN, PTW1_OUT, 0, PTW1_IN,
PTW0_FN, PTW0_OUT, 0, PTW0_IN }
PTW0_FN, PTW0_OUT, 0, PTW0_IN ))
},
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
PTX7_FN, PTX7_OUT, 0, PTX7_IN,
PTX6_FN, PTX6_OUT, 0, PTX6_IN,
PTX5_FN, PTX5_OUT, 0, PTX5_IN,
@ -1715,9 +1715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTX3_FN, PTX3_OUT, 0, PTX3_IN,
PTX2_FN, PTX2_OUT, 0, PTX2_IN,
PTX1_FN, PTX1_OUT, 0, PTX1_IN,
PTX0_FN, PTX0_OUT, 0, PTX0_IN }
PTX0_FN, PTX0_OUT, 0, PTX0_IN ))
},
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
PTY7_FN, PTY7_OUT, 0, PTY7_IN,
PTY6_FN, PTY6_OUT, 0, PTY6_IN,
PTY5_FN, PTY5_OUT, 0, PTY5_IN,
@ -1725,9 +1725,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTY3_FN, PTY3_OUT, 0, PTY3_IN,
PTY2_FN, PTY2_OUT, 0, PTY2_IN,
PTY1_FN, PTY1_OUT, 0, PTY1_IN,
PTY0_FN, PTY0_OUT, 0, PTY0_IN }
PTY0_FN, PTY0_OUT, 0, PTY0_IN ))
},
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
@ -1735,9 +1735,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN }
PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN ))
},
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2) {
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2, GROUP(
PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0,
PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0,
PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0,
@ -1745,9 +1745,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0,
PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2) {
{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2, GROUP(
PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0,
PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0,
0, 0, 0, 0,
@ -1755,9 +1755,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0,
PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0,
PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2) {
{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2, GROUP(
PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0,
PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0,
PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0,
@ -1765,9 +1765,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2) {
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2, GROUP(
PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0,
PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0,
PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0,
@ -1775,103 +1775,103 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0,
PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0,
PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0,
PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 }
PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
0, 0, PTE5_DATA, PTE4_DATA,
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
0, 0, PTG5_DATA, PTG4_DATA,
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
},
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
PTJ7_DATA, 0, PTJ5_DATA, 0,
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
},
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
},
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
},
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
},
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
},
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
0, 0, 0, 0,
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
},
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
},
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
},
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
0, 0, PTT5_DATA, PTT4_DATA,
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
},
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
0, 0, PTU5_DATA, PTU4_DATA,
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
},
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
},
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
},
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
},
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
},
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
{ },
};

204
drivers/pinctrl/sh-pfc/pfc-sh7724.c
View File

@ -1739,7 +1739,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2, GROUP(
PTA7_FN, PTA7_OUT, 0, PTA7_IN,
PTA6_FN, PTA6_OUT, 0, PTA6_IN,
PTA5_FN, PTA5_OUT, 0, PTA5_IN,
@ -1747,9 +1747,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTA3_FN, PTA3_OUT, 0, PTA3_IN,
PTA2_FN, PTA2_OUT, 0, PTA2_IN,
PTA1_FN, PTA1_OUT, 0, PTA1_IN,
PTA0_FN, PTA0_OUT, 0, PTA0_IN }
PTA0_FN, PTA0_OUT, 0, PTA0_IN ))
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2, GROUP(
PTB7_FN, PTB7_OUT, 0, PTB7_IN,
PTB6_FN, PTB6_OUT, 0, PTB6_IN,
PTB5_FN, PTB5_OUT, 0, PTB5_IN,
@ -1757,9 +1757,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTB3_FN, PTB3_OUT, 0, PTB3_IN,
PTB2_FN, PTB2_OUT, 0, PTB2_IN,
PTB1_FN, PTB1_OUT, 0, PTB1_IN,
PTB0_FN, PTB0_OUT, 0, PTB0_IN }
PTB0_FN, PTB0_OUT, 0, PTB0_IN ))
},
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
{ PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2, GROUP(
PTC7_FN, PTC7_OUT, 0, PTC7_IN,
PTC6_FN, PTC6_OUT, 0, PTC6_IN,
PTC5_FN, PTC5_OUT, 0, PTC5_IN,
@ -1767,9 +1767,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTC3_FN, PTC3_OUT, 0, PTC3_IN,
PTC2_FN, PTC2_OUT, 0, PTC2_IN,
PTC1_FN, PTC1_OUT, 0, PTC1_IN,
PTC0_FN, PTC0_OUT, 0, PTC0_IN }
PTC0_FN, PTC0_OUT, 0, PTC0_IN ))
},
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
{ PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2, GROUP(
PTD7_FN, PTD7_OUT, 0, PTD7_IN,
PTD6_FN, PTD6_OUT, 0, PTD6_IN,
PTD5_FN, PTD5_OUT, 0, PTD5_IN,
@ -1777,9 +1777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTD3_FN, PTD3_OUT, 0, PTD3_IN,
PTD2_FN, PTD2_OUT, 0, PTD2_IN,
PTD1_FN, PTD1_OUT, 0, PTD1_IN,
PTD0_FN, PTD0_OUT, 0, PTD0_IN }
PTD0_FN, PTD0_OUT, 0, PTD0_IN ))
},
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
{ PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2, GROUP(
PTE7_FN, PTE7_OUT, 0, PTE7_IN,
PTE6_FN, PTE6_OUT, 0, PTE6_IN,
PTE5_FN, PTE5_OUT, 0, PTE5_IN,
@ -1787,9 +1787,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTE3_FN, PTE3_OUT, 0, PTE3_IN,
PTE2_FN, PTE2_OUT, 0, PTE2_IN,
PTE1_FN, PTE1_OUT, 0, PTE1_IN,
PTE0_FN, PTE0_OUT, 0, PTE0_IN }
PTE0_FN, PTE0_OUT, 0, PTE0_IN ))
},
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
{ PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2, GROUP(
PTF7_FN, PTF7_OUT, 0, PTF7_IN,
PTF6_FN, PTF6_OUT, 0, PTF6_IN,
PTF5_FN, PTF5_OUT, 0, PTF5_IN,
@ -1797,9 +1797,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTF3_FN, PTF3_OUT, 0, PTF3_IN,
PTF2_FN, PTF2_OUT, 0, PTF2_IN,
PTF1_FN, PTF1_OUT, 0, PTF1_IN,
PTF0_FN, PTF0_OUT, 0, PTF0_IN }
PTF0_FN, PTF0_OUT, 0, PTF0_IN ))
},
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
{ PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PTG5_FN, PTG5_OUT, 0, 0,
@ -1807,9 +1807,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTG3_FN, PTG3_OUT, 0, 0,
PTG2_FN, PTG2_OUT, 0, 0,
PTG1_FN, PTG1_OUT, 0, 0,
PTG0_FN, PTG0_OUT, 0, 0 }
PTG0_FN, PTG0_OUT, 0, 0 ))
},
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
{ PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2, GROUP(
PTH7_FN, PTH7_OUT, 0, PTH7_IN,
PTH6_FN, PTH6_OUT, 0, PTH6_IN,
PTH5_FN, PTH5_OUT, 0, PTH5_IN,
@ -1817,9 +1817,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTH3_FN, PTH3_OUT, 0, PTH3_IN,
PTH2_FN, PTH2_OUT, 0, PTH2_IN,
PTH1_FN, PTH1_OUT, 0, PTH1_IN,
PTH0_FN, PTH0_OUT, 0, PTH0_IN }
PTH0_FN, PTH0_OUT, 0, PTH0_IN ))
},
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
{ PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2, GROUP(
PTJ7_FN, PTJ7_OUT, 0, 0,
PTJ6_FN, PTJ6_OUT, 0, 0,
PTJ5_FN, PTJ5_OUT, 0, 0,
@ -1827,9 +1827,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN }
PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN ))
},
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
{ PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2, GROUP(
PTK7_FN, PTK7_OUT, 0, PTK7_IN,
PTK6_FN, PTK6_OUT, 0, PTK6_IN,
PTK5_FN, PTK5_OUT, 0, PTK5_IN,
@ -1837,9 +1837,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTK3_FN, PTK3_OUT, 0, PTK3_IN,
PTK2_FN, PTK2_OUT, 0, PTK2_IN,
PTK1_FN, PTK1_OUT, 0, PTK1_IN,
PTK0_FN, PTK0_OUT, 0, PTK0_IN }
PTK0_FN, PTK0_OUT, 0, PTK0_IN ))
},
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
{ PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2, GROUP(
PTL7_FN, PTL7_OUT, 0, PTL7_IN,
PTL6_FN, PTL6_OUT, 0, PTL6_IN,
PTL5_FN, PTL5_OUT, 0, PTL5_IN,
@ -1847,9 +1847,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTL3_FN, PTL3_OUT, 0, PTL3_IN,
PTL2_FN, PTL2_OUT, 0, PTL2_IN,
PTL1_FN, PTL1_OUT, 0, PTL1_IN,
PTL0_FN, PTL0_OUT, 0, PTL0_IN }
PTL0_FN, PTL0_OUT, 0, PTL0_IN ))
},
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
{ PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2, GROUP(
PTM7_FN, PTM7_OUT, 0, PTM7_IN,
PTM6_FN, PTM6_OUT, 0, PTM6_IN,
PTM5_FN, PTM5_OUT, 0, PTM5_IN,
@ -1857,9 +1857,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTM3_FN, PTM3_OUT, 0, PTM3_IN,
PTM2_FN, PTM2_OUT, 0, PTM2_IN,
PTM1_FN, PTM1_OUT, 0, PTM1_IN,
PTM0_FN, PTM0_OUT, 0, PTM0_IN }
PTM0_FN, PTM0_OUT, 0, PTM0_IN ))
},
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
{ PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2, GROUP(
PTN7_FN, PTN7_OUT, 0, PTN7_IN,
PTN6_FN, PTN6_OUT, 0, PTN6_IN,
PTN5_FN, PTN5_OUT, 0, PTN5_IN,
@ -1867,9 +1867,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTN3_FN, PTN3_OUT, 0, PTN3_IN,
PTN2_FN, PTN2_OUT, 0, PTN2_IN,
PTN1_FN, PTN1_OUT, 0, PTN1_IN,
PTN0_FN, PTN0_OUT, 0, PTN0_IN }
PTN0_FN, PTN0_OUT, 0, PTN0_IN ))
},
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
{ PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2, GROUP(
PTQ7_FN, PTQ7_OUT, 0, PTQ7_IN,
PTQ6_FN, PTQ6_OUT, 0, PTQ6_IN,
PTQ5_FN, PTQ5_OUT, 0, PTQ5_IN,
@ -1877,9 +1877,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTQ3_FN, PTQ3_OUT, 0, PTQ3_IN,
PTQ2_FN, PTQ2_OUT, 0, PTQ2_IN,
PTQ1_FN, PTQ1_OUT, 0, PTQ1_IN,
PTQ0_FN, PTQ0_OUT, 0, PTQ0_IN }
PTQ0_FN, PTQ0_OUT, 0, PTQ0_IN ))
},
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
{ PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2, GROUP(
PTR7_FN, PTR7_OUT, 0, PTR7_IN,
PTR6_FN, PTR6_OUT, 0, PTR6_IN,
PTR5_FN, PTR5_OUT, 0, PTR5_IN,
@ -1887,9 +1887,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTR3_FN, 0, 0, PTR3_IN,
PTR2_FN, 0, 0, PTR2_IN,
PTR1_FN, PTR1_OUT, 0, PTR1_IN,
PTR0_FN, PTR0_OUT, 0, PTR0_IN }
PTR0_FN, PTR0_OUT, 0, PTR0_IN ))
},
{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
{ PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2, GROUP(
0, 0, 0, 0,
PTS6_FN, PTS6_OUT, 0, PTS6_IN,
PTS5_FN, PTS5_OUT, 0, PTS5_IN,
@ -1897,9 +1897,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTS3_FN, PTS3_OUT, 0, PTS3_IN,
PTS2_FN, PTS2_OUT, 0, PTS2_IN,
PTS1_FN, PTS1_OUT, 0, PTS1_IN,
PTS0_FN, PTS0_OUT, 0, PTS0_IN }
PTS0_FN, PTS0_OUT, 0, PTS0_IN ))
},
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
{ PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2, GROUP(
PTT7_FN, PTT7_OUT, 0, PTT7_IN,
PTT6_FN, PTT6_OUT, 0, PTT6_IN,
PTT5_FN, PTT5_OUT, 0, PTT5_IN,
@ -1907,9 +1907,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTT3_FN, PTT3_OUT, 0, PTT3_IN,
PTT2_FN, PTT2_OUT, 0, PTT2_IN,
PTT1_FN, PTT1_OUT, 0, PTT1_IN,
PTT0_FN, PTT0_OUT, 0, PTT0_IN }
PTT0_FN, PTT0_OUT, 0, PTT0_IN ))
},
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
{ PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2, GROUP(
PTU7_FN, PTU7_OUT, 0, PTU7_IN,
PTU6_FN, PTU6_OUT, 0, PTU6_IN,
PTU5_FN, PTU5_OUT, 0, PTU5_IN,
@ -1917,9 +1917,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTU3_FN, PTU3_OUT, 0, PTU3_IN,
PTU2_FN, PTU2_OUT, 0, PTU2_IN,
PTU1_FN, PTU1_OUT, 0, PTU1_IN,
PTU0_FN, PTU0_OUT, 0, PTU0_IN }
PTU0_FN, PTU0_OUT, 0, PTU0_IN ))
},
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
{ PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2, GROUP(
PTV7_FN, PTV7_OUT, 0, PTV7_IN,
PTV6_FN, PTV6_OUT, 0, PTV6_IN,
PTV5_FN, PTV5_OUT, 0, PTV5_IN,
@ -1927,9 +1927,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTV3_FN, PTV3_OUT, 0, PTV3_IN,
PTV2_FN, PTV2_OUT, 0, PTV2_IN,
PTV1_FN, PTV1_OUT, 0, PTV1_IN,
PTV0_FN, PTV0_OUT, 0, PTV0_IN }
PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
},
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
{ PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2, GROUP(
PTW7_FN, PTW7_OUT, 0, PTW7_IN,
PTW6_FN, PTW6_OUT, 0, PTW6_IN,
PTW5_FN, PTW5_OUT, 0, PTW5_IN,
@ -1937,9 +1937,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTW3_FN, PTW3_OUT, 0, PTW3_IN,
PTW2_FN, PTW2_OUT, 0, PTW2_IN,
PTW1_FN, PTW1_OUT, 0, PTW1_IN,
PTW0_FN, PTW0_OUT, 0, PTW0_IN }
PTW0_FN, PTW0_OUT, 0, PTW0_IN ))
},
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
{ PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2, GROUP(
PTX7_FN, PTX7_OUT, 0, PTX7_IN,
PTX6_FN, PTX6_OUT, 0, PTX6_IN,
PTX5_FN, PTX5_OUT, 0, PTX5_IN,
@ -1947,9 +1947,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTX3_FN, PTX3_OUT, 0, PTX3_IN,
PTX2_FN, PTX2_OUT, 0, PTX2_IN,
PTX1_FN, PTX1_OUT, 0, PTX1_IN,
PTX0_FN, PTX0_OUT, 0, PTX0_IN }
PTX0_FN, PTX0_OUT, 0, PTX0_IN ))
},
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
{ PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2, GROUP(
PTY7_FN, PTY7_OUT, 0, PTY7_IN,
PTY6_FN, PTY6_OUT, 0, PTY6_IN,
PTY5_FN, PTY5_OUT, 0, PTY5_IN,
@ -1957,9 +1957,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTY3_FN, PTY3_OUT, 0, PTY3_IN,
PTY2_FN, PTY2_OUT, 0, PTY2_IN,
PTY1_FN, PTY1_OUT, 0, PTY1_IN,
PTY0_FN, PTY0_OUT, 0, PTY0_IN }
PTY0_FN, PTY0_OUT, 0, PTY0_IN ))
},
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
{ PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2, GROUP(
PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
@ -1967,9 +1967,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN }
PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN ))
},
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
{ PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1, GROUP(
PSA15_0, PSA15_1,
PSA14_0, PSA14_1,
PSA13_0, PSA13_1,
@ -1985,9 +1985,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSA3_0, PSA3_1,
PSA2_0, PSA2_1,
PSA1_0, PSA1_1,
PSA0_0, PSA0_1}
PSA0_0, PSA0_1))
},
{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
{ PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1, GROUP(
0, 0,
PSB14_0, PSB14_1,
PSB13_0, PSB13_1,
@ -2003,9 +2003,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSB3_0, PSB3_1,
PSB2_0, PSB2_1,
PSB1_0, PSB1_1,
PSB0_0, PSB0_1}
PSB0_0, PSB0_1))
},
{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
{ PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1, GROUP(
PSC15_0, PSC15_1,
PSC14_0, PSC14_1,
PSC13_0, PSC13_1,
@ -2021,9 +2021,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
PSC2_0, PSC2_1,
PSC1_0, PSC1_1,
PSC0_0, PSC0_1}
PSC0_0, PSC0_1))
},
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
{ PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1, GROUP(
PSD15_0, PSD15_1,
PSD14_0, PSD14_1,
PSD13_0, PSD13_1,
@ -2039,9 +2039,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSD3_0, PSD3_1,
PSD2_0, PSD2_1,
PSD1_0, PSD1_1,
PSD0_0, PSD0_1}
PSD0_0, PSD0_1))
},
{ PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
{ PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1, GROUP(
PSE15_0, PSE15_1,
PSE14_0, PSE14_1,
PSE13_0, PSE13_1,
@ -2057,103 +2057,103 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PSE3_0, PSE3_1,
PSE2_0, PSE2_1,
PSE1_0, PSE1_1,
PSE0_0, PSE0_1}
PSE0_0, PSE0_1))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8, GROUP(
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
{ PINMUX_DATA_REG("PBDR", 0xa4050122, 8, GROUP(
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
{ PINMUX_DATA_REG("PCDR", 0xa4050124, 8, GROUP(
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
{ PINMUX_DATA_REG("PDDR", 0xa4050126, 8, GROUP(
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
{ PINMUX_DATA_REG("PEDR", 0xa4050128, 8, GROUP(
PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
{ PINMUX_DATA_REG("PFDR", 0xa405012a, 8, GROUP(
PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
{ PINMUX_DATA_REG("PGDR", 0xa405012c, 8, GROUP(
0, 0, PTG5_DATA, PTG4_DATA,
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
},
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
{ PINMUX_DATA_REG("PHDR", 0xa405012e, 8, GROUP(
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
{ PINMUX_DATA_REG("PJDR", 0xa4050130, 8, GROUP(
PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
},
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
{ PINMUX_DATA_REG("PKDR", 0xa4050132, 8, GROUP(
PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
},
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
{ PINMUX_DATA_REG("PLDR", 0xa4050134, 8, GROUP(
PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
},
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
{ PINMUX_DATA_REG("PMDR", 0xa4050136, 8, GROUP(
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
},
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
{ PINMUX_DATA_REG("PNDR", 0xa4050138, 8, GROUP(
PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
},
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
{ PINMUX_DATA_REG("PQDR", 0xa405013a, 8, GROUP(
PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
},
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
{ PINMUX_DATA_REG("PRDR", 0xa405013c, 8, GROUP(
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
},
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
{ PINMUX_DATA_REG("PSDR", 0xa405013e, 8, GROUP(
0, PTS6_DATA, PTS5_DATA, PTS4_DATA,
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
},
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
{ PINMUX_DATA_REG("PTDR", 0xa4050160, 8, GROUP(
PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
},
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
{ PINMUX_DATA_REG("PUDR", 0xa4050162, 8, GROUP(
PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
},
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
{ PINMUX_DATA_REG("PVDR", 0xa4050164, 8, GROUP(
PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
},
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
{ PINMUX_DATA_REG("PWDR", 0xa4050166, 8, GROUP(
PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
},
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
{ PINMUX_DATA_REG("PXDR", 0xa4050168, 8, GROUP(
PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
},
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
{ PINMUX_DATA_REG("PYDR", 0xa405016a, 8, GROUP(
PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
},
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
{ PINMUX_DATA_REG("PZDR", 0xa405016c, 8, GROUP(
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
{ },
};

140
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View File

@ -1635,7 +1635,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
{ PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1, GROUP(
GP_0_31_FN, FN_IP2_2_0,
GP_0_30_FN, FN_IP1_31_29,
GP_0_29_FN, FN_IP1_28_26,
@ -1667,9 +1667,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_0_3_FN, FN_IP1_15_14,
GP_0_2_FN, FN_IP1_13_12,
GP_0_1_FN, FN_IP1_11_10,
GP_0_0_FN, FN_IP1_9_8 }
GP_0_0_FN, FN_IP1_9_8 ))
},
{ PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) {
{ PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1, GROUP(
GP_1_31_FN, FN_IP11_25_23,
GP_1_30_FN, FN_IP2_13_11,
GP_1_29_FN, FN_IP2_10_8,
@ -1701,9 +1701,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_3_FN, FN_IP11_22_21,
GP_1_2_FN, FN_IP11_20_19,
GP_1_1_FN, FN_IP3_29_27,
GP_1_0_FN, FN_IP3_20 }
GP_1_0_FN, FN_IP3_20 ))
},
{ PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) {
{ PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1, GROUP(
GP_2_31_FN, FN_IP4_31_30,
GP_2_30_FN, FN_IP5_2_0,
GP_2_29_FN, FN_IP5_5_3,
@ -1735,9 +1735,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_3_FN, FN_IP4_2_0,
GP_2_2_FN, FN_IP11_11_10,
GP_2_1_FN, FN_IP11_9_7,
GP_2_0_FN, FN_IP11_6_4 }
GP_2_0_FN, FN_IP11_6_4 ))
},
{ PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) {
{ PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1, GROUP(
GP_3_31_FN, FN_IP9_1_0,
GP_3_30_FN, FN_IP8_19_18,
GP_3_29_FN, FN_IP8_17_16,
@ -1769,10 +1769,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_3_FN, FN_IP6_9_8,
GP_3_2_FN, FN_IP6_7_6,
GP_3_1_FN, FN_IP6_5_3,
GP_3_0_FN, FN_IP6_2_0 }
GP_3_0_FN, FN_IP6_2_0 ))
},
{ PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) {
{ PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1, GROUP(
GP_4_31_FN, FN_IP10_24_23,
GP_4_30_FN, FN_IP10_22,
GP_4_29_FN, FN_IP11_18_16,
@ -1804,9 +1804,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_4_3_FN, FN_IP9_25_24,
GP_4_2_FN, FN_IP9_23_22,
GP_4_1_FN, FN_IP9_21_20,
GP_4_0_FN, FN_IP9_19_18 }
GP_4_0_FN, FN_IP9_19_18 ))
},
{ PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) {
{ PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
@ -1819,12 +1819,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_FN, FN_IRQ3_B,
GP_5_2_FN, FN_IRQ2_B,
GP_5_1_FN, FN_IP11_3,
GP_5_0_FN, FN_IP10_25 }
GP_5_0_FN, FN_IP10_25 ))
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* IP0_31_30 [2] */
FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
FN_TIOC3D_C,
@ -1857,10 +1857,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP0_3_2 [2] */
FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
/* IP0_1_0 [2] */
FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C }
FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C ))
},
{ PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
GROUP(
/* IP1_31_29 [3] */
FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
FN_FD3_A, 0, 0, 0,
@ -1892,10 +1893,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP1_3_2 [2] */
FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
/* IP1_1_0 [2] */
FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C }
FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
},
{ PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3) {
GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
GROUP(
/* IP2_31 [1] */
0, 0,
/* IP2_30_28 [3] */
@ -1928,10 +1930,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
/* IP2_2_0 [3] */
FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
FN_FD4_A, 0, 0, 0 }
FN_FD4_A, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2) {
GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
GROUP(
/* IP3_31_30 [2] */
0, 0, 0, 0,
/* IP3_29_27 [3] */
@ -1965,10 +1968,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP3_2 [1] */
FN_CS1_A26, FN_QIO3_B,
/* IP3_1_0 [2] */
FN_D15, FN_SCK2_B, 0, 0 }
FN_D15, FN_SCK2_B, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2, 2, 2, 2, 2, 2 , 2, 3, 3, 3, 3, 3, 3) {
GROUP(2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP4_31_30 [2] */
0, FN_SCK2_A, FN_VI0_G3, 0,
/* IP4_29_28 [2] */
@ -2000,10 +2004,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_ET0_RX_DV, 0, 0, 0,
/* IP4_2_0 [3] */
FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
FN_ET0_ERXD7, 0, 0, 0 }
FN_ET0_ERXD7, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3) {
GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
3, 3, 3),
GROUP(
/* IP5_31 [1] */
0, 0,
/* IP5_30 [1] */
@ -2040,11 +2046,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, FN_ET0_ERXD2_B,
/* IP5_2_0 [3] */
FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
FN_ET0_RX_CLK_B, 0, 0, 0 }
FN_ET0_RX_CLK_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
1, 1, 1, 1, 1, 1, 1, 1,
3, 3, 2, 2, 2, 2, 2, 2, 3, 3) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
2, 2, 2, 2, 3, 3),
GROUP(
/* IP5_31 [1] */
0, 0,
/* IP6_30 [1] */
@ -2084,10 +2091,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_TCLKB_A, FN_HIFD01, 0, 0,
/* IP6_2_0 [3] */
FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
FN_TCLKA_A, FN_HIFD00, 0, 0 }
FN_TCLKA_A, FN_HIFD00, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
GROUP(
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
@ -2120,10 +2128,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_HIFD11, 0, 0, 0,
/* IP7_2_0 [3] */
FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
FN_HIFD10, 0, 0, 0 }
FN_HIFD10, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2),
GROUP(
/* IP9_31_30 [2] */
0, 0, 0, 0,
/* IP8_29_28 [2] */
@ -2156,11 +2166,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP8_3_2 [2] */
FN_DU0_DB6, 0, FN_HIFRDY, 0,
/* IP8_1_0 [2] */
FN_DU0_DB5, 0, FN_HIFDREQ, 0 }
FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2) {
GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2),
GROUP(
/* IP9_31_30 [2] */
0, 0, 0, 0,
/* IP9_29_28 [2] */
@ -2192,11 +2203,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP9_3_2 [2] */
FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
/* IP9_1_0 [2] */
FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B }
FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
},
{ PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
2, 2, 2, 1, 2, 1, 3,
3, 1, 3, 3, 3, 3, 3) {
GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
GROUP(
/* IP9_31_30 [2] */
0, 0, 0, 0,
/* IP10_29_28 [2] */
@ -2231,10 +2242,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_LCD_DON_B, 0, 0,
/* IP10_2_0 [3] */
FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
FN_LCD_DATA15_B, 0, 0, 0 }
FN_LCD_DATA15_B, 0, 0, 0 ))
},
{ PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) {
GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
1, 1, 1, 1),
GROUP(
/* IP11_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* IP11_28 [1] */
@ -2271,11 +2284,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* IP11_1 [1] */
FN_SDA1, FN_RX1_E,
/* IP11_0 [1] */
FN_SCL1, FN_SCIF_CLK_C }
FN_SCL1, FN_SCIF_CLK_C ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2, 2,
1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
GROUP(
/* SEL1_31_29 [3] */
0, 0, 0, 0, 0, 0, 0, 0,
/* SEL1_28 [1] */
@ -2327,11 +2341,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL1_1 [1] */
FN_SEL_MMC_0, FN_SEL_MMC_1,
/* SEL1_0 [1] */
FN_SEL_INTC_0, FN_SEL_INTC_1 }
FN_SEL_INTC_0, FN_SEL_INTC_1 ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2) {
GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
2, 1, 2, 2, 3, 2, 3, 2, 2),
GROUP(
/* SEL2_31 [1] */
0, 0,
/* SEL2_30 [1] */
@ -2375,15 +2390,20 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL2_3_2 [2] */
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
/* SEL2_1_0 [2] */
FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 }
FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 ))
},
/* GPIO 0 - 5*/
{ PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } },
{ PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } },
{ PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } },
{ PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } },
{ PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1) { GP_INOUTSEL(4) } },
{ PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) {
{ PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1, GROUP(GP_INOUTSEL(0)))
},
{ PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1, GROUP(GP_INOUTSEL(1)))
},
{ PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1, GROUP(GP_INOUTSEL(2)))
},
{ PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1, GROUP(GP_INOUTSEL(3)))
},
{ PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
},
{ PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
@ -2398,24 +2418,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_5_3_IN, GP_5_3_OUT,
GP_5_2_IN, GP_5_2_OUT,
GP_5_1_IN, GP_5_1_OUT,
GP_5_0_IN, GP_5_0_OUT }
GP_5_0_IN, GP_5_0_OUT ))
},
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
/* GPIO 0 - 5*/
{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
{ PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } },
{ PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } },
{ PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } },
{ PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) {
{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
{ PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
{ PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
{ PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
{ PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
},
{ },
};

244
drivers/pinctrl/sh-pfc/pfc-sh7757.c
View File

@ -1683,7 +1683,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
{ PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2, GROUP(
PTA7_FN, PTA7_OUT, PTA7_IN, 0,
PTA6_FN, PTA6_OUT, PTA6_IN, 0,
PTA5_FN, PTA5_OUT, PTA5_IN, 0,
@ -1691,9 +1691,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTA3_FN, PTA3_OUT, PTA3_IN, 0,
PTA2_FN, PTA2_OUT, PTA2_IN, 0,
PTA1_FN, PTA1_OUT, PTA1_IN, 0,
PTA0_FN, PTA0_OUT, PTA0_IN, 0 }
PTA0_FN, PTA0_OUT, PTA0_IN, 0 ))
},
{ PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
{ PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2, GROUP(
PTB7_FN, PTB7_OUT, PTB7_IN, 0,
PTB6_FN, PTB6_OUT, PTB6_IN, 0,
PTB5_FN, PTB5_OUT, PTB5_IN, 0,
@ -1701,9 +1701,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTB3_FN, PTB3_OUT, PTB3_IN, 0,
PTB2_FN, PTB2_OUT, PTB2_IN, 0,
PTB1_FN, PTB1_OUT, PTB1_IN, 0,
PTB0_FN, PTB0_OUT, PTB0_IN, 0 }
PTB0_FN, PTB0_OUT, PTB0_IN, 0 ))
},
{ PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
{ PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2, GROUP(
PTC7_FN, PTC7_OUT, PTC7_IN, 0,
PTC6_FN, PTC6_OUT, PTC6_IN, 0,
PTC5_FN, PTC5_OUT, PTC5_IN, 0,
@ -1711,9 +1711,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTC3_FN, PTC3_OUT, PTC3_IN, 0,
PTC2_FN, PTC2_OUT, PTC2_IN, 0,
PTC1_FN, PTC1_OUT, PTC1_IN, 0,
PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
PTC0_FN, PTC0_OUT, PTC0_IN, 0 ))
},
{ PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
{ PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2, GROUP(
PTD7_FN, PTD7_OUT, PTD7_IN, 0,
PTD6_FN, PTD6_OUT, PTD6_IN, 0,
PTD5_FN, PTD5_OUT, PTD5_IN, 0,
@ -1721,9 +1721,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTD3_FN, PTD3_OUT, PTD3_IN, 0,
PTD2_FN, PTD2_OUT, PTD2_IN, 0,
PTD1_FN, PTD1_OUT, PTD1_IN, 0,
PTD0_FN, PTD0_OUT, PTD0_IN, 0 }
PTD0_FN, PTD0_OUT, PTD0_IN, 0 ))
},
{ PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
{ PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2, GROUP(
PTE7_FN, PTE7_OUT, PTE7_IN, 0,
PTE6_FN, PTE6_OUT, PTE6_IN, 0,
PTE5_FN, PTE5_OUT, PTE5_IN, 0,
@ -1731,9 +1731,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTE3_FN, PTE3_OUT, PTE3_IN, 0,
PTE2_FN, PTE2_OUT, PTE2_IN, 0,
PTE1_FN, PTE1_OUT, PTE1_IN, 0,
PTE0_FN, PTE0_OUT, PTE0_IN, 0 }
PTE0_FN, PTE0_OUT, PTE0_IN, 0 ))
},
{ PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
{ PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2, GROUP(
PTF7_FN, PTF7_OUT, PTF7_IN, 0,
PTF6_FN, PTF6_OUT, PTF6_IN, 0,
PTF5_FN, PTF5_OUT, PTF5_IN, 0,
@ -1741,9 +1741,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTF3_FN, PTF3_OUT, PTF3_IN, 0,
PTF2_FN, PTF2_OUT, PTF2_IN, 0,
PTF1_FN, PTF1_OUT, PTF1_IN, 0,
PTF0_FN, PTF0_OUT, PTF0_IN, 0 }
PTF0_FN, PTF0_OUT, PTF0_IN, 0 ))
},
{ PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
{ PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2, GROUP(
PTG7_FN, PTG7_OUT, PTG7_IN, 0,
PTG6_FN, PTG6_OUT, PTG6_IN, 0,
PTG5_FN, PTG5_OUT, PTG5_IN, 0,
@ -1751,9 +1751,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTG3_FN, PTG3_OUT, PTG3_IN, 0,
PTG2_FN, PTG2_OUT, PTG2_IN, 0,
PTG1_FN, PTG1_OUT, PTG1_IN, 0,
PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
PTG0_FN, PTG0_OUT, PTG0_IN, 0 ))
},
{ PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
{ PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2, GROUP(
PTH7_FN, PTH7_OUT, PTH7_IN, 0,
PTH6_FN, PTH6_OUT, PTH6_IN, 0,
PTH5_FN, PTH5_OUT, PTH5_IN, 0,
@ -1761,9 +1761,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTH3_FN, PTH3_OUT, PTH3_IN, 0,
PTH2_FN, PTH2_OUT, PTH2_IN, 0,
PTH1_FN, PTH1_OUT, PTH1_IN, 0,
PTH0_FN, PTH0_OUT, PTH0_IN, 0 }
PTH0_FN, PTH0_OUT, PTH0_IN, 0 ))
},
{ PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
{ PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2, GROUP(
PTI7_FN, PTI7_OUT, PTI7_IN, 0,
PTI6_FN, PTI6_OUT, PTI6_IN, 0,
PTI5_FN, PTI5_OUT, PTI5_IN, 0,
@ -1771,9 +1771,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTI3_FN, PTI3_OUT, PTI3_IN, 0,
PTI2_FN, PTI2_OUT, PTI2_IN, 0,
PTI1_FN, PTI1_OUT, PTI1_IN, 0,
PTI0_FN, PTI0_OUT, PTI0_IN, 0 }
PTI0_FN, PTI0_OUT, PTI0_IN, 0 ))
},
{ PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
{ PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2, GROUP(
0, 0, 0, 0, /* reserved: always set 1 */
PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
@ -1781,9 +1781,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 }
PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 ))
},
{ PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
{ PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2, GROUP(
PTK7_FN, PTK7_OUT, PTK7_IN, 0,
PTK6_FN, PTK6_OUT, PTK6_IN, 0,
PTK5_FN, PTK5_OUT, PTK5_IN, 0,
@ -1791,9 +1791,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTK3_FN, PTK3_OUT, PTK3_IN, 0,
PTK2_FN, PTK2_OUT, PTK2_IN, 0,
PTK1_FN, PTK1_OUT, PTK1_IN, 0,
PTK0_FN, PTK0_OUT, PTK0_IN, 0 }
PTK0_FN, PTK0_OUT, PTK0_IN, 0 ))
},
{ PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
{ PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2, GROUP(
0, 0, 0, 0, /* reserved: always set 1 */
PTL6_FN, PTL6_OUT, PTL6_IN, 0,
PTL5_FN, PTL5_OUT, PTL5_IN, 0,
@ -1801,9 +1801,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTL3_FN, PTL3_OUT, PTL3_IN, 0,
PTL2_FN, PTL2_OUT, PTL2_IN, 0,
PTL1_FN, PTL1_OUT, PTL1_IN, 0,
PTL0_FN, PTL0_OUT, PTL0_IN, 0 }
PTL0_FN, PTL0_OUT, PTL0_IN, 0 ))
},
{ PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
{ PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2, GROUP(
PTM7_FN, PTM7_OUT, PTM7_IN, 0,
PTM6_FN, PTM6_OUT, PTM6_IN, 0,
PTM5_FN, PTM5_OUT, PTM5_IN, 0,
@ -1811,9 +1811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTM3_FN, PTM3_OUT, PTM3_IN, 0,
PTM2_FN, PTM2_OUT, PTM2_IN, 0,
PTM1_FN, PTM1_OUT, PTM1_IN, 0,
PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
PTM0_FN, PTM0_OUT, PTM0_IN, 0 ))
},
{ PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
{ PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2, GROUP(
0, 0, 0, 0, /* reserved: always set 1 */
PTN6_FN, PTN6_OUT, PTN6_IN, 0,
PTN5_FN, PTN5_OUT, PTN5_IN, 0,
@ -1821,9 +1821,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTN3_FN, PTN3_OUT, PTN3_IN, 0,
PTN2_FN, PTN2_OUT, PTN2_IN, 0,
PTN1_FN, PTN1_OUT, PTN1_IN, 0,
PTN0_FN, PTN0_OUT, PTN0_IN, 0 }
PTN0_FN, PTN0_OUT, PTN0_IN, 0 ))
},
{ PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
{ PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2, GROUP(
PTO7_FN, PTO7_OUT, PTO7_IN, 0,
PTO6_FN, PTO6_OUT, PTO6_IN, 0,
PTO5_FN, PTO5_OUT, PTO5_IN, 0,
@ -1831,10 +1831,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTO3_FN, PTO3_OUT, PTO3_IN, 0,
PTO2_FN, PTO2_OUT, PTO2_IN, 0,
PTO1_FN, PTO1_OUT, PTO1_IN, 0,
PTO0_FN, PTO0_OUT, PTO0_IN, 0 }
PTO0_FN, PTO0_OUT, PTO0_IN, 0 ))
},
#if 0 /* FIXME: Remove it? */
{ PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
{ PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2, GROUP(
0, 0, 0, 0, /* reserved: always set 1 */
PTP6_FN, PTP6_OUT, PTP6_IN, 0,
PTP5_FN, PTP5_OUT, PTP5_IN, 0,
@ -1842,10 +1842,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTP3_FN, PTP3_OUT, PTP3_IN, 0,
PTP2_FN, PTP2_OUT, PTP2_IN, 0,
PTP1_FN, PTP1_OUT, PTP1_IN, 0,
PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
PTP0_FN, PTP0_OUT, PTP0_IN, 0 ))
},
#endif
{ PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
{ PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2, GROUP(
0, 0, 0, 0, /* reserved: always set 1 */
PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
@ -1853,9 +1853,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 }
PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 ))
},
{ PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) {
{ PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2, GROUP(
PTR7_FN, PTR7_OUT, PTR7_IN, 0,
PTR6_FN, PTR6_OUT, PTR6_IN, 0,
PTR5_FN, PTR5_OUT, PTR5_IN, 0,
@ -1863,9 +1863,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTR3_FN, PTR3_OUT, PTR3_IN, 0,
PTR2_FN, PTR2_OUT, PTR2_IN, 0,
PTR1_FN, PTR1_OUT, PTR1_IN, 0,
PTR0_FN, PTR0_OUT, PTR0_IN, 0 }
PTR0_FN, PTR0_OUT, PTR0_IN, 0 ))
},
{ PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) {
{ PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2, GROUP(
PTS7_FN, PTS7_OUT, PTS7_IN, 0,
PTS6_FN, PTS6_OUT, PTS6_IN, 0,
PTS5_FN, PTS5_OUT, PTS5_IN, 0,
@ -1873,9 +1873,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTS3_FN, PTS3_OUT, PTS3_IN, 0,
PTS2_FN, PTS2_OUT, PTS2_IN, 0,
PTS1_FN, PTS1_OUT, PTS1_IN, 0,
PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
PTS0_FN, PTS0_OUT, PTS0_IN, 0 ))
},
{ PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
{ PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2, GROUP(
PTT7_FN, PTT7_OUT, PTT7_IN, 0,
PTT6_FN, PTT6_OUT, PTT6_IN, 0,
PTT5_FN, PTT5_OUT, PTT5_IN, 0,
@ -1883,9 +1883,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTT3_FN, PTT3_OUT, PTT3_IN, 0,
PTT2_FN, PTT2_OUT, PTT2_IN, 0,
PTT1_FN, PTT1_OUT, PTT1_IN, 0,
PTT0_FN, PTT0_OUT, PTT0_IN, 0 }
PTT0_FN, PTT0_OUT, PTT0_IN, 0 ))
},
{ PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
{ PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2, GROUP(
PTU7_FN, PTU7_OUT, PTU7_IN, 0,
PTU6_FN, PTU6_OUT, PTU6_IN, 0,
PTU5_FN, PTU5_OUT, PTU5_IN, 0,
@ -1893,9 +1893,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTU3_FN, PTU3_OUT, PTU3_IN, 0,
PTU2_FN, PTU2_OUT, PTU2_IN, 0,
PTU1_FN, PTU1_OUT, PTU1_IN, 0,
PTU0_FN, PTU0_OUT, PTU0_IN, 0 }
PTU0_FN, PTU0_OUT, PTU0_IN, 0 ))
},
{ PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) {
{ PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2, GROUP(
PTV7_FN, PTV7_OUT, PTV7_IN, 0,
PTV6_FN, PTV6_OUT, PTV6_IN, 0,
PTV5_FN, PTV5_OUT, PTV5_IN, 0,
@ -1903,9 +1903,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTV3_FN, PTV3_OUT, PTV3_IN, 0,
PTV2_FN, PTV2_OUT, PTV2_IN, 0,
PTV1_FN, PTV1_OUT, PTV1_IN, 0,
PTV0_FN, PTV0_OUT, PTV0_IN, 0 }
PTV0_FN, PTV0_OUT, PTV0_IN, 0 ))
},
{ PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
{ PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2, GROUP(
PTW7_FN, PTW7_OUT, PTW7_IN, 0,
PTW6_FN, PTW6_OUT, PTW6_IN, 0,
PTW5_FN, PTW5_OUT, PTW5_IN, 0,
@ -1913,9 +1913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTW3_FN, PTW3_OUT, PTW3_IN, 0,
PTW2_FN, PTW2_OUT, PTW2_IN, 0,
PTW1_FN, PTW1_OUT, PTW1_IN, 0,
PTW0_FN, PTW0_OUT, PTW0_IN, 0 }
PTW0_FN, PTW0_OUT, PTW0_IN, 0 ))
},
{ PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) {
{ PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2, GROUP(
PTX7_FN, PTX7_OUT, PTX7_IN, 0,
PTX6_FN, PTX6_OUT, PTX6_IN, 0,
PTX5_FN, PTX5_OUT, PTX5_IN, 0,
@ -1923,9 +1923,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTX3_FN, PTX3_OUT, PTX3_IN, 0,
PTX2_FN, PTX2_OUT, PTX2_IN, 0,
PTX1_FN, PTX1_OUT, PTX1_IN, 0,
PTX0_FN, PTX0_OUT, PTX0_IN, 0 }
PTX0_FN, PTX0_OUT, PTX0_IN, 0 ))
},
{ PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) {
{ PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2, GROUP(
PTY7_FN, PTY7_OUT, PTY7_IN, 0,
PTY6_FN, PTY6_OUT, PTY6_IN, 0,
PTY5_FN, PTY5_OUT, PTY5_IN, 0,
@ -1933,9 +1933,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTY3_FN, PTY3_OUT, PTY3_IN, 0,
PTY2_FN, PTY2_OUT, PTY2_IN, 0,
PTY1_FN, PTY1_OUT, PTY1_IN, 0,
PTY0_FN, PTY0_OUT, PTY0_IN, 0 }
PTY0_FN, PTY0_OUT, PTY0_IN, 0 ))
},
{ PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
{ PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2, GROUP(
PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
@ -1943,10 +1943,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 }
PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 ))
},
{ PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
{ PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1, GROUP(
PS0_15_FN1, PS0_15_FN2,
PS0_14_FN1, PS0_14_FN2,
PS0_13_FN1, PS0_13_FN2,
@ -1962,9 +1962,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS0_3_FN1, PS0_3_FN2,
PS0_2_FN1, PS0_2_FN2,
0, 0,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
{ PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -1980,9 +1980,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
PS1_2_FN1, PS1_2_FN2,
0, 0,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
{ PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1, GROUP(
0, 0,
0, 0,
PS2_13_FN1, PS2_13_FN2,
@ -1998,9 +1998,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
PS2_2_FN1, PS2_2_FN2,
0, 0,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) {
{ PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1, GROUP(
PS3_15_FN1, PS3_15_FN2,
PS3_14_FN1, PS3_14_FN2,
PS3_13_FN1, PS3_13_FN2,
@ -2016,10 +2016,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
PS3_2_FN1, PS3_2_FN2,
PS3_1_FN1, PS3_1_FN2,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
{ PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1, GROUP(
0, 0,
PS4_14_FN1, PS4_14_FN2,
PS4_13_FN1, PS4_13_FN2,
@ -2035,9 +2035,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS4_3_FN1, PS4_3_FN2,
PS4_2_FN1, PS4_2_FN2,
PS4_1_FN1, PS4_1_FN2,
PS4_0_FN1, PS4_0_FN2, }
PS4_0_FN1, PS4_0_FN2, ))
},
{ PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
{ PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -2053,9 +2053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS5_3_FN1, PS5_3_FN2,
PS5_2_FN1, PS5_2_FN2,
0, 0,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
{ PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1, GROUP(
PS6_15_FN1, PS6_15_FN2,
PS6_14_FN1, PS6_14_FN2,
PS6_13_FN1, PS6_13_FN2,
@ -2071,9 +2071,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PS6_3_FN1, PS6_3_FN2,
PS6_2_FN1, PS6_2_FN2,
PS6_1_FN1, PS6_1_FN2,
PS6_0_FN1, PS6_0_FN2, }
PS6_0_FN1, PS6_0_FN2, ))
},
{ PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) {
{ PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1, GROUP(
PS7_15_FN1, PS7_15_FN2,
PS7_14_FN1, PS7_14_FN2,
PS7_13_FN1, PS7_13_FN2,
@ -2089,9 +2089,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
0, 0, }
0, 0, ))
},
{ PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) {
{ PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1, GROUP(
PS8_15_FN1, PS8_15_FN2,
PS8_14_FN1, PS8_14_FN2,
PS8_13_FN1, PS8_13_FN2,
@ -2107,115 +2107,115 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
0, 0,
0, 0,
0, 0, }
0, 0, ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
{ PINMUX_DATA_REG("PADR", 0xffec0034, 8, GROUP(
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xffec0036, 8) {
{ PINMUX_DATA_REG("PBDR", 0xffec0036, 8, GROUP(
PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xffec0038, 8) {
{ PINMUX_DATA_REG("PCDR", 0xffec0038, 8, GROUP(
PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xffec003a, 8) {
{ PINMUX_DATA_REG("PDDR", 0xffec003a, 8, GROUP(
PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xffec003c, 8) {
{ PINMUX_DATA_REG("PEDR", 0xffec003c, 8, GROUP(
PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR", 0xffec003e, 8) {
{ PINMUX_DATA_REG("PFDR", 0xffec003e, 8, GROUP(
PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xffec0040, 8) {
{ PINMUX_DATA_REG("PGDR", 0xffec0040, 8, GROUP(
PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA ))
},
{ PINMUX_DATA_REG("PHDR", 0xffec0042, 8) {
{ PINMUX_DATA_REG("PHDR", 0xffec0042, 8, GROUP(
PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA ))
},
{ PINMUX_DATA_REG("PIDR", 0xffec0044, 8) {
{ PINMUX_DATA_REG("PIDR", 0xffec0044, 8, GROUP(
PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
{ PINMUX_DATA_REG("PJDR", 0xffec0046, 8, GROUP(
0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA ))
},
{ PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
{ PINMUX_DATA_REG("PKDR", 0xffec0048, 8, GROUP(
PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA ))
},
{ PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
{ PINMUX_DATA_REG("PLDR", 0xffec004a, 8, GROUP(
0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA ))
},
{ PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
{ PINMUX_DATA_REG("PMDR", 0xffec004c, 8, GROUP(
PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA ))
},
{ PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
{ PINMUX_DATA_REG("PNDR", 0xffec004e, 8, GROUP(
0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA ))
},
{ PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
{ PINMUX_DATA_REG("PODR", 0xffec0050, 8, GROUP(
PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA ))
},
{ PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
{ PINMUX_DATA_REG("PPDR", 0xffec0052, 8, GROUP(
PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA ))
},
{ PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
{ PINMUX_DATA_REG("PQDR", 0xffec0054, 8, GROUP(
0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA ))
},
{ PINMUX_DATA_REG("PRDR", 0xffec0056, 8) {
{ PINMUX_DATA_REG("PRDR", 0xffec0056, 8, GROUP(
PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA ))
},
{ PINMUX_DATA_REG("PSDR", 0xffec0058, 8) {
{ PINMUX_DATA_REG("PSDR", 0xffec0058, 8, GROUP(
PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA ))
},
{ PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
{ PINMUX_DATA_REG("PTDR", 0xffec005a, 8, GROUP(
PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA ))
},
{ PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
{ PINMUX_DATA_REG("PUDR", 0xffec005c, 8, GROUP(
PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA ))
},
{ PINMUX_DATA_REG("PVDR", 0xffec005e, 8) {
{ PINMUX_DATA_REG("PVDR", 0xffec005e, 8, GROUP(
PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
},
{ PINMUX_DATA_REG("PWDR", 0xffec0060, 8) {
{ PINMUX_DATA_REG("PWDR", 0xffec0060, 8, GROUP(
PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA ))
},
{ PINMUX_DATA_REG("PXDR", 0xffec0062, 8) {
{ PINMUX_DATA_REG("PXDR", 0xffec0062, 8, GROUP(
PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA ))
},
{ PINMUX_DATA_REG("PYDR", 0xffec0064, 8) {
{ PINMUX_DATA_REG("PYDR", 0xffec0064, 8, GROUP(
PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA ))
},
{ PINMUX_DATA_REG("PZDR", 0xffec0066, 8) {
{ PINMUX_DATA_REG("PZDR", 0xffec0066, 8, GROUP(
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
},
{ },
};

136
drivers/pinctrl/sh-pfc/pfc-sh7785.c
View File

@ -985,7 +985,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2, GROUP(
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
@ -993,9 +993,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PA3_FN, PA3_OUT, PA3_IN, 0,
PA2_FN, PA2_OUT, PA2_IN, 0,
PA1_FN, PA1_OUT, PA1_IN, 0,
PA0_FN, PA0_OUT, PA0_IN, 0 }
PA0_FN, PA0_OUT, PA0_IN, 0 ))
},
{ PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) {
{ PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2, GROUP(
PB7_FN, PB7_OUT, PB7_IN, 0,
PB6_FN, PB6_OUT, PB6_IN, 0,
PB5_FN, PB5_OUT, PB5_IN, 0,
@ -1003,9 +1003,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB3_FN, PB3_OUT, PB3_IN, 0,
PB2_FN, PB2_OUT, PB2_IN, 0,
PB1_FN, PB1_OUT, PB1_IN, 0,
PB0_FN, PB0_OUT, PB0_IN, 0 }
PB0_FN, PB0_OUT, PB0_IN, 0 ))
},
{ PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) {
{ PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2, GROUP(
PC7_FN, PC7_OUT, PC7_IN, 0,
PC6_FN, PC6_OUT, PC6_IN, 0,
PC5_FN, PC5_OUT, PC5_IN, 0,
@ -1013,9 +1013,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC3_FN, PC3_OUT, PC3_IN, 0,
PC2_FN, PC2_OUT, PC2_IN, 0,
PC1_FN, PC1_OUT, PC1_IN, 0,
PC0_FN, PC0_OUT, PC0_IN, 0 }
PC0_FN, PC0_OUT, PC0_IN, 0 ))
},
{ PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) {
{ PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2, GROUP(
PD7_FN, PD7_OUT, PD7_IN, 0,
PD6_FN, PD6_OUT, PD6_IN, 0,
PD5_FN, PD5_OUT, PD5_IN, 0,
@ -1023,9 +1023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD3_FN, PD3_OUT, PD3_IN, 0,
PD2_FN, PD2_OUT, PD2_IN, 0,
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0 }
PD0_FN, PD0_OUT, PD0_IN, 0 ))
},
{ PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) {
{ PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PE5_FN, PE5_OUT, PE5_IN, 0,
@ -1033,9 +1033,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PE3_FN, PE3_OUT, PE3_IN, 0,
PE2_FN, PE2_OUT, PE2_IN, 0,
PE1_FN, PE1_OUT, PE1_IN, 0,
PE0_FN, PE0_OUT, PE0_IN, 0 }
PE0_FN, PE0_OUT, PE0_IN, 0 ))
},
{ PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) {
{ PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2, GROUP(
PF7_FN, PF7_OUT, PF7_IN, 0,
PF6_FN, PF6_OUT, PF6_IN, 0,
PF5_FN, PF5_OUT, PF5_IN, 0,
@ -1043,9 +1043,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF3_FN, PF3_OUT, PF3_IN, 0,
PF2_FN, PF2_OUT, PF2_IN, 0,
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0 }
PF0_FN, PF0_OUT, PF0_IN, 0 ))
},
{ PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) {
{ PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2, GROUP(
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
@ -1053,9 +1053,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PG3_FN, PG3_OUT, PG3_IN, 0,
PG2_FN, PG2_OUT, PG2_IN, 0,
PG1_FN, PG1_OUT, PG1_IN, 0,
PG0_FN, PG0_OUT, PG0_IN, 0 }
PG0_FN, PG0_OUT, PG0_IN, 0 ))
},
{ PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) {
{ PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2, GROUP(
PH7_FN, PH7_OUT, PH7_IN, 0,
PH6_FN, PH6_OUT, PH6_IN, 0,
PH5_FN, PH5_OUT, PH5_IN, 0,
@ -1063,9 +1063,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PH3_FN, PH3_OUT, PH3_IN, 0,
PH2_FN, PH2_OUT, PH2_IN, 0,
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0 }
PH0_FN, PH0_OUT, PH0_IN, 0 ))
},
{ PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) {
{ PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2, GROUP(
PJ7_FN, PJ7_OUT, PJ7_IN, 0,
PJ6_FN, PJ6_OUT, PJ6_IN, 0,
PJ5_FN, PJ5_OUT, PJ5_IN, 0,
@ -1073,9 +1073,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ3_FN, PJ3_OUT, PJ3_IN, 0,
PJ2_FN, PJ2_OUT, PJ2_IN, 0,
PJ1_FN, PJ1_OUT, PJ1_IN, 0,
PJ0_FN, PJ0_OUT, PJ0_IN, 0 }
PJ0_FN, PJ0_OUT, PJ0_IN, 0 ))
},
{ PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) {
{ PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2, GROUP(
PK7_FN, PK7_OUT, PK7_IN, 0,
PK6_FN, PK6_OUT, PK6_IN, 0,
PK5_FN, PK5_OUT, PK5_IN, 0,
@ -1083,9 +1083,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PK3_FN, PK3_OUT, PK3_IN, 0,
PK2_FN, PK2_OUT, PK2_IN, 0,
PK1_FN, PK1_OUT, PK1_IN, 0,
PK0_FN, PK0_OUT, PK0_IN, 0 }
PK0_FN, PK0_OUT, PK0_IN, 0 ))
},
{ PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) {
{ PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2, GROUP(
PL7_FN, PL7_OUT, PL7_IN, 0,
PL6_FN, PL6_OUT, PL6_IN, 0,
PL5_FN, PL5_OUT, PL5_IN, 0,
@ -1093,9 +1093,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PL3_FN, PL3_OUT, PL3_IN, 0,
PL2_FN, PL2_OUT, PL2_IN, 0,
PL1_FN, PL1_OUT, PL1_IN, 0,
PL0_FN, PL0_OUT, PL0_IN, 0 }
PL0_FN, PL0_OUT, PL0_IN, 0 ))
},
{ PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) {
{ PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1103,9 +1103,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
PM1_FN, PM1_OUT, PM1_IN, 0,
PM0_FN, PM0_OUT, PM0_IN, 0 }
PM0_FN, PM0_OUT, PM0_IN, 0 ))
},
{ PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) {
{ PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2, GROUP(
PN7_FN, PN7_OUT, PN7_IN, 0,
PN6_FN, PN6_OUT, PN6_IN, 0,
PN5_FN, PN5_OUT, PN5_IN, 0,
@ -1113,9 +1113,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PN3_FN, PN3_OUT, PN3_IN, 0,
PN2_FN, PN2_OUT, PN2_IN, 0,
PN1_FN, PN1_OUT, PN1_IN, 0,
PN0_FN, PN0_OUT, PN0_IN, 0 }
PN0_FN, PN0_OUT, PN0_IN, 0 ))
},
{ PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) {
{ PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
PP5_FN, PP5_OUT, PP5_IN, 0,
@ -1123,9 +1123,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PP3_FN, PP3_OUT, PP3_IN, 0,
PP2_FN, PP2_OUT, PP2_IN, 0,
PP1_FN, PP1_OUT, PP1_IN, 0,
PP0_FN, PP0_OUT, PP0_IN, 0 }
PP0_FN, PP0_OUT, PP0_IN, 0 ))
},
{ PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) {
{ PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1133,9 +1133,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PQ3_FN, PQ3_OUT, PQ3_IN, 0,
PQ2_FN, PQ2_OUT, PQ2_IN, 0,
PQ1_FN, PQ1_OUT, PQ1_IN, 0,
PQ0_FN, PQ0_OUT, PQ0_IN, 0 }
PQ0_FN, PQ0_OUT, PQ0_IN, 0 ))
},
{ PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) {
{ PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2, GROUP(
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
@ -1143,9 +1143,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PR3_FN, PR3_OUT, PR3_IN, 0,
PR2_FN, PR2_OUT, PR2_IN, 0,
PR1_FN, PR1_OUT, PR1_IN, 0,
PR0_FN, PR0_OUT, PR0_IN, 0 }
PR0_FN, PR0_OUT, PR0_IN, 0 ))
},
{ PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) {
{ PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1, GROUP(
P1MSEL15_0, P1MSEL15_1,
P1MSEL14_0, P1MSEL14_1,
P1MSEL13_0, P1MSEL13_1,
@ -1161,9 +1161,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
P1MSEL3_0, P1MSEL3_1,
P1MSEL2_0, P1MSEL2_1,
P1MSEL1_0, P1MSEL1_1,
P1MSEL0_0, P1MSEL0_1 }
P1MSEL0_0, P1MSEL0_1 ))
},
{ PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1) {
{ PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1, GROUP(
0, 0,
0, 0,
0, 0,
@ -1179,75 +1179,75 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0,
P2MSEL2_0, P2MSEL2_1,
P2MSEL1_0, P2MSEL1_1,
P2MSEL0_0, P2MSEL0_1 }
P2MSEL0_0, P2MSEL0_1 ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffe70020, 8) {
{ PINMUX_DATA_REG("PADR", 0xffe70020, 8, GROUP(
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xffe70022, 8) {
{ PINMUX_DATA_REG("PBDR", 0xffe70022, 8, GROUP(
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xffe70024, 8) {
{ PINMUX_DATA_REG("PCDR", 0xffe70024, 8, GROUP(
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xffe70026, 8) {
{ PINMUX_DATA_REG("PDDR", 0xffe70026, 8, GROUP(
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xffe70028, 8) {
{ PINMUX_DATA_REG("PEDR", 0xffe70028, 8, GROUP(
0, 0, PE5_DATA, PE4_DATA,
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA ))
},
{ PINMUX_DATA_REG("PFDR", 0xffe7002a, 8) {
{ PINMUX_DATA_REG("PFDR", 0xffe7002a, 8, GROUP(
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xffe7002c, 8) {
{ PINMUX_DATA_REG("PGDR", 0xffe7002c, 8, GROUP(
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA ))
},
{ PINMUX_DATA_REG("PHDR", 0xffe7002e, 8) {
{ PINMUX_DATA_REG("PHDR", 0xffe7002e, 8, GROUP(
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xffe70030, 8) {
{ PINMUX_DATA_REG("PJDR", 0xffe70030, 8, GROUP(
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
},
{ PINMUX_DATA_REG("PKDR", 0xffe70032, 8) {
{ PINMUX_DATA_REG("PKDR", 0xffe70032, 8, GROUP(
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
},
{ PINMUX_DATA_REG("PLDR", 0xffe70034, 8) {
{ PINMUX_DATA_REG("PLDR", 0xffe70034, 8, GROUP(
PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA,
PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA }
PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA ))
},
{ PINMUX_DATA_REG("PMDR", 0xffe70036, 8) {
{ PINMUX_DATA_REG("PMDR", 0xffe70036, 8, GROUP(
0, 0, 0, 0,
0, 0, PM1_DATA, PM0_DATA }
0, 0, PM1_DATA, PM0_DATA ))
},
{ PINMUX_DATA_REG("PNDR", 0xffe70038, 8) {
{ PINMUX_DATA_REG("PNDR", 0xffe70038, 8, GROUP(
PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA,
PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA }
PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA ))
},
{ PINMUX_DATA_REG("PPDR", 0xffe7003a, 8) {
{ PINMUX_DATA_REG("PPDR", 0xffe7003a, 8, GROUP(
0, 0, PP5_DATA, PP4_DATA,
PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA }
PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA ))
},
{ PINMUX_DATA_REG("PQDR", 0xffe7003c, 8) {
{ PINMUX_DATA_REG("PQDR", 0xffe7003c, 8, GROUP(
0, 0, 0, PQ4_DATA,
PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA }
PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA ))
},
{ PINMUX_DATA_REG("PRDR", 0xffe7003e, 8) {
{ PINMUX_DATA_REG("PRDR", 0xffe7003e, 8, GROUP(
0, 0, 0, 0,
PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA }
PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA ))
},
{ },
};

80
drivers/pinctrl/sh-pfc/pfc-sh7786.c
View File

@ -627,7 +627,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP(
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
@ -635,9 +635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PA3_FN, PA3_OUT, PA3_IN, 0,
PA2_FN, PA2_OUT, PA2_IN, 0,
PA1_FN, PA1_OUT, PA1_IN, 0,
PA0_FN, PA0_OUT, PA0_IN, 0 }
PA0_FN, PA0_OUT, PA0_IN, 0 ))
},
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP(
PB7_FN, PB7_OUT, PB7_IN, 0,
PB6_FN, PB6_OUT, PB6_IN, 0,
PB5_FN, PB5_OUT, PB5_IN, 0,
@ -645,9 +645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB3_FN, PB3_OUT, PB3_IN, 0,
PB2_FN, PB2_OUT, PB2_IN, 0,
PB1_FN, PB1_OUT, PB1_IN, 0,
PB0_FN, PB0_OUT, PB0_IN, 0 }
PB0_FN, PB0_OUT, PB0_IN, 0 ))
},
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP(
PC7_FN, PC7_OUT, PC7_IN, 0,
PC6_FN, PC6_OUT, PC6_IN, 0,
PC5_FN, PC5_OUT, PC5_IN, 0,
@ -655,9 +655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PC3_FN, PC3_OUT, PC3_IN, 0,
PC2_FN, PC2_OUT, PC2_IN, 0,
PC1_FN, PC1_OUT, PC1_IN, 0,
PC0_FN, PC0_OUT, PC0_IN, 0 }
PC0_FN, PC0_OUT, PC0_IN, 0 ))
},
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP(
PD7_FN, PD7_OUT, PD7_IN, 0,
PD6_FN, PD6_OUT, PD6_IN, 0,
PD5_FN, PD5_OUT, PD5_IN, 0,
@ -665,9 +665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD3_FN, PD3_OUT, PD3_IN, 0,
PD2_FN, PD2_OUT, PD2_IN, 0,
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0 }
PD0_FN, PD0_OUT, PD0_IN, 0 ))
},
{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP(
PE7_FN, PE7_OUT, PE7_IN, 0,
PE6_FN, PE6_OUT, PE6_IN, 0,
0, 0, 0, 0,
@ -675,9 +675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP(
PF7_FN, PF7_OUT, PF7_IN, 0,
PF6_FN, PF6_OUT, PF6_IN, 0,
PF5_FN, PF5_OUT, PF5_IN, 0,
@ -685,9 +685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF3_FN, PF3_OUT, PF3_IN, 0,
PF2_FN, PF2_OUT, PF2_IN, 0,
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0 }
PF0_FN, PF0_OUT, PF0_IN, 0 ))
},
{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP(
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
@ -695,9 +695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP(
PH7_FN, PH7_OUT, PH7_IN, 0,
PH6_FN, PH6_OUT, PH6_IN, 0,
PH5_FN, PH5_OUT, PH5_IN, 0,
@ -705,9 +705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PH3_FN, PH3_OUT, PH3_IN, 0,
PH2_FN, PH2_OUT, PH2_IN, 0,
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0 }
PH0_FN, PH0_OUT, PH0_IN, 0 ))
},
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP(
PJ7_FN, PJ7_OUT, PJ7_IN, 0,
PJ6_FN, PJ6_OUT, PJ6_IN, 0,
PJ5_FN, PJ5_OUT, PJ5_IN, 0,
@ -715,9 +715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PJ3_FN, PJ3_OUT, PJ3_IN, 0,
PJ2_FN, PJ2_OUT, PJ2_IN, 0,
PJ1_FN, PJ1_OUT, PJ1_IN, 0,
0, 0, 0, 0, }
0, 0, 0, 0, ))
},
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP(
0, 0,
P1MSEL14_0, P1MSEL14_1,
P1MSEL13_0, P1MSEL13_1,
@ -733,9 +733,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
P1MSEL3_0, P1MSEL3_1,
P1MSEL2_0, P1MSEL2_1,
P1MSEL1_0, P1MSEL1_1,
P1MSEL0_0, P1MSEL0_1 }
P1MSEL0_0, P1MSEL0_1 ))
},
{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP(
P2MSEL15_0, P2MSEL15_1,
P2MSEL14_0, P2MSEL14_1,
P2MSEL13_0, P2MSEL13_1,
@ -751,47 +751,47 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
P2MSEL3_0, P2MSEL3_1,
P2MSEL2_0, P2MSEL2_1,
P2MSEL1_0, P2MSEL1_1,
P2MSEL0_0, P2MSEL0_1 }
P2MSEL0_0, P2MSEL0_1 ))
},
{}
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP(
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
},
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP(
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
},
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP(
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
},
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP(
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
},
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP(
PE7_DATA, PE6_DATA,
0, 0, 0, 0, 0, 0 }
0, 0, 0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP(
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
},
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP(
PG7_DATA, PG6_DATA, PG5_DATA, 0,
0, 0, 0, 0 }
0, 0, 0, 0 ))
},
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP(
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
},
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP(
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
},
{ },
};

32
drivers/pinctrl/sh-pfc/pfc-shx3.c
View File

@ -431,7 +431,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2, GROUP(
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
@ -447,9 +447,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PB3_FN, PB3_OUT, PB3_IN, 0,
PB2_FN, PB2_OUT, PB2_IN, 0,
PB1_FN, PB1_OUT, PB1_IN, 0,
PB0_FN, PB0_OUT, PB0_IN, 0, },
PB0_FN, PB0_OUT, PB0_IN, 0, ))
},
{ PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
{ PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2, GROUP(
PC7_FN, PC7_OUT, PC7_IN, 0,
PC6_FN, PC6_OUT, PC6_IN, 0,
PC5_FN, PC5_OUT, PC5_IN, 0,
@ -465,9 +465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PD3_FN, PD3_OUT, PD3_IN, 0,
PD2_FN, PD2_OUT, PD2_IN, 0,
PD1_FN, PD1_OUT, PD1_IN, 0,
PD0_FN, PD0_OUT, PD0_IN, 0, },
PD0_FN, PD0_OUT, PD0_IN, 0, ))
},
{ PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
{ PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2, GROUP(
PE7_FN, PE7_OUT, PE7_IN, 0,
PE6_FN, PE6_OUT, PE6_IN, 0,
PE5_FN, PE5_OUT, PE5_IN, 0,
@ -483,9 +483,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PF3_FN, PF3_OUT, PF3_IN, 0,
PF2_FN, PF2_OUT, PF2_IN, 0,
PF1_FN, PF1_OUT, PF1_IN, 0,
PF0_FN, PF0_OUT, PF0_IN, 0, },
PF0_FN, PF0_OUT, PF0_IN, 0, ))
},
{ PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
{ PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2, GROUP(
PG7_FN, PG7_OUT, PG7_IN, 0,
PG6_FN, PG6_OUT, PG6_IN, 0,
PG5_FN, PG5_OUT, PG5_IN, 0,
@ -501,43 +501,43 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PH3_FN, PH3_OUT, PH3_IN, 0,
PH2_FN, PH2_OUT, PH2_IN, 0,
PH1_FN, PH1_OUT, PH1_IN, 0,
PH0_FN, PH0_OUT, PH0_IN, 0, },
PH0_FN, PH0_OUT, PH0_IN, 0, ))
},
{ },
};
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
0, 0, 0, 0, 0, 0, 0, 0,
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, ))
},
{ PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
{ PINMUX_DATA_REG("PCDDR", 0xffc70014, 32, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
0, 0, 0, 0, 0, 0, 0, 0,
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, ))
},
{ PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
{ PINMUX_DATA_REG("PEFDR", 0xffc70018, 32, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
0, 0, 0, 0, 0, 0, 0, 0,
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, ))
},
{ PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
{ PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32, GROUP(
0, 0, 0, 0, 0, 0, 0, 0,
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, PH5_DATA, PH4_DATA,
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, ))
},
{ },
};

68
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -111,40 +111,54 @@ struct pinmux_func {
struct pinmux_cfg_reg {
u32 reg;
u8 reg_width, field_width;
#ifdef DEBUG
u16 nr_enum_ids; /* for variable width regs only */
#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
#else
#define SET_NR_ENUM_IDS(n)
#endif
const u16 *enum_ids;
const u8 *var_field_width;
};
#define GROUP(...) __VA_ARGS__
/*
* Describe a config register consisting of several fields of the same width
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - f_width: Width of the fixed-width register fields (in bits)
* This macro must be followed by initialization data: For each register field
* (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
* one for each possible combination of the register field bit values.
* - ids: For each register field (from left to right, i.e. MSB to LSB),
* 2^f_width enum IDs must be specified, one for each possible
* combination of the register field bit values, all wrapped using
* the GROUP() macro.
*/
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
.reg = r, .reg_width = r_width, \
.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width), \
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
(r_width / f_width) * (1 << f_width)), \
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
{ ids }
/*
* Describe a config register consisting of several fields of different widths
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - var_fw0, var_fwn...: List of widths of the register fields (in bits),
* From left to right (i.e. MSB to LSB)
* This macro must be followed by initialization data: For each register field
* (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
* one for each possible combination of the register field bit values.
* - f_widths: List of widths of the register fields (in bits), from left
* to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
* - ids: For each register field (from left to right, i.e. MSB to LSB),
* 2^f_widths[i] enum IDs must be specified, one for each possible
* combination of the register field bit values, all wrapped using
* the GROUP() macro.
*/
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.var_field_width = (const u8 []) { var_fw0, var_fwn, 0 }, \
.enum_ids = (const u16 [])
#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
.reg = r, .reg_width = r_width, \
.var_field_width = (const u8 []) { f_widths, 0 }, \
SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
.enum_ids = (const u16 []) { ids }
struct pinmux_drive_reg_field {
u16 pin;
@ -187,12 +201,14 @@ struct pinmux_data_reg {
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* This macro must be followed by initialization data: For each register bit
* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
* - ids: For each register bit (from left to right, i.e. MSB to LSB), one
* enum ID must be specified, all wrapped using the GROUP() macro.
*/
#define PINMUX_DATA_REG(name, r, r_width) \
.reg = r, .reg_width = r_width, \
.enum_ids = (const u16 [r_width]) \
#define PINMUX_DATA_REG(name, r, r_width, ids) \
.reg = r, .reg_width = r_width + \
BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
r_width), \
.enum_ids = (const u16 [r_width]) { ids }
struct pinmux_irq {
const short *gpios;
@ -261,7 +277,7 @@ struct sh_pfc_soc_info {
const struct sh_pfc_function *functions;
unsigned int nr_functions;
#ifdef CONFIG_SUPERH
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
const struct pinmux_func *func_gpios;
unsigned int nr_func_gpios;
#endif
@ -402,8 +418,8 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
/*
* Describe a pinmux configuration in which a pin is physically multiplexed
* with other pins.
* - ipsr: IPSR field
* - fn: Function name, also referring to the IPSR field
* - ipsr: IPSR field (unused, for documentation purposes only)
* - fn: Function name
* - psel: Physical multiplexing selector
*/
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
@ -663,7 +679,9 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
*/
#define PORTCR(nr, reg) \
{ \
PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
GROUP(2, 2, 1, 3), \
GROUP( \
/* PULMD[1:0], handled by .set_bias() */ \
0, 0, 0, 0, \
/* IE and OE */ \
@ -675,7 +693,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 \
} \
)) \
}
/*

105
drivers/pinctrl/stm32/pinctrl-stm32.c
View File

@ -95,6 +95,9 @@ struct stm32_pinctrl {
struct regmap *regmap;
struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
struct hwspinlock *hwlock;
struct stm32_desc_pin *pins;
u32 npins;
u32 pkg;
};
static inline int stm32_gpio_pin(int gpio)
@ -358,8 +361,8 @@ static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
{
int i;
for (i = 0; i < pctl->match_data->npins; i++) {
const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
for (i = 0; i < pctl->npins; i++) {
const struct stm32_desc_pin *pin = pctl->pins + i;
const struct stm32_desc_function *func = pin->functions;
if (pin->pin.number != pin_num)
@ -1119,23 +1122,35 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
return 0;
}
static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
{
struct device_node *parent;
struct irq_domain *domain;
if (!of_find_property(np, "interrupt-parent", NULL))
return NULL;
parent = of_irq_find_parent(np);
if (!parent)
return ERR_PTR(-ENXIO);
domain = irq_find_host(parent);
if (!domain)
/* domain not registered yet */
return ERR_PTR(-EPROBE_DEFER);
return domain;
}
static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
struct stm32_pinctrl *pctl)
{
struct device_node *np = pdev->dev.of_node, *parent;
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct regmap *rm;
int offset, ret, i;
int mask, mask_width;
parent = of_irq_find_parent(np);
if (!parent)
return -ENXIO;
pctl->domain = irq_find_host(parent);
if (!pctl->domain)
return -ENXIO;
pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(pctl->regmap))
return PTR_ERR(pctl->regmap);
@ -1175,7 +1190,7 @@ static int stm32_pctrl_build_state(struct platform_device *pdev)
struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
int i;
pctl->ngroups = pctl->match_data->npins;
pctl->ngroups = pctl->npins;
/* Allocate groups */
pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
@ -1189,19 +1204,50 @@ static int stm32_pctrl_build_state(struct platform_device *pdev)
if (!pctl->grp_names)
return -ENOMEM;
for (i = 0; i < pctl->match_data->npins; i++) {
const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
for (i = 0; i < pctl->npins; i++) {
const struct stm32_desc_pin *pin = pctl->pins + i;
struct stm32_pinctrl_group *group = pctl->groups + i;
group->name = pin->pin.name;
group->pin = pin->pin.number;
pctl->grp_names[i] = pin->pin.name;
}
return 0;
}
static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
struct stm32_desc_pin *pins)
{
const struct stm32_desc_pin *p;
int i, nb_pins_available = 0;
for (i = 0; i < pctl->match_data->npins; i++) {
p = pctl->match_data->pins + i;
if (pctl->pkg && !(pctl->pkg & p->pkg))
continue;
pins->pin = p->pin;
pins->functions = p->functions;
pins++;
nb_pins_available++;
}
pctl->npins = nb_pins_available;
return 0;
}
static void stm32_pctl_get_package(struct device_node *np,
struct stm32_pinctrl *pctl)
{
if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
pctl->pkg = 0;
dev_warn(pctl->dev, "No package detected, use default one\n");
} else {
dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
}
}
int stm32_pctl_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@ -1230,6 +1276,11 @@ int stm32_pctl_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pctl);
/* check for IRQ controller (may require deferred probe) */
pctl->domain = stm32_pctrl_get_irq_domain(np);
if (IS_ERR(pctl->domain))
return PTR_ERR(pctl->domain);
/* hwspinlock is optional */
hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
if (hwlock_id < 0) {
@ -1241,30 +1292,43 @@ int stm32_pctl_probe(struct platform_device *pdev)
pctl->dev = dev;
pctl->match_data = match->data;
/* get package information */
stm32_pctl_get_package(np, pctl);
pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
sizeof(*pctl->pins), GFP_KERNEL);
if (!pctl->pins)
return -ENOMEM;
ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
if (ret)
return ret;
ret = stm32_pctrl_build_state(pdev);
if (ret) {
dev_err(dev, "build state failed: %d\n", ret);
return -EINVAL;
}
if (of_find_property(np, "interrupt-parent", NULL)) {
if (pctl->domain) {
ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
if (ret)
return ret;
}
pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < pctl->match_data->npins; i++)
pins[i] = pctl->match_data->pins[i].pin;
for (i = 0; i < pctl->npins; i++)
pins[i] = pctl->pins[i].pin;
pctl->pctl_desc.name = dev_name(&pdev->dev);
pctl->pctl_desc.owner = THIS_MODULE;
pctl->pctl_desc.pins = pins;
pctl->pctl_desc.npins = pctl->match_data->npins;
pctl->pctl_desc.npins = pctl->npins;
pctl->pctl_desc.confops = &stm32_pconf_ops;
pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
pctl->pctl_desc.pmxops = &stm32_pmx_ops;
@ -1305,4 +1369,3 @@ int stm32_pctl_probe(struct platform_device *pdev)
return 0;
}

14
drivers/pinctrl/stm32/pinctrl-stm32.h
View File

@ -18,6 +18,12 @@
#define STM32_PIN_AF(x) ((x) + 1)
#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1)
/* package information */
#define STM32MP_PKG_AA BIT(0)
#define STM32MP_PKG_AB BIT(1)
#define STM32MP_PKG_AC BIT(2)
#define STM32MP_PKG_AD BIT(3)
struct stm32_desc_function {
const char *name;
const unsigned char num;
@ -26,6 +32,7 @@ struct stm32_desc_function {
struct stm32_desc_pin {
struct pinctrl_pin_desc pin;
const struct stm32_desc_function *functions;
const unsigned int pkg;
};
#define STM32_PIN(_pin, ...) \
@ -35,6 +42,13 @@ struct stm32_desc_pin {
__VA_ARGS__, { } }, \
}
#define STM32_PIN_PKG(_pin, _pkg, ...) \
{ \
.pin = _pin, \
.pkg = _pkg, \
.functions = (struct stm32_desc_function[]){ \
__VA_ARGS__, { } }, \
}
#define STM32_FUNCTION(_num, _name) \
{ \
.num = _num, \

1089
drivers/pinctrl/stm32/pinctrl-stm32mp157.c
View File

File diff suppressed because it is too large Load Diff

57
drivers/pinctrl/sunxi/Kconfig
View File

@ -11,82 +11,101 @@ config PINCTRL_SUNIV_F1C100S
select PINCTRL_SUNXI
config PINCTRL_SUN4I_A10
def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
bool "Support for the Allwinner A10, A20 and R40 PIO"
default MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN5I
def_bool MACH_SUN5I
bool "Support for the Allwinner A10s, A13, R8 and NextThing GR8 PIO"
default MACH_SUN5I
select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31
def_bool MACH_SUN6I
bool "Support for the Allwinner A31 PIO"
default MACH_SUN6I
select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31_R
def_bool MACH_SUN6I
bool "Support for the Allwinner A31 R-PIO"
default MACH_SUN6I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
bool "Support for the Allwinner A23 PIO"
default MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A33
def_bool MACH_SUN8I
bool "Support for the Allwinner A33 PIO"
default MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A83T
def_bool MACH_SUN8I
bool "Support for the Allwinner A83T PIO"
default MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A83T_R
def_bool MACH_SUN8I
bool "Support for the Allwinner A83T R-PIO"
default MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
bool "Support for the Allwinner A23 and A33 R-PIO"
default MACH_SUN8I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
config PINCTRL_SUN8I_H3
def_bool MACH_SUN8I
bool "Support for the Allwinner H3 PIO"
default MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN8I_H3_R
def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI)
bool "Support for the Allwinner H3 and H5 R-PIO"
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
select PINCTRL_SUNXI
config PINCTRL_SUN8I_V3S
def_bool MACH_SUN8I
bool "Support for the Allwinner V3s PIO"
default MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN9I_A80
def_bool MACH_SUN9I
bool "Support for the Allwinner A80 PIO"
default MACH_SUN9I
select PINCTRL_SUNXI
config PINCTRL_SUN9I_A80_R
def_bool MACH_SUN9I
bool "Support for the Allwinner A80 R-PIO"
default MACH_SUN9I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI
config PINCTRL_SUN50I_A64
def_bool ARM64 && ARCH_SUNXI
bool "Support for the Allwinner A64 PIO"
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
config PINCTRL_SUN50I_A64_R
def_bool ARM64 && ARCH_SUNXI
bool "Support for the Allwinner A64 R-PIO"
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
config PINCTRL_SUN50I_H5
def_bool ARM64 && ARCH_SUNXI
bool "Support for the Allwinner H5 PIO"
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
config PINCTRL_SUN50I_H6
def_bool ARM64 && ARCH_SUNXI
bool "Support for the Allwinner H6 PIO"
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
config PINCTRL_SUN50I_H6_R
def_bool ARM64 && ARCH_SUNXI
bool "Support for the Allwinner H6 R-PIO"
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
endif

1
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
View File

@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
.irq_banks = 4,
.irq_bank_map = h6_irq_bank_map,
.irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};
static int h6_pinctrl_probe(struct platform_device *pdev)

2
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
View File

@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
.pin_base = PL_BASE,
.irq_banks = 2,
.disable_strict_mode = true,
.has_io_bias_cfg = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
};
static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)

2
drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
View File

@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
.npins = ARRAY_SIZE(sun9i_a80_pins),
.irq_banks = 5,
.disable_strict_mode = true,
.has_io_bias_cfg = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
};
static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)

92
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -530,14 +530,10 @@ static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
return sunxi_pconf_get(pctldev, g->pin, config);
}
static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long *configs,
unsigned num_configs)
static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, unsigned num_configs)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = &pctl->groups[group];
unsigned pin = g->pin - pctl->desc->pin_base;
int i;
for (i = 0; i < num_configs; i++) {
@ -596,9 +592,20 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
return 0;
}
static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *configs, unsigned num_configs)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = &pctl->groups[group];
/* We only support 1 pin per group. Chain it to the pin callback */
return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
}
static const struct pinconf_ops sunxi_pconf_ops = {
.is_generic = true,
.pin_config_get = sunxi_pconf_get,
.pin_config_set = sunxi_pconf_set,
.pin_config_group_get = sunxi_pconf_group_get,
.pin_config_group_set = sunxi_pconf_group_set,
};
@ -607,10 +614,12 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
unsigned pin,
struct regulator *supply)
{
unsigned short bank = pin / PINS_PER_BANK;
unsigned long flags;
u32 val, reg;
int uV;
if (!pctl->desc->has_io_bias_cfg)
if (!pctl->desc->io_bias_cfg_variant)
return 0;
uV = regulator_get_voltage(supply);
@ -621,25 +630,41 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
if (uV == 0)
return 0;
/* Configured value must be equal or greater to actual voltage */
if (uV <= 1800000)
val = 0x0; /* 1.8V */
else if (uV <= 2500000)
val = 0x6; /* 2.5V */
else if (uV <= 2800000)
val = 0x9; /* 2.8V */
else if (uV <= 3000000)
val = 0xA; /* 3.0V */
else
val = 0xD; /* 3.3V */
switch (pctl->desc->io_bias_cfg_variant) {
case BIAS_VOLTAGE_GRP_CONFIG:
/*
* Configured value must be equal or greater to actual
* voltage.
*/
if (uV <= 1800000)
val = 0x0; /* 1.8V */
else if (uV <= 2500000)
val = 0x6; /* 2.5V */
else if (uV <= 2800000)
val = 0x9; /* 2.8V */
else if (uV <= 3000000)
val = 0xA; /* 3.0V */
else
val = 0xD; /* 3.3V */
pin -= pctl->desc->pin_base;
pin -= pctl->desc->pin_base;
reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
reg &= ~IO_BIAS_MASK;
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
reg &= ~IO_BIAS_MASK;
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
return 0;
case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
val = uV <= 1800000 ? 1 : 0;
return 0;
raw_spin_lock_irqsave(&pctl->lock, flags);
reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
reg &= ~(1 << bank);
writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
raw_spin_unlock_irqrestore(&pctl->lock, flags);
return 0;
default:
return -EINVAL;
}
}
static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
@ -1443,16 +1468,17 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
pctl->chip->owner = THIS_MODULE;
pctl->chip->request = gpiochip_generic_request,
pctl->chip->free = gpiochip_generic_free,
pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
pctl->chip->get = sunxi_pinctrl_gpio_get,
pctl->chip->set = sunxi_pinctrl_gpio_set,
pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
pctl->chip->of_gpio_n_cells = 3,
pctl->chip->can_sleep = false,
pctl->chip->request = gpiochip_generic_request;
pctl->chip->free = gpiochip_generic_free;
pctl->chip->set_config = gpiochip_generic_config;
pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
pctl->chip->get = sunxi_pinctrl_gpio_get;
pctl->chip->set = sunxi_pinctrl_gpio_set;
pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
pctl->chip->of_gpio_n_cells = 3;
pctl->chip->can_sleep = false;
pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
pctl->desc->pin_base;
pctl->chip->label = dev_name(&pdev->dev);

18
drivers/pinctrl/sunxi/pinctrl-sunxi.h
View File

@ -95,6 +95,22 @@
#define PINCTRL_SUN7I_A20 BIT(7)
#define PINCTRL_SUN8I_R40 BIT(8)
#define PIO_POW_MOD_SEL_REG 0x340
enum sunxi_desc_bias_voltage {
BIAS_VOLTAGE_NONE,
/*
* Bias voltage configuration is done through
* Pn_GRP_CONFIG registers, as seen on A80 SoC.
*/
BIAS_VOLTAGE_GRP_CONFIG,
/*
* Bias voltage is set through PIO_POW_MOD_SEL_REG
* register, as seen on H6 SoC, for example.
*/
BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};
struct sunxi_desc_function {
unsigned long variant;
const char *name;
@ -117,7 +133,7 @@ struct sunxi_pinctrl_desc {
const unsigned int *irq_bank_map;
bool irq_read_needs_mux;
bool disable_strict_mode;
bool has_io_bias_cfg;
enum sunxi_desc_bias_voltage io_bias_cfg_variant;
};
struct sunxi_pinctrl_function {

1
drivers/pinctrl/zte/pinctrl-zx.c
View File

@ -411,6 +411,7 @@ int zx_pinctrl_init(struct platform_device *pdev,
}
zpctl->aux_base = of_iomap(np, 0);
of_node_put(np);
if (!zpctl->aux_base)
return -ENOMEM;

6
include/dt-bindings/pinctrl/stm32-pinfunc.h
View File

@ -32,5 +32,11 @@
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
/* package information */
#define STM32MP_PKG_AA 0x1
#define STM32MP_PKG_AB 0x2
#define STM32MP_PKG_AC 0x4
#define STM32MP_PKG_AD 0x8
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */

3
include/linux/gpio/driver.h
View File

@ -614,6 +614,9 @@ struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
enum gpiod_flags flags);
void gpiochip_free_own_desc(struct gpio_desc *desc);
void devprop_gpiochip_set_names(struct gpio_chip *chip,
const struct fwnode_handle *fwnode);
#else /* CONFIG_GPIOLIB */
static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)