drm/i915: Allocate a common scratch page
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications by not assuming per-engine isolation.
For later use, it simplifies engine initialisation (by removing the
allocation that required struct_mutex!) and means that we can always rely
on there being a scratch page.
v2: Check that we allocated a large enough scratch for I830 w/a
Fixes: 06e562e7f515 ("drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5") # v4.18.20
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108850
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181204141522.13640-1-chris@chris-wilson.co.uk
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.18.20+
(cherry picked from commit 5179749925)
[Joonas: Use new function in gen9_init_indirectctx_bb too]
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
hifive-unleashed-5.1
Chris Wilson
Joonas Lahtinen
parent
cf66b8a0ba
commit
fe78742d7f
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@ -2150,6 +2150,8 @@ struct drm_i915_private {
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struct delayed_work idle_work;
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ktime_t last_init_time;
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struct i915_vma *scratch;
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} gt;
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/* perform PHY state sanity checks? */
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@ -3872,4 +3874,9 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
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return I915_HWS_CSB_WRITE_INDEX;
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}
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static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
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{
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return i915_ggtt_offset(i915->gt.scratch);
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}
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#endif
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@ -5500,6 +5500,44 @@ err_active:
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goto out_ctx;
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}
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static int
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i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int ret;
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obj = i915_gem_object_create_stolen(i915, size);
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if (!obj)
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obj = i915_gem_object_create_internal(i915, size);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate scratch page\n");
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return PTR_ERR(obj);
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}
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vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_unref;
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}
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ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
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if (ret)
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goto err_unref;
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i915->gt.scratch = vma;
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return 0;
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err_unref:
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i915_gem_object_put(obj);
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return ret;
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}
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static void i915_gem_fini_scratch(struct drm_i915_private *i915)
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{
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i915_vma_unpin_and_release(&i915->gt.scratch, 0);
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}
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int i915_gem_init(struct drm_i915_private *dev_priv)
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{
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int ret;
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@ -5546,12 +5584,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
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goto err_unlock;
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}
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ret = i915_gem_contexts_init(dev_priv);
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ret = i915_gem_init_scratch(dev_priv,
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IS_GEN2(dev_priv) ? SZ_256K : PAGE_SIZE);
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if (ret) {
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GEM_BUG_ON(ret == -EIO);
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goto err_ggtt;
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}
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ret = i915_gem_contexts_init(dev_priv);
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if (ret) {
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GEM_BUG_ON(ret == -EIO);
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goto err_scratch;
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}
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ret = intel_engines_init(dev_priv);
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if (ret) {
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GEM_BUG_ON(ret == -EIO);
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@ -5624,6 +5669,8 @@ err_pm:
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err_context:
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if (ret != -EIO)
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i915_gem_contexts_fini(dev_priv);
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err_scratch:
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i915_gem_fini_scratch(dev_priv);
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err_ggtt:
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err_unlock:
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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@ -5675,6 +5722,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
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intel_uc_fini(dev_priv);
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i915_gem_cleanup_engines(dev_priv);
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i915_gem_contexts_fini(dev_priv);
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i915_gem_fini_scratch(dev_priv);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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intel_wa_list_free(&dev_priv->gt_wa_list);
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@ -1495,7 +1495,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
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if (HAS_BROKEN_CS_TLB(i915))
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ee->wa_batchbuffer =
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i915_error_object_create(i915,
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engine->scratch);
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i915->gt.scratch);
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request_record_user_bo(request, ee);
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ee->ctx =
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@ -490,46 +490,6 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
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intel_engine_init_cmd_parser(engine);
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}
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int intel_engine_create_scratch(struct intel_engine_cs *engine,
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unsigned int size)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int ret;
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WARN_ON(engine->scratch);
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obj = i915_gem_object_create_stolen(engine->i915, size);
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if (!obj)
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obj = i915_gem_object_create_internal(engine->i915, size);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate scratch page\n");
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return PTR_ERR(obj);
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}
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vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_unref;
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}
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ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
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if (ret)
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goto err_unref;
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engine->scratch = vma;
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return 0;
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err_unref:
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i915_gem_object_put(obj);
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return ret;
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}
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void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
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{
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i915_vma_unpin_and_release(&engine->scratch, 0);
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}
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static void cleanup_status_page(struct intel_engine_cs *engine)
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{
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if (HWS_NEEDS_PHYSICAL(engine->i915)) {
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@ -704,8 +664,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *i915 = engine->i915;
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intel_engine_cleanup_scratch(engine);
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cleanup_status_page(engine);
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intel_engine_fini_breadcrumbs(engine);
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@ -1448,9 +1448,10 @@ static int execlists_request_alloc(struct i915_request *request)
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static u32 *
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gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
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{
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/* NB no one else is allowed to scribble over scratch + 256! */
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*batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
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*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
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*batch++ = i915_ggtt_offset(engine->scratch) + 256;
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*batch++ = i915_scratch_offset(engine->i915) + 256;
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*batch++ = 0;
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*batch++ = MI_LOAD_REGISTER_IMM(1);
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@ -1464,7 +1465,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
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*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
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*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
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*batch++ = i915_ggtt_offset(engine->scratch) + 256;
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*batch++ = i915_scratch_offset(engine->i915) + 256;
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*batch++ = 0;
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return batch;
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@ -1501,7 +1502,7 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
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PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_QW_WRITE,
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i915_ggtt_offset(engine->scratch) +
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i915_scratch_offset(engine->i915) +
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2 * CACHELINE_BYTES);
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*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
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@ -1578,7 +1579,7 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
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PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_QW_WRITE,
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i915_ggtt_offset(engine->scratch)
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i915_scratch_offset(engine->i915)
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+ 2 * CACHELINE_BYTES);
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}
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@ -2146,7 +2147,7 @@ static int gen8_emit_flush_render(struct i915_request *request,
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{
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struct intel_engine_cs *engine = request->engine;
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u32 scratch_addr =
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i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
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i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
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bool vf_flush_wa = false, dc_flush_wa = false;
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u32 *cs, flags = 0;
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int len;
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@ -2483,10 +2484,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
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if (ret)
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return ret;
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ret = intel_engine_create_scratch(engine, PAGE_SIZE);
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if (ret)
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goto err_cleanup_common;
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ret = intel_init_workaround_bb(engine);
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if (ret) {
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/*
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@ -2501,10 +2498,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
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intel_engine_init_workarounds(engine);
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return 0;
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err_cleanup_common:
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intel_engine_cleanup_common(engine);
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return ret;
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}
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int logical_xcs_ring_init(struct intel_engine_cs *engine)
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@ -150,8 +150,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
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*/
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if (mode & EMIT_INVALIDATE) {
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*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
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*cs++ = i915_ggtt_offset(rq->engine->scratch) |
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PIPE_CONTROL_GLOBAL_GTT;
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*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
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*cs++ = 0;
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*cs++ = 0;
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@ -159,8 +158,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
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*cs++ = MI_FLUSH;
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*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
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*cs++ = i915_ggtt_offset(rq->engine->scratch) |
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PIPE_CONTROL_GLOBAL_GTT;
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*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
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*cs++ = 0;
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*cs++ = 0;
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}
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@ -212,8 +210,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
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static int
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intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
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{
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u32 scratch_addr =
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i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
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u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
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u32 *cs;
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cs = intel_ring_begin(rq, 6);
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@ -246,8 +243,7 @@ intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
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static int
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gen6_render_ring_flush(struct i915_request *rq, u32 mode)
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{
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u32 scratch_addr =
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i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
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u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
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u32 *cs, flags = 0;
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int ret;
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@ -316,8 +312,7 @@ gen7_render_ring_cs_stall_wa(struct i915_request *rq)
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static int
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gen7_render_ring_flush(struct i915_request *rq, u32 mode)
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{
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u32 scratch_addr =
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i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
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u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
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u32 *cs, flags = 0;
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/*
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@ -971,7 +966,7 @@ i965_emit_bb_start(struct i915_request *rq,
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}
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/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
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#define I830_BATCH_LIMIT (256*1024)
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#define I830_BATCH_LIMIT SZ_256K
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#define I830_TLB_ENTRIES (2)
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#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
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static int
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@ -979,7 +974,9 @@ i830_emit_bb_start(struct i915_request *rq,
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u64 offset, u32 len,
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unsigned int dispatch_flags)
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{
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u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
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u32 *cs, cs_offset = i915_scratch_offset(rq->i915);
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GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE);
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cs = intel_ring_begin(rq, 6);
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if (IS_ERR(cs))
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@ -1437,7 +1434,6 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
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{
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struct i915_timeline *timeline;
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struct intel_ring *ring;
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unsigned int size;
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int err;
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intel_engine_setup_common(engine);
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@ -1462,21 +1458,12 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
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GEM_BUG_ON(engine->buffer);
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engine->buffer = ring;
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size = PAGE_SIZE;
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if (HAS_BROKEN_CS_TLB(engine->i915))
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size = I830_WA_SIZE;
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err = intel_engine_create_scratch(engine, size);
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err = intel_engine_init_common(engine);
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if (err)
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goto err_unpin;
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err = intel_engine_init_common(engine);
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if (err)
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goto err_scratch;
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return 0;
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err_scratch:
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intel_engine_cleanup_scratch(engine);
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err_unpin:
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intel_ring_unpin(ring);
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err_ring:
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@ -1550,7 +1537,7 @@ static int flush_pd_dir(struct i915_request *rq)
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/* Stall until the page table load is complete */
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
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*cs++ = i915_ggtt_offset(engine->scratch);
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*cs++ = i915_scratch_offset(rq->i915);
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*cs++ = MI_NOOP;
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intel_ring_advance(rq, cs);
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@ -1659,7 +1646,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
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/* Insert a delay before the next switch! */
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(last_reg);
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*cs++ = i915_ggtt_offset(engine->scratch);
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*cs++ = i915_scratch_offset(rq->i915);
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*cs++ = MI_NOOP;
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}
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*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
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|
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@ -442,7 +442,6 @@ struct intel_engine_cs {
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struct intel_hw_status_page status_page;
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struct i915_ctx_workarounds wa_ctx;
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struct i915_wa_list wa_list;
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struct i915_vma *scratch;
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u32 irq_keep_mask; /* always keep these interrupts */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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@ -900,10 +899,6 @@ void intel_engine_setup_common(struct intel_engine_cs *engine);
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int intel_engine_init_common(struct intel_engine_cs *engine);
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void intel_engine_cleanup_common(struct intel_engine_cs *engine);
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int intel_engine_create_scratch(struct intel_engine_cs *engine,
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unsigned int size);
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void intel_engine_cleanup_scratch(struct intel_engine_cs *engine);
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int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
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int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
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int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
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|
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