[PATCH] powerpc: merge atomic.h, memory.h
powerpc: Merge atomic.h and memory.h into powerpc Merged atomic.h into include/powerpc. Moved asm-style HMT_ defines from memory.h into ppc_asm.h, where there were already HMT_defines; moved c-style HMT_ defines to processor.h. Renamed memory.h to synch.h to better reflect its contents. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Jon Loeliger <linuxppc@jdl.com> Signed-off-by: Paul Mackerras <paulus@samba.org>hifive-unleashed-5.1
Becky Bruce
Paul Mackerras
parent
2bfadee32f
commit
feaf7cf153
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@ -1,29 +1,20 @@
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#ifndef _ASM_POWERPC_ATOMIC_H_
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#define _ASM_POWERPC_ATOMIC_H_
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/*
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* PowerPC atomic operations
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*/
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#ifndef _ASM_PPC_ATOMIC_H_
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#define _ASM_PPC_ATOMIC_H_
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typedef struct { volatile int counter; } atomic_t;
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#ifdef __KERNEL__
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#include <asm/synch.h>
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#define ATOMIC_INIT(i) { (i) }
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
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#ifdef CONFIG_SMP
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#define SMP_SYNC "sync"
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#define SMP_ISYNC "\n\tisync"
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#else
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#define SMP_SYNC ""
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#define SMP_ISYNC
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#endif
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/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
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* The old ATOMIC_SYNC_FIX covered some but not all of this.
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*/
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@ -53,12 +44,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # atomic_add_return\n\
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add %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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SMP_ISYNC
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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@ -88,12 +80,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # atomic_sub_return\n\
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subf %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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SMP_ISYNC
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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@ -121,12 +114,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1 \n\
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bne- 1b"
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SMP_ISYNC
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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@ -164,12 +158,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_return\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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SMP_ISYNC
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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@ -189,13 +184,14 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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SMP_ISYNC
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ISYNC_ON_SMP
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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@ -204,11 +200,10 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
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return t;
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}
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#define __MB __asm__ __volatile__ (SMP_SYNC : : : "memory")
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#define smp_mb__before_atomic_dec() __MB
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#define smp_mb__after_atomic_dec() __MB
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#define smp_mb__before_atomic_inc() __MB
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#define smp_mb__after_atomic_inc() __MB
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#endif /* __KERNEL__ */
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#endif /* _ASM_PPC_ATOMIC_H_ */
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#endif /* _ASM_POWERPC_ATOMIC_H_ */
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@ -75,8 +75,11 @@
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#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
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/* Macros to adjust thread priority for Iseries hardware multithreading */
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#define HMT_VERY_LOW or 31,31,31 # very low priority\n"
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#define HMT_LOW or 1,1,1
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#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority\n"
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#define HMT_MEDIUM or 2,2,2
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#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority\n"
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#define HMT_HIGH or 3,3,3
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/* handle instructions that older assemblers may not know */
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@ -0,0 +1,51 @@
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#ifndef _ASM_POWERPC_SYNCH_H
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#define _ASM_POWERPC_SYNCH_H
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#include <linux/config.h>
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#ifdef __powerpc64__
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#define __SUBARCH_HAS_LWSYNC
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#endif
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#ifdef __SUBARCH_HAS_LWSYNC
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# define LWSYNC lwsync
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#else
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# define LWSYNC sync
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#endif
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/*
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* Arguably the bitops and *xchg operations don't imply any memory barrier
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* or SMP ordering, but in fact a lot of drivers expect them to imply
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* both, since they do on x86 cpus.
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*/
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#ifdef CONFIG_SMP
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#define EIEIO_ON_SMP "eieio\n"
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#define ISYNC_ON_SMP "\n\tisync"
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#define SYNC_ON_SMP __stringify(LWSYNC) "\n"
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#else
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#define EIEIO_ON_SMP
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#define ISYNC_ON_SMP
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#define SYNC_ON_SMP
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#endif
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static inline void eieio(void)
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{
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__asm__ __volatile__ ("eieio" : : : "memory");
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}
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static inline void isync(void)
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{
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__asm__ __volatile__ ("isync" : : : "memory");
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}
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#ifdef CONFIG_SMP
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#define eieio_on_smp() eieio()
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#define isync_on_smp() isync()
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#else
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#define eieio_on_smp() __asm__ __volatile__("": : :"memory")
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#define isync_on_smp() __asm__ __volatile__("": : :"memory")
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#endif
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#endif /* _ASM_POWERPC_SYNCH_H */
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@ -8,6 +8,7 @@
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#include <asm/page.h>
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#include <asm/byteorder.h>
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#include <asm/synch.h>
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#include <asm/mmu.h>
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#define SIO_CONFIG_RA 0x398
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@ -440,16 +441,6 @@ extern inline void * phys_to_virt(unsigned long address)
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#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
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#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
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/*
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* Enforce In-order Execution of I/O:
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* Acts as a barrier to ensure all previous I/O accesses have
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* completed before any further ones are issued.
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*/
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extern inline void eieio(void)
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{
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__asm__ __volatile__ ("eieio" : : : "memory");
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}
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/* Enforce in-order execution of data I/O.
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* No distinction between read/write on PPC; use eieio for all three.
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*/
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@ -1,197 +0,0 @@
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/*
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* PowerPC64 atomic operations
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*
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* Copyright (C) 2001 Paul Mackerras <paulus@au.ibm.com>, IBM
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_PPC64_ATOMIC_H_
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#define _ASM_PPC64_ATOMIC_H_
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#include <asm/memory.h>
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typedef struct { volatile int counter; } atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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static __inline__ void atomic_add(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_add\n\
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add %0,%2,%0\n\
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stwcx. %0,0,%3\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_add_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # atomic_add_return\n\
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add %0,%1,%0\n\
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stwcx. %0,0,%2\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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static __inline__ void atomic_sub(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_sub\n\
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subf %0,%2,%0\n\
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stwcx. %0,0,%3\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_sub_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # atomic_sub_return\n\
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subf %0,%1,%0\n\
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stwcx. %0,0,%2\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n\
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stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_inc_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n\
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stwcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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static __inline__ void atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n\
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stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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}
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static __inline__ int atomic_dec_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_return\n\
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addic %0,%0,-1\n\
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stwcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ int atomic_dec_if_positive(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n\
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stwcx. %0,0,%1\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#endif /* _ASM_PPC64_ATOMIC_H_ */
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@ -42,7 +42,7 @@
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#ifdef __KERNEL__
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#include <asm/memory.h>
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#include <asm/synch.h>
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/*
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* clear_bit doesn't imply a memory barrier
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@ -5,7 +5,7 @@
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#include <linux/futex.h>
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#include <asm/errno.h>
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#include <asm/memory.h>
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#include <asm/synch.h>
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#include <asm/uaccess.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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@ -15,7 +15,7 @@
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#ifdef CONFIG_PPC_ISERIES
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#include <asm/iSeries/iSeries_io.h>
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#endif
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#include <asm/memory.h>
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#include <asm/synch.h>
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#include <asm/delay.h>
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#include <asm-generic/iomap.h>
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@ -1,61 +0,0 @@
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#ifndef _ASM_PPC64_MEMORY_H_
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#define _ASM_PPC64_MEMORY_H_
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|
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/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
/*
|
||||
* Arguably the bitops and *xchg operations don't imply any memory barrier
|
||||
* or SMP ordering, but in fact a lot of drivers expect them to imply
|
||||
* both, since they do on x86 cpus.
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
#define EIEIO_ON_SMP "eieio\n"
|
||||
#define ISYNC_ON_SMP "\n\tisync"
|
||||
#define SYNC_ON_SMP "lwsync\n\t"
|
||||
#else
|
||||
#define EIEIO_ON_SMP
|
||||
#define ISYNC_ON_SMP
|
||||
#define SYNC_ON_SMP
|
||||
#endif
|
||||
|
||||
static inline void eieio(void)
|
||||
{
|
||||
__asm__ __volatile__ ("eieio" : : : "memory");
|
||||
}
|
||||
|
||||
static inline void isync(void)
|
||||
{
|
||||
__asm__ __volatile__ ("isync" : : : "memory");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define eieio_on_smp() eieio()
|
||||
#define isync_on_smp() isync()
|
||||
#else
|
||||
#define eieio_on_smp() __asm__ __volatile__("": : :"memory")
|
||||
#define isync_on_smp() __asm__ __volatile__("": : :"memory")
|
||||
#endif
|
||||
|
||||
/* Macros for adjusting thread priority (hardware multi-threading) */
|
||||
#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
|
||||
#define HMT_low() asm volatile("or 1,1,1 # low priority")
|
||||
#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
|
||||
#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
|
||||
#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
|
||||
#define HMT_high() asm volatile("or 3,3,3 # high priority")
|
||||
|
||||
#define HMT_VERY_LOW "\tor 31,31,31 # very low priority\n"
|
||||
#define HMT_LOW "\tor 1,1,1 # low priority\n"
|
||||
#define HMT_MEDIUM_LOW "\tor 6,6,6 # medium low priority\n"
|
||||
#define HMT_MEDIUM "\tor 2,2,2 # medium priority\n"
|
||||
#define HMT_MEDIUM_HIGH "\tor 5,5,5 # medium high priority\n"
|
||||
#define HMT_HIGH "\tor 3,3,3 # high priority\n"
|
||||
|
||||
#endif
|
||||
|
|
@ -368,6 +368,14 @@ GLUE(.,name):
|
|||
#define mfasr() ({unsigned long rval; \
|
||||
asm volatile("mfasr %0" : "=r" (rval)); rval;})
|
||||
|
||||
/* Macros for adjusting thread priority (hardware multi-threading) */
|
||||
#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
|
||||
#define HMT_low() asm volatile("or 1,1,1 # low priority")
|
||||
#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
|
||||
#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
|
||||
#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
|
||||
#define HMT_high() asm volatile("or 3,3,3 # high priority")
|
||||
|
||||
static inline void set_tb(unsigned int upper, unsigned int lower)
|
||||
{
|
||||
mttbl(0);
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/hw_irq.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/synch.h>
|
||||
|
||||
/*
|
||||
* Memory barrier.
|
||||
|
|
@ -48,7 +48,7 @@
|
|||
#ifdef CONFIG_SMP
|
||||
#define smp_mb() mb()
|
||||
#define smp_rmb() rmb()
|
||||
#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
|
||||
#define smp_wmb() eieio()
|
||||
#define smp_read_barrier_depends() read_barrier_depends()
|
||||
#else
|
||||
#define smp_mb() __asm__ __volatile__("": : :"memory")
|
||||
|
|
|
|||
Loading…
Reference in New Issue