ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt
Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30 board dt files. Set the parent clock of slink controller to PLLP and configure clock to 100MHz. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -89,6 +89,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
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&tegra_ehci3_pdata),
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OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
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{}
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};
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@ -108,6 +112,10 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
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{ "sdmmc1", "pll_p", 48000000, false},
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{ "sdmmc3", "pll_p", 48000000, false},
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{ "sdmmc4", "pll_p", 48000000, false},
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{ "sbc1", "pll_p", 100000000, false },
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{ "sbc2", "pll_p", 100000000, false },
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{ "sbc3", "pll_p", 100000000, false },
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{ "sbc4", "pll_p", 100000000, false },
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{ NULL, NULL, 0, 0},
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};
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@ -51,6 +51,12 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
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{}
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};
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@ -70,6 +76,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
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{ "sdmmc1", "pll_p", 48000000, false},
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{ "sdmmc3", "pll_p", 48000000, false},
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{ "sdmmc4", "pll_p", 48000000, false},
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{ "sbc1", "pll_p", 100000000, false},
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{ "sbc2", "pll_p", 100000000, false},
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{ "sbc3", "pll_p", 100000000, false},
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{ "sbc4", "pll_p", 100000000, false},
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{ "sbc5", "pll_p", 100000000, false},
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{ "sbc6", "pll_p", 100000000, false},
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{ NULL, NULL, 0, 0},
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};
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