ARM: 5829/1: ARM: U8500 register definitions
Adds register definitions, shared peripheral interrupt numbers (SHPI) and IO mappings for the U8500 core support. SHPI are assigned to [160:32] where first 32 interrupts are reserved. Reviewed-by: Alessandro Rubin <rubini@unipv.it> Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Srinidhi Kasagar
Russell King
parent
59b559d7a3
commit
ffae4e014a
131
arch/arm/mach-ux500/include/mach/hardware.h
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131
arch/arm/mach-ux500/include/mach/hardware.h
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/*
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* Copyright (C) 2009 ST-Ericsson.
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*
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* U8500 hardware definitions
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MACH_HARDWARE_H
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#define __MACH_HARDWARE_H
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/* macros to get at IO space when running virtually
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* We dont map all the peripherals, let ioremap do
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* this for us. We map only very basic peripherals here.
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*/
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#define U8500_IO_VIRTUAL 0xf0000000
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#define U8500_IO_PHYSICAL 0xa0000000
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/* this macro is used in assembly, so no cast */
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#define IO_ADDRESS(x) \
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(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
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/* typesafe io address */
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#define __io_address(n) __io(IO_ADDRESS(n))
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/*
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* Base address definitions for U8500 Onchip IPs. All the
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* peripherals are contained in a single 1 Mbyte region, with
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* AHB peripherals at the bottom and APB peripherals at the
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* top of the region. PER stands for PERIPHERAL region which
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* itself divided into sub regions.
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*/
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#define U8500_PER3_BASE 0x80000000
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#define U8500_PER2_BASE 0x80110000
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#define U8500_PER1_BASE 0x80120000
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#define U8500_PER4_BASE 0x80150000
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#define U8500_PER6_BASE 0xa03c0000
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#define U8500_PER5_BASE 0xa03e0000
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#define U8500_PER7_BASE 0xa03d0000
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#define U8500_SVA_BASE 0xa0100000
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#define U8500_SIA_BASE 0xa0200000
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#define U8500_SGA_BASE 0xa0300000
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#define U8500_MCDE_BASE 0xa0350000
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#define U8500_DMA_BASE 0xa0362000
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#define U8500_SCU_BASE 0xa0410000
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#define U8500_GIC_CPU_BASE 0xa0410100
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#define U8500_TWD_BASE 0xa0410600
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#define U8500_GIC_DIST_BASE 0xa0411000
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#define U8500_L2CC_BASE 0xa0412000
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#define U8500_TWD_SIZE 0x100
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/* per7 base addressess */
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#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
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#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
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#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
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#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
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#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
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/* per6 base addressess */
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#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
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#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
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#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
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#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
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#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
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#define U8500_CLKRST6_BASE (U8500_PER7_BASE + 0xf000)
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/* per5 base addressess */
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#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
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#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
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#define U8500_CLKRST5_BASE (U8500_PER7_BASE + 0x1f000)
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/* per4 base addressess */
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#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
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#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
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#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
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#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
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#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
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#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
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#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
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#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
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/* per3 base addressess */
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#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
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#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
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#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
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#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
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#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
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#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
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#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
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#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
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#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
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#define U8500_CLKRST3_BASE (U8500_PER7_BASE + 0xf000)
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/* per2 base addressess */
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#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
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#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
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#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
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#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
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#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
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#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
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#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
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#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
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#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
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#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
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#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
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#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
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#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
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/* per1 base addresses */
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#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
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#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
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#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
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#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
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#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
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#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
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#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
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#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
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#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
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#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
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#define U8500_CLKRST1_BASE (U8500_PER2_BASE + 0xf000)
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/* ST-Ericsson modified pl022 id */
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#define SSP_PER_ID 0x01080022
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#endif /* __MACH_HARDWARE_H */
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22
arch/arm/mach-ux500/include/mach/io.h
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arch/arm/mach-ux500/include/mach/io.h
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/*
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* arch/arm/mach-u8500/include/mach/io.h
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*
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* Copyright (C) 1997-1999 Russell King
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*
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* Modifications:
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* 06-12-1997 RMK Created.
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* 07-04-1999 RMK Major cleanup
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* We don't actually have real ISA nor PCI buses, but there is so many
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* drivers out there that might just work if we fake them...
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*/
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#define __io(a) __typesafe_io(a)
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#define __mem_pci(a) (a)
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#endif
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71
arch/arm/mach-ux500/include/mach/irqs.h
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arch/arm/mach-ux500/include/mach/irqs.h
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/*
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* Copyright (C) 2008 STMicroelectronics
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* Copyright (C) 2009 ST-Ericsson.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef ASM_ARCH_IRQS_H
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#define ASM_ARCH_IRQS_H
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#include <mach/hardware.h>
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#define IRQ_LOCALTIMER 29
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#define IRQ_LOCALWDOG 30
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/* Shared Peripheral Interrupt (SHPI) */
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#define IRQ_SHPI_START 32
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/* Interrupt numbers generic for shared peripheral */
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#define IRQ_MTU0 (IRQ_SHPI_START + 4)
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#define IRQ_SPI2 (IRQ_SHPI_START + 6)
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#define IRQ_SPI0 (IRQ_SHPI_START + 8)
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#define IRQ_UART0 (IRQ_SHPI_START + 11)
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#define IRQ_I2C3 (IRQ_SHPI_START + 12)
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#define IRQ_SSP0 (IRQ_SHPI_START + 14)
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#define IRQ_MTU1 (IRQ_SHPI_START + 17)
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#define IRQ_RTC_RTT (IRQ_SHPI_START + 18)
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#define IRQ_UART1 (IRQ_SHPI_START + 19)
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#define IRQ_I2C0 (IRQ_SHPI_START + 21)
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#define IRQ_I2C1 (IRQ_SHPI_START + 22)
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#define IRQ_USBOTG (IRQ_SHPI_START + 23)
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#define IRQ_DMA (IRQ_SHPI_START + 25)
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#define IRQ_UART2 (IRQ_SHPI_START + 26)
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#define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29)
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#define IRQ_MSP0 (IRQ_SHPI_START + 31)
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#define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
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#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
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#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
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#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
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#define IRQ_AB4500 (IRQ_SHPI_START + 40)
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#define IRQ_DISP (IRQ_SHPI_START + 48)
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#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
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#define IRQ_SSP1 (IRQ_SHPI_START + 52)
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#define IRQ_I2C2 (IRQ_SHPI_START + 55)
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#define IRQ_SDMMC0 (IRQ_SHPI_START + 60)
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#define IRQ_MSP1 (IRQ_SHPI_START + 62)
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#define IRQ_SPI1 (IRQ_SHPI_START + 96)
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#define IRQ_MSP2 (IRQ_SHPI_START + 98)
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#define IRQ_SDMMC4 (IRQ_SHPI_START + 99)
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#define IRQ_HSIRD0 (IRQ_SHPI_START + 104)
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#define IRQ_HSIRD1 (IRQ_SHPI_START + 105)
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#define IRQ_HSITD0 (IRQ_SHPI_START + 106)
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#define IRQ_HSITD1 (IRQ_SHPI_START + 107)
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#define IRQ_GPIO0 (IRQ_SHPI_START + 119)
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#define IRQ_GPIO1 (IRQ_SHPI_START + 120)
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#define IRQ_GPIO2 (IRQ_SHPI_START + 121)
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#define IRQ_GPIO3 (IRQ_SHPI_START + 122)
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#define IRQ_GPIO4 (IRQ_SHPI_START + 123)
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#define IRQ_GPIO5 (IRQ_SHPI_START + 124)
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#define IRQ_GPIO6 (IRQ_SHPI_START + 125)
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#define IRQ_GPIO7 (IRQ_SHPI_START + 126)
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#define IRQ_GPIO8 (IRQ_SHPI_START + 127)
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/* There are 128 shared peripheral interrupts assigned to
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* INTID[160:32]. The first 32 interrupts are reserved.
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*/
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#define NR_IRQS 161
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#endif /*ASM_ARCH_IRQS_H*/
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