powerpc/cache: add cache flush operation for various e500
Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at init time. The callback function will flush all caches in the current cpu. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>5.4-rM2-2.2.x-imx-squashed
Ran Wang
Dong Aisheng
parent
3ba26f9e41
commit
ffb8e12c2e
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@ -43,6 +43,14 @@ extern int machine_check_e500mc(struct pt_regs *regs);
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extern int machine_check_e500(struct pt_regs *regs);
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extern int machine_check_e200(struct pt_regs *regs);
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extern int machine_check_47x(struct pt_regs *regs);
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#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC)
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extern void __flush_caches_e500v2(void);
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extern void __flush_caches_e500mc(void);
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extern void __flush_caches_e5500(void);
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extern void __flush_caches_e6500(void);
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#endif
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int machine_check_8xx(struct pt_regs *regs);
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int machine_check_83xx(struct pt_regs *regs);
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@ -70,6 +78,10 @@ struct cpu_spec {
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/* flush caches inside the current cpu */
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void (*cpu_down_flush)(void);
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#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC)
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/* flush caches of the cpu which is running the function */
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void (*cpu_flush_caches)(void);
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#endif
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/* number of performance monitor counters */
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unsigned int num_pmcs;
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enum powerpc_pmc_type pmc_type;
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@ -365,6 +365,9 @@ int main(void)
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OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
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OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
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OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
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#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC)
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OFFSET(CPU_FLUSH_CACHES, cpu_spec, cpu_flush_caches);
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#endif
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OFFSET(pbe_address, pbe, address);
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OFFSET(pbe_orig_address, pbe, orig_address);
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@ -340,3 +340,84 @@ _GLOBAL(cpu_down_flush_e5500)
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/* L1 Data Cache of e6500 contains no modified data, no flush is required */
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_GLOBAL(cpu_down_flush_e6500)
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blr
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_GLOBAL(__flush_caches_e500v2)
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mflr r0
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bl flush_dcache_L1
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mtlr r0
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blr
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_GLOBAL(__flush_caches_e500mc)
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_GLOBAL(__flush_caches_e5500)
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mflr r0
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bl flush_dcache_L1
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bl flush_backside_L2_cache
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mtlr r0
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blr
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/* L1 Data Cache of e6500 contains no modified data, no flush is required */
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_GLOBAL(__flush_caches_e6500)
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blr
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/* r3 = virtual address of L2 controller, WIMG = 01xx */
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_GLOBAL(flush_disable_L2)
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/* It's a write-through cache, so only invalidation is needed. */
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mbar
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isync
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lwz r4, 0(r3)
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li r5, 1
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rlwimi r4, r5, 30, 0xc0000000
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stw r4, 0(r3)
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/* Wait for the invalidate to finish */
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1: lwz r4, 0(r3)
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andis. r4, r4, 0x4000
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bne 1b
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mbar
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blr
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/* r3 = virtual address of L2 controller, WIMG = 01xx */
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_GLOBAL(invalidate_enable_L2)
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mbar
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isync
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lwz r4, 0(r3)
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li r5, 3
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rlwimi r4, r5, 30, 0xc0000000
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stw r4, 0(r3)
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/* Wait for the invalidate to finish */
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1: lwz r4, 0(r3)
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andis. r4, r4, 0x4000
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bne 1b
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mbar
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blr
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/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
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_GLOBAL(__flush_disable_L1)
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mflr r10
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bl flush_dcache_L1 /* Flush L1 d-cache */
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mtlr r10
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mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
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li r5, 2
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rlwimi r4, r5, 0, 3
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msync
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isync
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mtspr SPRN_L1CSR0, r4
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isync
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1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
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andi. r4, r4, 2
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bne 1b
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mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
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li r5, 2
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rlwimi r4, r5, 0, 3
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mtspr SPRN_L1CSR1, r4
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isync
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blr
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@ -2051,6 +2051,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.machine_check = machine_check_e500,
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.platform = "ppc8548",
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.cpu_down_flush = cpu_down_flush_e500v2,
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.cpu_flush_caches = __flush_caches_e500v2,
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},
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#else
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{ /* e500mc */
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@ -2071,6 +2072,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.machine_check = machine_check_e500mc,
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.platform = "ppce500mc",
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.cpu_down_flush = cpu_down_flush_e500mc,
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.cpu_flush_caches = __flush_caches_e500mc,
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},
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#endif /* CONFIG_PPC_E500MC */
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#endif /* CONFIG_PPC32 */
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@ -2096,6 +2098,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.machine_check = machine_check_e500mc,
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.platform = "ppce5500",
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.cpu_down_flush = cpu_down_flush_e5500,
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.cpu_flush_caches = __flush_caches_e5500,
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},
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{ /* e6500 */
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.pvr_mask = 0xffff0000,
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@ -2119,6 +2122,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.machine_check = machine_check_e500mc,
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.platform = "ppce6500",
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.cpu_down_flush = cpu_down_flush_e6500,
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.cpu_flush_caches = __flush_caches_e6500,
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},
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#endif /* CONFIG_PPC_E500MC */
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#ifdef CONFIG_PPC32
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