Actions Semi SoC drivers for 4.13
This adds clock source and power domain drivers for S500/S900. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJZTUdyAAoJEPou0S0+fgE/cxIQALU/QhWWSaHwbGnavU9gKbar lOwfoSmdwlrCR7hUCxH14o11fF03fXxWdEGz825DJjZghEIVn7VEW521DzXzA1dy bF6s95seZXYKUwtcPERgxbRP89itr/cTZiIGnEeKFfAIU1lmd5KNYHme05+e2bcQ G6St+8NbtqKzMaXSaDIHiHpA2ewiMmnsg9exOCcFFYCe2qUzKVOYFtbqeb+cldML yUIfgRQnGHiVqhbzx/aSwwkmZic+j7VCwScaZEL6THJ0pem+ayuTCBdvk9LYk/aM cksZf1Jc5RwFi6ErybpWkVBE0U2voSyNHoK10dmUy0kyS2hj3ttXjtu1yFHV/K/5 /Ebe+aUP37sMoDQn/ZcAEY1+LV4RieL/8ePeUgH1dZ/+57T4Zapq2jE2iUazotF5 VleN1Gn6UDUnPDTXUzwTSPaE2Kw85TMKVeubOy/mbJ71E1ggB02xzHkI8nhw9xMX SzRXykR/lIrWyDufmRDiyczMhNcClgiVrxcwU0VrkgJKXrWa5Nj2xyo06GsPjftd 27P11Hi7aWFwZADw57k7h61yxVzJT9FpSp2ekYipDkgw6VAWiPvkbe90nolGI0zb 3gzWWxOZnqxk1gdfY3eTdLxAhFXituC/iSxAFSmWeLtL6OcFVQqZaJgi5MDL7vPg afrLMF5xasvqA2+zudak =FpP/ -----END PGP SIGNATURE----- Merge tag 'actions-drivers-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/drivers Pull "Actions Semi SoC drivers for 4.13" from Andreas Färber: This adds clock source and power domain drivers for S500/S900. * tag 'actions-drivers-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: soc: actions: owl-sps: Factor out owl_sps_set_pg() for power-gating soc: actions: Add Owl SPS dt-bindings: power: Add Owl SPS power domains clocksource: owl: Add S900 support clocksource: Add Owl timerhifive-unleashed-5.1
Arnd Bergmann
commit
ffe3744a59
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@ -0,0 +1,17 @@
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Actions Semi Owl Smart Power System (SPS)
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Required properties:
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- compatible : "actions,s500-sps" for S500
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- reg : Offset and length of the register set for the device.
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- #power-domain-cells : Must be 1.
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See macros in:
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include/dt-bindings/power/owl-s500-powergate.h for S500
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Example:
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sps: power-controller@b01b0100 {
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compatible = "actions,s500-sps";
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reg = <0xb01b0100 0x100>;
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#power-domain-cells = <1>;
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};
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@ -109,6 +109,13 @@ config ORION_TIMER
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help
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Enables the support for the Orion timer driver
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config OWL_TIMER
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bool "Owl timer driver" if COMPILE_TEST
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depends on GENERIC_CLOCKEVENTS
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select CLKSRC_MMIO
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help
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Enables the support for the Actions Semi Owl timer driver.
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config SUN4I_TIMER
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bool "Sun4i timer driver" if COMPILE_TEST
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depends on GENERIC_CLOCKEVENTS
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@ -53,6 +53,7 @@ obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
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obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
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obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
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obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
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obj-$(CONFIG_OWL_TIMER) += owl-timer.o
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obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
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@ -0,0 +1,172 @@
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/*
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* Actions Semi Owl timer
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*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2017 SUSE Linux GmbH
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* Author: Andreas Färber
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define OWL_Tx_CTL 0x0
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#define OWL_Tx_CMP 0x4
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#define OWL_Tx_VAL 0x8
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#define OWL_Tx_CTL_PD BIT(0)
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#define OWL_Tx_CTL_INTEN BIT(1)
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#define OWL_Tx_CTL_EN BIT(2)
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static void __iomem *owl_timer_base;
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static void __iomem *owl_clksrc_base;
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static void __iomem *owl_clkevt_base;
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static inline void owl_timer_reset(void __iomem *base)
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{
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writel(0, base + OWL_Tx_CTL);
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writel(0, base + OWL_Tx_VAL);
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writel(0, base + OWL_Tx_CMP);
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}
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static inline void owl_timer_set_enabled(void __iomem *base, bool enabled)
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{
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u32 ctl = readl(base + OWL_Tx_CTL);
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/* PD bit is cleared when set */
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ctl &= ~OWL_Tx_CTL_PD;
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if (enabled)
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ctl |= OWL_Tx_CTL_EN;
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else
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ctl &= ~OWL_Tx_CTL_EN;
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writel(ctl, base + OWL_Tx_CTL);
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}
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static u64 notrace owl_timer_sched_read(void)
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{
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return (u64)readl(owl_clksrc_base + OWL_Tx_VAL);
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}
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static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
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{
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owl_timer_set_enabled(owl_clkevt_base, false);
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return 0;
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}
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static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
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{
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owl_timer_reset(owl_clkevt_base);
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return 0;
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}
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static int owl_timer_tick_resume(struct clock_event_device *evt)
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{
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return 0;
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}
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static int owl_timer_set_next_event(unsigned long evt,
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struct clock_event_device *ev)
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{
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void __iomem *base = owl_clkevt_base;
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owl_timer_set_enabled(base, false);
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writel(OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL);
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writel(0, base + OWL_Tx_VAL);
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writel(evt, base + OWL_Tx_CMP);
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owl_timer_set_enabled(base, true);
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return 0;
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}
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static struct clock_event_device owl_clockevent = {
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.name = "owl_tick",
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.rating = 200,
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ,
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.set_state_shutdown = owl_timer_set_state_shutdown,
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.set_state_oneshot = owl_timer_set_state_oneshot,
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.tick_resume = owl_timer_tick_resume,
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.set_next_event = owl_timer_set_next_event,
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};
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static irqreturn_t owl_timer1_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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writel(OWL_Tx_CTL_PD, owl_clkevt_base + OWL_Tx_CTL);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int __init owl_timer_init(struct device_node *node)
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{
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struct clk *clk;
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unsigned long rate;
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int timer1_irq, ret;
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owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
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if (IS_ERR(owl_timer_base)) {
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pr_err("Can't map timer registers");
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return PTR_ERR(owl_timer_base);
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}
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owl_clksrc_base = owl_timer_base + 0x08;
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owl_clkevt_base = owl_timer_base + 0x14;
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timer1_irq = of_irq_get_byname(node, "timer1");
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if (timer1_irq <= 0) {
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pr_err("Can't parse timer1 IRQ");
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return -EINVAL;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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rate = clk_get_rate(clk);
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owl_timer_reset(owl_clksrc_base);
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owl_timer_set_enabled(owl_clksrc_base, true);
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sched_clock_register(owl_timer_sched_read, 32, rate);
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clocksource_mmio_init(owl_clksrc_base + OWL_Tx_VAL, node->name,
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rate, 200, 32, clocksource_mmio_readl_up);
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owl_timer_reset(owl_clkevt_base);
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ret = request_irq(timer1_irq, owl_timer1_interrupt, IRQF_TIMER,
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"owl-timer", &owl_clockevent);
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if (ret) {
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pr_err("failed to request irq %d\n", timer1_irq);
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return ret;
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}
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owl_clockevent.cpumask = cpumask_of(0);
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owl_clockevent.irq = timer1_irq;
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clockevents_config_and_register(&owl_clockevent, rate,
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0xf, 0xffffffff);
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return 0;
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}
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CLOCKSOURCE_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init);
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CLOCKSOURCE_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init);
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@ -1,5 +1,6 @@
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menu "SOC (System On Chip) specific Drivers"
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source "drivers/soc/actions/Kconfig"
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source "drivers/soc/atmel/Kconfig"
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source "drivers/soc/bcm/Kconfig"
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source "drivers/soc/fsl/Kconfig"
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@ -2,6 +2,7 @@
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# Makefile for the Linux Kernel SOC specific device drivers.
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#
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obj-$(CONFIG_ARCH_ACTIONS) += actions/
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obj-$(CONFIG_ARCH_AT91) += atmel/
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obj-y += bcm/
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obj-$(CONFIG_ARCH_DOVE) += dove/
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@ -0,0 +1,16 @@
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if ARCH_ACTIONS || COMPILE_TEST
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config OWL_PM_DOMAINS_HELPER
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bool
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config OWL_PM_DOMAINS
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bool "Actions Semi SPS power domains"
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depends on PM
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select OWL_PM_DOMAINS_HELPER
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select PM_GENERIC_DOMAINS
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help
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Say 'y' here to enable support for Smart Power System (SPS)
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power-gating on Actions Semiconductor S500 SoC.
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If unsure, say 'n'.
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endif
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@ -0,0 +1,2 @@
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obj-$(CONFIG_OWL_PM_DOMAINS_HELPER) += owl-sps-helper.o
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obj-$(CONFIG_OWL_PM_DOMAINS) += owl-sps.o
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@ -0,0 +1,51 @@
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/*
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* Actions Semi Owl Smart Power System (SPS) shared helpers
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*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2017 Andreas Färber
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#define OWL_SPS_PG_CTL 0x0
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int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable)
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{
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u32 val;
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bool ack;
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int timeout;
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val = readl(base + OWL_SPS_PG_CTL);
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ack = val & ack_mask;
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if (ack == enable)
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return 0;
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if (enable)
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val |= pwr_mask;
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else
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val &= ~pwr_mask;
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writel(val, base + OWL_SPS_PG_CTL);
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for (timeout = 5000; timeout > 0; timeout -= 50) {
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val = readl(base + OWL_SPS_PG_CTL);
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if ((val & ack_mask) == (enable ? ack_mask : 0))
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break;
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udelay(50);
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}
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if (timeout <= 0)
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return -ETIMEDOUT;
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udelay(10);
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return 0;
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}
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EXPORT_SYMBOL_GPL(owl_sps_set_pg);
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@ -0,0 +1,224 @@
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/*
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* Actions Semi Owl Smart Power System (SPS)
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*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2017 Andreas Färber
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pm_domain.h>
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#include <linux/soc/actions/owl-sps.h>
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#include <dt-bindings/power/owl-s500-powergate.h>
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struct owl_sps_domain_info {
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const char *name;
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int pwr_bit;
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int ack_bit;
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unsigned int genpd_flags;
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};
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struct owl_sps_info {
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unsigned num_domains;
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const struct owl_sps_domain_info *domains;
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};
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struct owl_sps {
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struct device *dev;
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const struct owl_sps_info *info;
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void __iomem *base;
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struct genpd_onecell_data genpd_data;
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struct generic_pm_domain *domains[];
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};
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#define to_owl_pd(gpd) container_of(gpd, struct owl_sps_domain, genpd)
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struct owl_sps_domain {
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struct generic_pm_domain genpd;
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const struct owl_sps_domain_info *info;
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struct owl_sps *sps;
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};
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static int owl_sps_set_power(struct owl_sps_domain *pd, bool enable)
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{
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u32 pwr_mask, ack_mask;
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ack_mask = BIT(pd->info->ack_bit);
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pwr_mask = BIT(pd->info->pwr_bit);
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return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable);
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}
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static int owl_sps_power_on(struct generic_pm_domain *domain)
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{
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struct owl_sps_domain *pd = to_owl_pd(domain);
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dev_dbg(pd->sps->dev, "%s power on", pd->info->name);
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return owl_sps_set_power(pd, true);
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}
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static int owl_sps_power_off(struct generic_pm_domain *domain)
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{
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struct owl_sps_domain *pd = to_owl_pd(domain);
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dev_dbg(pd->sps->dev, "%s power off", pd->info->name);
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return owl_sps_set_power(pd, false);
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}
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static int owl_sps_init_domain(struct owl_sps *sps, int index)
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{
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struct owl_sps_domain *pd;
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pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->info = &sps->info->domains[index];
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pd->sps = sps;
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pd->genpd.name = pd->info->name;
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pd->genpd.power_on = owl_sps_power_on;
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pd->genpd.power_off = owl_sps_power_off;
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pd->genpd.flags = pd->info->genpd_flags;
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pm_genpd_init(&pd->genpd, NULL, false);
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sps->genpd_data.domains[index] = &pd->genpd;
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return 0;
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}
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static int owl_sps_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
|
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const struct owl_sps_info *sps_info;
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struct owl_sps *sps;
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int i, ret;
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|
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "no device node\n");
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return -ENODEV;
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}
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match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev);
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if (!match || !match->data) {
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dev_err(&pdev->dev, "unknown compatible or missing data\n");
|
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return -EINVAL;
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}
|
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|
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sps_info = match->data;
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sps = devm_kzalloc(&pdev->dev, sizeof(*sps) +
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sps_info->num_domains * sizeof(sps->domains[0]),
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GFP_KERNEL);
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if (!sps)
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return -ENOMEM;
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|
||||
sps->base = of_io_request_and_map(pdev->dev.of_node, 0, "owl-sps");
|
||||
if (IS_ERR(sps->base)) {
|
||||
dev_err(&pdev->dev, "failed to map sps registers\n");
|
||||
return PTR_ERR(sps->base);
|
||||
}
|
||||
|
||||
sps->dev = &pdev->dev;
|
||||
sps->info = sps_info;
|
||||
sps->genpd_data.domains = sps->domains;
|
||||
sps->genpd_data.num_domains = sps_info->num_domains;
|
||||
|
||||
for (i = 0; i < sps_info->num_domains; i++) {
|
||||
ret = owl_sps_init_domain(sps, i);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_genpd_add_provider_onecell(pdev->dev.of_node, &sps->genpd_data);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to add provider (%d)", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct owl_sps_domain_info s500_sps_domains[] = {
|
||||
[S500_PD_VDE] = {
|
||||
.name = "VDE",
|
||||
.pwr_bit = 0,
|
||||
.ack_bit = 16,
|
||||
},
|
||||
[S500_PD_VCE_SI] = {
|
||||
.name = "VCE_SI",
|
||||
.pwr_bit = 1,
|
||||
.ack_bit = 17,
|
||||
},
|
||||
[S500_PD_USB2_1] = {
|
||||
.name = "USB2_1",
|
||||
.pwr_bit = 2,
|
||||
.ack_bit = 18,
|
||||
},
|
||||
[S500_PD_CPU2] = {
|
||||
.name = "CPU2",
|
||||
.pwr_bit = 5,
|
||||
.ack_bit = 21,
|
||||
.genpd_flags = GENPD_FLAG_ALWAYS_ON,
|
||||
},
|
||||
[S500_PD_CPU3] = {
|
||||
.name = "CPU3",
|
||||
.pwr_bit = 6,
|
||||
.ack_bit = 22,
|
||||
.genpd_flags = GENPD_FLAG_ALWAYS_ON,
|
||||
},
|
||||
[S500_PD_DMA] = {
|
||||
.name = "DMA",
|
||||
.pwr_bit = 8,
|
||||
.ack_bit = 12,
|
||||
},
|
||||
[S500_PD_DS] = {
|
||||
.name = "DS",
|
||||
.pwr_bit = 9,
|
||||
.ack_bit = 13,
|
||||
},
|
||||
[S500_PD_USB3] = {
|
||||
.name = "USB3",
|
||||
.pwr_bit = 10,
|
||||
.ack_bit = 14,
|
||||
},
|
||||
[S500_PD_USB2_0] = {
|
||||
.name = "USB2_0",
|
||||
.pwr_bit = 11,
|
||||
.ack_bit = 15,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct owl_sps_info s500_sps_info = {
|
||||
.num_domains = ARRAY_SIZE(s500_sps_domains),
|
||||
.domains = s500_sps_domains,
|
||||
};
|
||||
|
||||
static const struct of_device_id owl_sps_of_matches[] = {
|
||||
{ .compatible = "actions,s500-sps", .data = &s500_sps_info },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver owl_sps_platform_driver = {
|
||||
.probe = owl_sps_probe,
|
||||
.driver = {
|
||||
.name = "owl-sps",
|
||||
.of_match_table = owl_sps_of_matches,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init owl_sps_init(void)
|
||||
{
|
||||
return platform_driver_register(&owl_sps_platform_driver);
|
||||
}
|
||||
postcore_initcall(owl_sps_init);
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
#ifndef DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
|
||||
#define DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
|
||||
|
||||
#define S500_PD_VDE 0
|
||||
#define S500_PD_VCE_SI 1
|
||||
#define S500_PD_USB2_1 2
|
||||
#define S500_PD_CPU2 3
|
||||
#define S500_PD_CPU3 4
|
||||
#define S500_PD_DMA 5
|
||||
#define S500_PD_DS 6
|
||||
#define S500_PD_USB3 7
|
||||
#define S500_PD_USB2_0 8
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef SOC_ACTIONS_OWL_SPS_H
|
||||
#define SOC_ACTIONS_OWL_SPS_H
|
||||
|
||||
int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue