Xtensa improvements for 4.6:
- control whether perf IRQ is treated as NMI from Kconfig;
- implement ioremap for regions outside KIO segment;
- fix ISS serial port behaviour when EOF is reached;
- fix preemption in {clear,copy}_user_highpage;
- fix endianness issues for XTFPGA devices, big-endian cores are now
fully functional;
- clean up debug infrastructure and add support for hardware breakpoints
and watchpoints.
- add processor configurations for Three Core HiFi-2 MX and HiFi3 cpus
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Merge tag 'xtensa-next-20160320' of git://github.com/czankel/xtensa-linux
Pull Xtensa updates from Chris Zankel:
"Xtensa improvements for 4.6:
- control whether perf IRQ is treated as NMI from Kconfig
- implement ioremap for regions outside KIO segment
- fix ISS serial port behaviour when EOF is reached
- fix preemption in {clear,copy}_user_highpage
- fix endianness issues for XTFPGA devices, big-endian cores are now
fully functional
- clean up debug infrastructure and add support for hardware
breakpoints and watchpoints
- add processor configurations for Three Core HiFi-2 MX and HiFi3
cpus"
* tag 'xtensa-next-20160320' of git://github.com/czankel/xtensa-linux:
xtensa: add test_kc705_hifi variant
xtensa: add Three Core HiFi-2 MX Variant.
xtensa: support hardware breakpoints/watchpoints
xtensa: use context structure for debug exceptions
xtensa: remove remaining non-functional KGDB bits
xtensa: clear all DBREAKC registers on start
xtensa: xtfpga: fix earlycon endianness
xtensa: xtfpga: fix i2c controller register width and endianness
xtensa: xtfpga: fix ethernet controller endianness
xtensa: xtfpga: fix serial port register width and endianness
xtensa: define CONFIG_CPU_{BIG,LITTLE}_ENDIAN
xtensa: fix preemption in {clear,copy}_user_highpage
xtensa: ISS: don't hang if stdin EOF is reached
xtensa: support ioremap for memory outside KIO region
xtensa: use XTENSA_INT_LEVEL macro in asm/timex.h
xtensa: make fake NMI configurable
hifive-unleashed-5.1
Linus Torvalds
commit
fffad3e1b3
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|
@ -17,6 +17,7 @@ config XTENSA
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select HAVE_DMA_API_DEBUG
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select HAVE_FUNCTION_TRACER
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select HAVE_FUTEX_CMPXCHG if !MMU
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select HAVE_HW_BREAKPOINT if PERF_EVENTS
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select HAVE_IRQ_TIME_ACCOUNTING
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select HAVE_OPROFILE
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select HAVE_PERF_EVENTS
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@ -138,6 +139,22 @@ config XTENSA_VARIANT_HAVE_PERF_EVENTS
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If unsure, say N.
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config XTENSA_FAKE_NMI
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bool "Treat PMM IRQ as NMI"
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depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
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default n
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help
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If PMM IRQ is the only IRQ at EXCM level it is safe to
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treat it as NMI, which improves accuracy of profiling.
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If there are other interrupts at or above PMM IRQ priority level
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but not above the EXCM level, PMM IRQ still may be treated as NMI,
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but only if these IRQs are not used. There will be a build warning
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saying that this is not safe, and a bugcheck if one of these IRQs
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actually fire.
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If unsure, say N.
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config XTENSA_UNALIGNED_USER
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bool "Unaligned memory access in use space"
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help
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@ -53,9 +53,11 @@ endif
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ifeq ($(shell echo __XTENSA_EB__ | $(CC) -E - | grep -v "\#"),1)
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CHECKFLAGS += -D__XTENSA_EB__
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KBUILD_CPPFLAGS += -DCONFIG_CPU_BIG_ENDIAN
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endif
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ifeq ($(shell echo __XTENSA_EL__ | $(CC) -E - | grep -v "\#"),1)
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CHECKFLAGS += -D__XTENSA_EL__
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KBUILD_CPPFLAGS += -DCONFIG_CPU_LITTLE_ENDIAN
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endif
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vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y))
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@ -5,7 +5,7 @@
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/ {
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compatible = "cdns,xtensa-kc705";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000";
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bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000";
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};
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memory@0 {
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device_type = "memory";
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@ -5,7 +5,7 @@
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interrupt-parent = <&pic>;
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
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};
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memory@0 {
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@ -60,6 +60,8 @@
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no-loopback-test;
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reg = <0x0d050020 0x20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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native-endian;
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interrupts = <0 1>; /* external irq 0 */
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clocks = <&osc>;
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};
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@ -67,6 +69,7 @@
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enet0: ethoc@0d030000 {
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compatible = "opencores,ethoc";
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reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
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native-endian;
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interrupts = <1 1>; /* external irq 1 */
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local-mac-address = [00 50 c2 13 6f 00];
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clocks = <&osc>;
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@ -86,7 +89,8 @@
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#size-cells = <0>;
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reg = <0x0d090000 0x20>;
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reg-shift = <2>;
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reg-io-width = <1>;
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reg-io-width = <4>;
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native-endian;
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interrupts = <4 1>;
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clocks = <&osc>;
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@ -0,0 +1,58 @@
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/*
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* Xtensa hardware breakpoints/watchpoints handling functions
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*/
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#ifndef __ASM_XTENSA_HW_BREAKPOINT_H
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#define __ASM_XTENSA_HW_BREAKPOINT_H
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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#include <linux/kdebug.h>
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#include <linux/types.h>
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#include <uapi/linux/hw_breakpoint.h>
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/* Breakpoint */
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#define XTENSA_BREAKPOINT_EXECUTE 0
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/* Watchpoints */
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#define XTENSA_BREAKPOINT_LOAD 1
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#define XTENSA_BREAKPOINT_STORE 2
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struct arch_hw_breakpoint {
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unsigned long address;
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u16 len;
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u16 type;
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};
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struct perf_event;
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struct pt_regs;
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struct task_struct;
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int hw_breakpoint_slots(int type);
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int arch_check_bp_in_kernelspace(struct perf_event *bp);
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int arch_validate_hwbkpt_settings(struct perf_event *bp);
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int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data);
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int arch_install_hw_breakpoint(struct perf_event *bp);
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void arch_uninstall_hw_breakpoint(struct perf_event *bp);
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void hw_breakpoint_pmu_read(struct perf_event *bp);
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int check_hw_breakpoint(struct pt_regs *regs);
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void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
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#else
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struct task_struct;
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static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
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{
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}
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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#endif /* __ASM_XTENSA_HW_BREAKPOINT_H */
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@ -25,9 +25,12 @@
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#ifdef CONFIG_MMU
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void __iomem *xtensa_ioremap_nocache(unsigned long addr, unsigned long size);
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void __iomem *xtensa_ioremap_cache(unsigned long addr, unsigned long size);
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void xtensa_iounmap(volatile void __iomem *addr);
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/*
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* Return the virtual address for the specified bus memory.
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* Note that we currently don't support any address outside the KIO segment.
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*/
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static inline void __iomem *ioremap_nocache(unsigned long offset,
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unsigned long size)
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@ -36,7 +39,7 @@ static inline void __iomem *ioremap_nocache(unsigned long offset,
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&& offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
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return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
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else
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BUG();
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return xtensa_ioremap_nocache(offset, size);
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}
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static inline void __iomem *ioremap_cache(unsigned long offset,
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@ -46,7 +49,7 @@ static inline void __iomem *ioremap_cache(unsigned long offset,
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&& offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
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return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
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else
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BUG();
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return xtensa_ioremap_cache(offset, size);
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}
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#define ioremap_cache ioremap_cache
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@ -60,6 +63,13 @@ static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
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static inline void iounmap(volatile void __iomem *addr)
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{
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unsigned long va = (unsigned long) addr;
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if (!(va >= XCHAL_KIO_CACHED_VADDR &&
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va - XCHAL_KIO_CACHED_VADDR < XCHAL_KIO_SIZE) &&
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!(va >= XCHAL_KIO_BYPASS_VADDR &&
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va - XCHAL_KIO_BYPASS_VADDR < XCHAL_KIO_SIZE))
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xtensa_iounmap(addr);
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}
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#define virt_to_bus virt_to_phys
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@ -13,6 +13,7 @@
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#define _XTENSA_IRQFLAGS_H
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#include <linux/types.h>
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#include <asm/processor.h>
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static inline unsigned long arch_local_save_flags(void)
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{
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@ -78,22 +78,20 @@
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#define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level)
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#define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK)
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#define IS_POW2(v) (((v) & ((v) - 1)) == 0)
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#define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l)
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#define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK)
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#define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT)
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/* LOCKLEVEL defines the interrupt level that masks all
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* general-purpose interrupts.
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*/
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#if defined(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) && \
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defined(XCHAL_PROFILING_INTERRUPT) && \
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PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \
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XCHAL_EXCM_LEVEL > 1 && \
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IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL))
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#define LOCKLEVEL (XCHAL_EXCM_LEVEL - 1)
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#if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT)
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#define LOCKLEVEL (PROFILING_INTLEVEL - 1)
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#else
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#define LOCKLEVEL XCHAL_EXCM_LEVEL
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#endif
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#define TOPLEVEL XCHAL_EXCM_LEVEL
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#define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL)
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@ -132,11 +130,10 @@ struct thread_struct {
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unsigned long bad_vaddr; /* last user fault */
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unsigned long bad_uaddr; /* last kernel fault accessing user space */
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unsigned long error_code;
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unsigned long ibreak[XCHAL_NUM_IBREAK];
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unsigned long dbreaka[XCHAL_NUM_DBREAK];
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unsigned long dbreakc[XCHAL_NUM_DBREAK];
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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struct perf_event *ptrace_bp[XCHAL_NUM_IBREAK];
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struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK];
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#endif
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/* Make structure 16 bytes aligned. */
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int align[0] __attribute__ ((aligned(16)));
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};
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|
|
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|||
|
|
@ -28,6 +28,7 @@
|
|||
/* Special registers. */
|
||||
|
||||
#define SREG_MR 32
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#define SREG_IBREAKENABLE 96
|
||||
#define SREG_IBREAKA 128
|
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#define SREG_DBREAKA 144
|
||||
#define SREG_DBREAKC 160
|
||||
|
|
@ -103,6 +104,8 @@
|
|||
|
||||
/* DEBUGCAUSE register fields. */
|
||||
|
||||
#define DEBUGCAUSE_DBNUM_MASK 0xf00
|
||||
#define DEBUGCAUSE_DBNUM_SHIFT 8 /* First bit of DBNUM field */
|
||||
#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
|
||||
#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
|
||||
#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
|
||||
|
|
|
|||
|
|
@ -111,6 +111,7 @@ static inline struct thread_info *current_thread_info(void)
|
|||
#define TIF_MEMDIE 5 /* is terminating due to OOM killer */
|
||||
#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */
|
||||
#define TIF_NOTIFY_RESUME 7 /* callback before returning to user */
|
||||
#define TIF_DB_DISABLED 8 /* debug trap disabled for syscall */
|
||||
|
||||
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
|
||||
#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
|
||||
|
|
|
|||
|
|
@ -12,19 +12,16 @@
|
|||
#include <asm/processor.h>
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#define _INTLEVEL(x) XCHAL_INT ## x ## _LEVEL
|
||||
#define INTLEVEL(x) _INTLEVEL(x)
|
||||
|
||||
#if XCHAL_NUM_TIMERS > 0 && \
|
||||
INTLEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
|
||||
XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
|
||||
# define LINUX_TIMER 0
|
||||
# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
|
||||
#elif XCHAL_NUM_TIMERS > 1 && \
|
||||
INTLEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
|
||||
XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
|
||||
# define LINUX_TIMER 1
|
||||
# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
|
||||
#elif XCHAL_NUM_TIMERS > 2 && \
|
||||
INTLEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
|
||||
XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
|
||||
# define LINUX_TIMER 2
|
||||
# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -65,4 +65,21 @@ static inline void spill_registers(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
struct debug_table {
|
||||
/* Pointer to debug exception handler */
|
||||
void (*debug_exception)(void);
|
||||
/* Temporary register save area */
|
||||
unsigned long debug_save[1];
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
/* Save area for DBREAKC registers */
|
||||
unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
|
||||
/* Saved ICOUNT register */
|
||||
unsigned long icount_save;
|
||||
/* Saved ICOUNTLEVEL register */
|
||||
unsigned long icount_level_save;
|
||||
#endif
|
||||
};
|
||||
|
||||
void debug_exception(void);
|
||||
|
||||
#endif /* _XTENSA_TRAPS_H */
|
||||
|
|
|
|||
|
|
@ -72,6 +72,8 @@
|
|||
#define PTRACE_SETREGS 13
|
||||
#define PTRACE_GETXTREGS 18
|
||||
#define PTRACE_SETXTREGS 19
|
||||
#define PTRACE_GETHBPREGS 20
|
||||
#define PTRACE_SETHBPREGS 21
|
||||
|
||||
|
||||
#endif /* _UAPI_XTENSA_PTRACE_H */
|
||||
|
|
|
|||
|
|
@ -8,12 +8,12 @@ obj-y := align.o coprocessor.o entry.o irq.o pci-dma.o platform.o process.o \
|
|||
ptrace.o setup.o signal.o stacktrace.o syscall.o time.o traps.o \
|
||||
vectors.o
|
||||
|
||||
obj-$(CONFIG_KGDB) += xtensa-stub.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
|
||||
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o
|
||||
obj-$(CONFIG_SMP) += smp.o mxhead.o
|
||||
obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o
|
||||
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
|
||||
|
||||
AFLAGS_head.o += -mtext-section-literals
|
||||
AFLAGS_mxhead.o += -mtext-section-literals
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/kbuild.h>
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
int main(void)
|
||||
|
|
@ -117,5 +118,16 @@ int main(void)
|
|||
DEFINE(_CLONE_UNTRACED, CLONE_UNTRACED);
|
||||
DEFINE(PG_ARCH_1, PG_arch_1);
|
||||
|
||||
/* struct debug_table */
|
||||
DEFINE(DT_DEBUG_EXCEPTION,
|
||||
offsetof(struct debug_table, debug_exception));
|
||||
DEFINE(DT_DEBUG_SAVE, offsetof(struct debug_table, debug_save));
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
DEFINE(DT_DBREAKC_SAVE, offsetof(struct debug_table, dbreakc_save));
|
||||
DEFINE(DT_ICOUNT_SAVE, offsetof(struct debug_table, icount_save));
|
||||
DEFINE(DT_ICOUNT_LEVEL_SAVE,
|
||||
offsetof(struct debug_table, icount_level_save));
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -543,6 +543,12 @@ common_exception_return:
|
|||
#endif
|
||||
|
||||
5:
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
_bbci.l a4, TIF_DB_DISABLED, 7f
|
||||
movi a4, restore_dbreak
|
||||
callx4 a4
|
||||
7:
|
||||
#endif
|
||||
#ifdef CONFIG_DEBUG_TLB_SANITY
|
||||
l32i a4, a1, PT_DEPC
|
||||
bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
|
||||
|
|
@ -789,39 +795,99 @@ ENTRY(debug_exception)
|
|||
|
||||
movi a2, 1 << PS_EXCM_BIT
|
||||
or a2, a0, a2
|
||||
movi a0, debug_exception # restore a3, debug jump vector
|
||||
wsr a2, ps
|
||||
xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
|
||||
/* Switch to kernel/user stack, restore jump vector, and save a0 */
|
||||
|
||||
bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
|
||||
|
||||
addi a2, a1, -16-PT_SIZE # assume kernel stack
|
||||
3:
|
||||
l32i a0, a3, DT_DEBUG_SAVE
|
||||
s32i a1, a2, PT_AREG1
|
||||
s32i a0, a2, PT_AREG0
|
||||
movi a0, 0
|
||||
s32i a1, a2, PT_AREG1
|
||||
s32i a0, a2, PT_DEPC # mark it as a regular exception
|
||||
xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
xsr a0, depc
|
||||
s32i a3, a2, PT_AREG3
|
||||
s32i a0, a2, PT_AREG2
|
||||
mov a1, a2
|
||||
|
||||
/* Debug exception is handled as an exception, so interrupts will
|
||||
* likely be enabled in the common exception handler. Disable
|
||||
* preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM
|
||||
* meaning.
|
||||
*/
|
||||
#if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT)
|
||||
GET_THREAD_INFO(a2, a1)
|
||||
l32i a3, a2, TI_PRE_COUNT
|
||||
addi a3, a3, 1
|
||||
s32i a3, a2, TI_PRE_COUNT
|
||||
#endif
|
||||
|
||||
rsr a2, ps
|
||||
bbsi.l a2, PS_UM_BIT, _user_exception
|
||||
j _kernel_exception
|
||||
|
||||
2: rsr a2, excsave1
|
||||
l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
|
||||
s32i a0, a2, PT_AREG0
|
||||
movi a0, 0
|
||||
s32i a1, a2, PT_AREG1
|
||||
s32i a0, a2, PT_DEPC
|
||||
xsr a0, depc
|
||||
s32i a3, a2, PT_AREG3
|
||||
s32i a0, a2, PT_AREG2
|
||||
mov a1, a2
|
||||
j _user_exception
|
||||
j 3b
|
||||
|
||||
/* Debug exception while in exception mode. */
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
/* Debug exception while in exception mode. This may happen when
|
||||
* window overflow/underflow handler or fast exception handler hits
|
||||
* data breakpoint, in which case save and disable all data
|
||||
* breakpoints, single-step faulting instruction and restore data
|
||||
* breakpoints.
|
||||
*/
|
||||
1:
|
||||
bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode
|
||||
|
||||
rsr a0, debugcause
|
||||
bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
|
||||
|
||||
.set _index, 0
|
||||
.rept XCHAL_NUM_DBREAK
|
||||
l32i a0, a3, DT_DBREAKC_SAVE + _index * 4
|
||||
wsr a0, SREG_DBREAKC + _index
|
||||
.set _index, _index + 1
|
||||
.endr
|
||||
|
||||
l32i a0, a3, DT_ICOUNT_LEVEL_SAVE
|
||||
wsr a0, icountlevel
|
||||
|
||||
l32i a0, a3, DT_ICOUNT_SAVE
|
||||
xsr a0, icount
|
||||
|
||||
l32i a0, a3, DT_DEBUG_SAVE
|
||||
xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
rfi XCHAL_DEBUGLEVEL
|
||||
|
||||
.Ldebug_save_dbreak:
|
||||
.set _index, 0
|
||||
.rept XCHAL_NUM_DBREAK
|
||||
movi a0, 0
|
||||
xsr a0, SREG_DBREAKC + _index
|
||||
s32i a0, a3, DT_DBREAKC_SAVE + _index * 4
|
||||
.set _index, _index + 1
|
||||
.endr
|
||||
|
||||
movi a0, XCHAL_EXCM_LEVEL + 1
|
||||
xsr a0, icountlevel
|
||||
s32i a0, a3, DT_ICOUNT_LEVEL_SAVE
|
||||
|
||||
movi a0, 0xfffffffe
|
||||
xsr a0, icount
|
||||
s32i a0, a3, DT_ICOUNT_SAVE
|
||||
|
||||
l32i a0, a3, DT_DEBUG_SAVE
|
||||
xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
rfi XCHAL_DEBUGLEVEL
|
||||
#else
|
||||
/* Debug exception while in exception mode. Should not happen. */
|
||||
1: j 1b // FIXME!!
|
||||
#endif
|
||||
|
||||
ENDPROC(debug_exception)
|
||||
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ ENTRY(_startup)
|
|||
wsr a0, icountlevel
|
||||
|
||||
.set _index, 0
|
||||
.rept XCHAL_NUM_DBREAK - 1
|
||||
.rept XCHAL_NUM_DBREAK
|
||||
wsr a0, SREG_DBREAKC + _index
|
||||
.set _index, _index + 1
|
||||
.endr
|
||||
|
|
@ -197,11 +197,6 @@ ENTRY(_startup)
|
|||
wsr a2, ps # (enable reg-windows; progmode stack)
|
||||
rsync
|
||||
|
||||
/* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
|
||||
|
||||
movi a2, debug_exception
|
||||
wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Notice that we assume with SMP that cores have PRID
|
||||
|
|
|
|||
|
|
@ -0,0 +1,317 @@
|
|||
/*
|
||||
* Xtensa hardware breakpoints/watchpoints handling functions
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2016 Cadence Design Systems Inc.
|
||||
*/
|
||||
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/perf_event.h>
|
||||
#include <variant/core.h>
|
||||
|
||||
/* Breakpoint currently in use for each IBREAKA. */
|
||||
static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
|
||||
|
||||
/* Watchpoint currently in use for each DBREAKA. */
|
||||
static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
|
||||
|
||||
int hw_breakpoint_slots(int type)
|
||||
{
|
||||
switch (type) {
|
||||
case TYPE_INST:
|
||||
return XCHAL_NUM_IBREAK;
|
||||
case TYPE_DATA:
|
||||
return XCHAL_NUM_DBREAK;
|
||||
default:
|
||||
pr_warn("unknown slot type: %d\n", type);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int arch_check_bp_in_kernelspace(struct perf_event *bp)
|
||||
{
|
||||
unsigned int len;
|
||||
unsigned long va;
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
|
||||
va = info->address;
|
||||
len = bp->attr.bp_len;
|
||||
|
||||
return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Construct an arch_hw_breakpoint from a perf_event.
|
||||
*/
|
||||
static int arch_build_bp_info(struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
|
||||
/* Type */
|
||||
switch (bp->attr.bp_type) {
|
||||
case HW_BREAKPOINT_X:
|
||||
info->type = XTENSA_BREAKPOINT_EXECUTE;
|
||||
break;
|
||||
case HW_BREAKPOINT_R:
|
||||
info->type = XTENSA_BREAKPOINT_LOAD;
|
||||
break;
|
||||
case HW_BREAKPOINT_W:
|
||||
info->type = XTENSA_BREAKPOINT_STORE;
|
||||
break;
|
||||
case HW_BREAKPOINT_RW:
|
||||
info->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Len */
|
||||
info->len = bp->attr.bp_len;
|
||||
if (info->len < 1 || info->len > 64 || !is_power_of_2(info->len))
|
||||
return -EINVAL;
|
||||
|
||||
/* Address */
|
||||
info->address = bp->attr.bp_addr;
|
||||
if (info->address & (info->len - 1))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_validate_hwbkpt_settings(struct perf_event *bp)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Build the arch_hw_breakpoint. */
|
||||
ret = arch_build_bp_info(bp);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
|
||||
unsigned long val, void *data)
|
||||
{
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static void xtensa_wsr(unsigned long v, u8 sr)
|
||||
{
|
||||
/* We don't have indexed wsr and creating instruction dynamically
|
||||
* doesn't seem worth it given how small XCHAL_NUM_IBREAK and
|
||||
* XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
|
||||
* the switch below needs to be extended.
|
||||
*/
|
||||
BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
|
||||
BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);
|
||||
|
||||
switch (sr) {
|
||||
#if XCHAL_NUM_IBREAK > 0
|
||||
case SREG_IBREAKA + 0:
|
||||
WSR(v, SREG_IBREAKA + 0);
|
||||
break;
|
||||
#endif
|
||||
#if XCHAL_NUM_IBREAK > 1
|
||||
case SREG_IBREAKA + 1:
|
||||
WSR(v, SREG_IBREAKA + 1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if XCHAL_NUM_DBREAK > 0
|
||||
case SREG_DBREAKA + 0:
|
||||
WSR(v, SREG_DBREAKA + 0);
|
||||
break;
|
||||
case SREG_DBREAKC + 0:
|
||||
WSR(v, SREG_DBREAKC + 0);
|
||||
break;
|
||||
#endif
|
||||
#if XCHAL_NUM_DBREAK > 1
|
||||
case SREG_DBREAKA + 1:
|
||||
WSR(v, SREG_DBREAKA + 1);
|
||||
break;
|
||||
|
||||
case SREG_DBREAKC + 1:
|
||||
WSR(v, SREG_DBREAKC + 1);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static int alloc_slot(struct perf_event **slot, size_t n,
|
||||
struct perf_event *bp)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < n; ++i) {
|
||||
if (!slot[i]) {
|
||||
slot[i] = bp;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
static void set_ibreak_regs(int reg, struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
unsigned long ibreakenable;
|
||||
|
||||
xtensa_wsr(info->address, SREG_IBREAKA + reg);
|
||||
RSR(ibreakenable, SREG_IBREAKENABLE);
|
||||
WSR(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
|
||||
}
|
||||
|
||||
static void set_dbreak_regs(int reg, struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;
|
||||
|
||||
if (info->type & XTENSA_BREAKPOINT_LOAD)
|
||||
dbreakc |= DBREAKC_LOAD_MASK;
|
||||
if (info->type & XTENSA_BREAKPOINT_STORE)
|
||||
dbreakc |= DBREAKC_STOR_MASK;
|
||||
|
||||
xtensa_wsr(info->address, SREG_DBREAKA + reg);
|
||||
xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
|
||||
}
|
||||
|
||||
int arch_install_hw_breakpoint(struct perf_event *bp)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
|
||||
/* Breakpoint */
|
||||
i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
|
||||
if (i < 0)
|
||||
return i;
|
||||
set_ibreak_regs(i, bp);
|
||||
|
||||
} else {
|
||||
/* Watchpoint */
|
||||
i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
|
||||
if (i < 0)
|
||||
return i;
|
||||
set_dbreak_regs(i, bp);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int free_slot(struct perf_event **slot, size_t n,
|
||||
struct perf_event *bp)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < n; ++i) {
|
||||
if (slot[i] == bp) {
|
||||
slot[i] = NULL;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
int i;
|
||||
|
||||
if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
|
||||
unsigned long ibreakenable;
|
||||
|
||||
/* Breakpoint */
|
||||
i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
|
||||
if (i >= 0) {
|
||||
RSR(ibreakenable, SREG_IBREAKENABLE);
|
||||
WSR(ibreakenable & ~(1 << i), SREG_IBREAKENABLE);
|
||||
}
|
||||
} else {
|
||||
/* Watchpoint */
|
||||
i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
|
||||
if (i >= 0)
|
||||
xtensa_wsr(0, SREG_DBREAKC + i);
|
||||
}
|
||||
}
|
||||
|
||||
void hw_breakpoint_pmu_read(struct perf_event *bp)
|
||||
{
|
||||
}
|
||||
|
||||
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
|
||||
{
|
||||
int i;
|
||||
struct thread_struct *t = &tsk->thread;
|
||||
|
||||
for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
|
||||
if (t->ptrace_bp[i]) {
|
||||
unregister_hw_breakpoint(t->ptrace_bp[i]);
|
||||
t->ptrace_bp[i] = NULL;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
|
||||
if (t->ptrace_wp[i]) {
|
||||
unregister_hw_breakpoint(t->ptrace_wp[i]);
|
||||
t->ptrace_wp[i] = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set ptrace breakpoint pointers to zero for this task.
|
||||
* This is required in order to prevent child processes from unregistering
|
||||
* breakpoints held by their parent.
|
||||
*/
|
||||
void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
|
||||
{
|
||||
memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
|
||||
memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
|
||||
}
|
||||
|
||||
void restore_dbreak(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
|
||||
struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];
|
||||
|
||||
if (bp)
|
||||
set_dbreak_regs(i, bp);
|
||||
}
|
||||
clear_thread_flag(TIF_DB_DISABLED);
|
||||
}
|
||||
|
||||
int check_hw_breakpoint(struct pt_regs *regs)
|
||||
{
|
||||
if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
|
||||
int i;
|
||||
struct perf_event **bp = this_cpu_ptr(bp_on_reg);
|
||||
|
||||
for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
|
||||
if (bp[i] && !bp[i]->attr.disabled &&
|
||||
regs->pc == bp[i]->attr.bp_addr)
|
||||
perf_bp_event(bp[i], regs);
|
||||
}
|
||||
return 0;
|
||||
} else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
|
||||
struct perf_event **bp = this_cpu_ptr(wp_on_reg);
|
||||
int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
|
||||
DEBUGCAUSE_DBNUM_SHIFT;
|
||||
|
||||
if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
|
||||
if (user_mode(regs)) {
|
||||
perf_bp_event(bp[dbnum], regs);
|
||||
} else {
|
||||
set_thread_flag(TIF_DB_DISABLED);
|
||||
xtensa_wsr(0, SREG_DBREAKC + dbnum);
|
||||
}
|
||||
} else {
|
||||
WARN_ONCE(1,
|
||||
"Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",
|
||||
dbnum);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
return -ENOENT;
|
||||
}
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/unistd.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/elf.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/prctl.h>
|
||||
#include <linux/init_task.h>
|
||||
|
|
@ -43,6 +44,7 @@
|
|||
#include <linux/atomic.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/regs.h>
|
||||
#include <asm/hw_breakpoint.h>
|
||||
|
||||
extern void ret_from_fork(void);
|
||||
extern void ret_from_kernel_thread(void);
|
||||
|
|
@ -131,6 +133,7 @@ void flush_thread(void)
|
|||
coprocessor_flush_all(ti);
|
||||
coprocessor_release_all(ti);
|
||||
#endif
|
||||
flush_ptrace_hw_breakpoint(current);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -273,6 +276,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp_thread_fn,
|
|||
ti->cpenable = 0;
|
||||
#endif
|
||||
|
||||
clear_ptrace_hw_breakpoint(p);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -13,21 +13,23 @@
|
|||
* Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/security.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/elf.h>
|
||||
#include <asm/coprocessor.h>
|
||||
#include <asm/elf.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
|
||||
void user_enable_single_step(struct task_struct *child)
|
||||
|
|
@ -267,6 +269,146 @@ int ptrace_pokeusr(struct task_struct *child, long regno, long val)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
static void ptrace_hbptriggered(struct perf_event *bp,
|
||||
struct perf_sample_data *data,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
int i;
|
||||
siginfo_t info;
|
||||
struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
|
||||
|
||||
if (bp->attr.bp_type & HW_BREAKPOINT_X) {
|
||||
for (i = 0; i < XCHAL_NUM_IBREAK; ++i)
|
||||
if (current->thread.ptrace_bp[i] == bp)
|
||||
break;
|
||||
i <<= 1;
|
||||
} else {
|
||||
for (i = 0; i < XCHAL_NUM_DBREAK; ++i)
|
||||
if (current->thread.ptrace_wp[i] == bp)
|
||||
break;
|
||||
i = (i << 1) | 1;
|
||||
}
|
||||
|
||||
info.si_signo = SIGTRAP;
|
||||
info.si_errno = i;
|
||||
info.si_code = TRAP_HWBKPT;
|
||||
info.si_addr = (void __user *)bkpt->address;
|
||||
|
||||
force_sig_info(SIGTRAP, &info, current);
|
||||
}
|
||||
|
||||
static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
|
||||
{
|
||||
struct perf_event_attr attr;
|
||||
|
||||
ptrace_breakpoint_init(&attr);
|
||||
|
||||
/* Initialise fields to sane defaults. */
|
||||
attr.bp_addr = 0;
|
||||
attr.bp_len = 1;
|
||||
attr.bp_type = type;
|
||||
attr.disabled = 1;
|
||||
|
||||
return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL,
|
||||
tsk);
|
||||
}
|
||||
|
||||
/*
|
||||
* Address bit 0 choose instruction (0) or data (1) break register, bits
|
||||
* 31..1 are the register number.
|
||||
* Both PTRACE_GETHBPREGS and PTRACE_SETHBPREGS transfer two 32-bit words:
|
||||
* address (0) and control (1).
|
||||
* Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
|
||||
* Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
|
||||
* 'trigger on load, bits 29..0 are length. Length 0 is used to clear a
|
||||
* breakpoint. To set a breakpoint length must be a power of 2 in the range
|
||||
* 1..64 and the address must be length-aligned.
|
||||
*/
|
||||
|
||||
static long ptrace_gethbpregs(struct task_struct *child, long addr,
|
||||
long __user *datap)
|
||||
{
|
||||
struct perf_event *bp;
|
||||
u32 user_data[2] = {0};
|
||||
bool dbreak = addr & 1;
|
||||
unsigned idx = addr >> 1;
|
||||
|
||||
if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
|
||||
(dbreak && idx >= XCHAL_NUM_DBREAK))
|
||||
return -EINVAL;
|
||||
|
||||
if (dbreak)
|
||||
bp = child->thread.ptrace_wp[idx];
|
||||
else
|
||||
bp = child->thread.ptrace_bp[idx];
|
||||
|
||||
if (bp) {
|
||||
user_data[0] = bp->attr.bp_addr;
|
||||
user_data[1] = bp->attr.disabled ? 0 : bp->attr.bp_len;
|
||||
if (dbreak) {
|
||||
if (bp->attr.bp_type & HW_BREAKPOINT_R)
|
||||
user_data[1] |= DBREAKC_LOAD_MASK;
|
||||
if (bp->attr.bp_type & HW_BREAKPOINT_W)
|
||||
user_data[1] |= DBREAKC_STOR_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
if (copy_to_user(datap, user_data, sizeof(user_data)))
|
||||
return -EFAULT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long ptrace_sethbpregs(struct task_struct *child, long addr,
|
||||
long __user *datap)
|
||||
{
|
||||
struct perf_event *bp;
|
||||
struct perf_event_attr attr;
|
||||
u32 user_data[2];
|
||||
bool dbreak = addr & 1;
|
||||
unsigned idx = addr >> 1;
|
||||
int bp_type = 0;
|
||||
|
||||
if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
|
||||
(dbreak && idx >= XCHAL_NUM_DBREAK))
|
||||
return -EINVAL;
|
||||
|
||||
if (copy_from_user(user_data, datap, sizeof(user_data)))
|
||||
return -EFAULT;
|
||||
|
||||
if (dbreak) {
|
||||
bp = child->thread.ptrace_wp[idx];
|
||||
if (user_data[1] & DBREAKC_LOAD_MASK)
|
||||
bp_type |= HW_BREAKPOINT_R;
|
||||
if (user_data[1] & DBREAKC_STOR_MASK)
|
||||
bp_type |= HW_BREAKPOINT_W;
|
||||
} else {
|
||||
bp = child->thread.ptrace_bp[idx];
|
||||
bp_type = HW_BREAKPOINT_X;
|
||||
}
|
||||
|
||||
if (!bp) {
|
||||
bp = ptrace_hbp_create(child,
|
||||
bp_type ? bp_type : HW_BREAKPOINT_RW);
|
||||
if (IS_ERR(bp))
|
||||
return PTR_ERR(bp);
|
||||
if (dbreak)
|
||||
child->thread.ptrace_wp[idx] = bp;
|
||||
else
|
||||
child->thread.ptrace_bp[idx] = bp;
|
||||
}
|
||||
|
||||
attr = bp->attr;
|
||||
attr.bp_addr = user_data[0];
|
||||
attr.bp_len = user_data[1] & ~(DBREAKC_LOAD_MASK | DBREAKC_STOR_MASK);
|
||||
attr.bp_type = bp_type;
|
||||
attr.disabled = !attr.bp_len;
|
||||
|
||||
return modify_user_hw_breakpoint(bp, &attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
long arch_ptrace(struct task_struct *child, long request,
|
||||
unsigned long addr, unsigned long data)
|
||||
{
|
||||
|
|
@ -307,7 +449,15 @@ long arch_ptrace(struct task_struct *child, long request,
|
|||
case PTRACE_SETXTREGS:
|
||||
ret = ptrace_setxregs(child, datap);
|
||||
break;
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
case PTRACE_GETHBPREGS:
|
||||
ret = ptrace_gethbpregs(child, addr, datap);
|
||||
break;
|
||||
|
||||
case PTRACE_SETHBPREGS:
|
||||
ret = ptrace_sethbpregs(child, addr, datap);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ret = ptrace_request(child, request, addr, data);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -39,11 +39,7 @@
|
|||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
extern int gdb_enter;
|
||||
extern int return_from_debug_flag;
|
||||
#endif
|
||||
#include <asm/hw_breakpoint.h>
|
||||
|
||||
/*
|
||||
* Machine specific interrupt handlers
|
||||
|
|
@ -162,6 +158,8 @@ COPROCESSOR(7),
|
|||
|
||||
DEFINE_PER_CPU(unsigned long, exc_table[EXC_TABLE_SIZE/4]);
|
||||
|
||||
DEFINE_PER_CPU(struct debug_table, debug_table);
|
||||
|
||||
void die(const char*, struct pt_regs*, long);
|
||||
|
||||
static inline void
|
||||
|
|
@ -205,6 +203,32 @@ extern void do_IRQ(int, struct pt_regs *);
|
|||
|
||||
#if XTENSA_FAKE_NMI
|
||||
|
||||
#define IS_POW2(v) (((v) & ((v) - 1)) == 0)
|
||||
|
||||
#if !(PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \
|
||||
IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL)))
|
||||
#warning "Fake NMI is requested for PMM, but there are other IRQs at or above its level."
|
||||
#warning "Fake NMI will be used, but there will be a bugcheck if one of those IRQs fire."
|
||||
|
||||
static inline void check_valid_nmi(void)
|
||||
{
|
||||
unsigned intread = get_sr(interrupt);
|
||||
unsigned intenable = get_sr(intenable);
|
||||
|
||||
BUG_ON(intread & intenable &
|
||||
~(XTENSA_INTLEVEL_ANDBELOW_MASK(PROFILING_INTLEVEL) ^
|
||||
XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL) ^
|
||||
BIT(XCHAL_PROFILING_INTERRUPT)));
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void check_valid_nmi(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_id);
|
||||
|
||||
DEFINE_PER_CPU(unsigned long, nmi_count);
|
||||
|
|
@ -219,6 +243,7 @@ void do_nmi(struct pt_regs *regs)
|
|||
old_regs = set_irq_regs(regs);
|
||||
nmi_enter();
|
||||
++*this_cpu_ptr(&nmi_count);
|
||||
check_valid_nmi();
|
||||
xtensa_pmu_irq_handler(0, NULL);
|
||||
nmi_exit();
|
||||
set_irq_regs(old_regs);
|
||||
|
|
@ -314,23 +339,22 @@ do_unaligned_user (struct pt_regs *regs)
|
|||
}
|
||||
#endif
|
||||
|
||||
/* Handle debug events.
|
||||
* When CONFIG_HAVE_HW_BREAKPOINT is on this handler is called with
|
||||
* preemption disabled to avoid rescheduling and keep mapping of hardware
|
||||
* breakpoint structures to debug registers intact, so that
|
||||
* DEBUGCAUSE.DBNUM could be used in case of data breakpoint hit.
|
||||
*/
|
||||
void
|
||||
do_debug(struct pt_regs *regs)
|
||||
{
|
||||
#ifdef CONFIG_KGDB
|
||||
/* If remote debugging is configured AND enabled, we give control to
|
||||
* kgdb. Otherwise, we fall through, perhaps giving control to the
|
||||
* native debugger.
|
||||
*/
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
int ret = check_hw_breakpoint(regs);
|
||||
|
||||
if (gdb_enter) {
|
||||
extern void gdb_handle_exception(struct pt_regs *);
|
||||
gdb_handle_exception(regs);
|
||||
return_from_debug_flag = 1;
|
||||
preempt_enable();
|
||||
if (ret == 0)
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
__die_if_kernel("Breakpoint in kernel", regs, SIGKILL);
|
||||
|
||||
/* If in user mode, send SIGTRAP signal to current process */
|
||||
|
|
@ -364,6 +388,15 @@ static void trap_init_excsave(void)
|
|||
__asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1));
|
||||
}
|
||||
|
||||
static void trap_init_debug(void)
|
||||
{
|
||||
unsigned long debugsave = (unsigned long)this_cpu_ptr(&debug_table);
|
||||
|
||||
this_cpu_ptr(&debug_table)->debug_exception = debug_exception;
|
||||
__asm__ __volatile__("wsr %0, excsave" __stringify(XCHAL_DEBUGLEVEL)
|
||||
:: "a"(debugsave));
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize dispatch tables.
|
||||
*
|
||||
|
|
@ -407,12 +440,14 @@ void __init trap_init(void)
|
|||
|
||||
/* Initialize EXCSAVE_1 to hold the address of the exception table. */
|
||||
trap_init_excsave();
|
||||
trap_init_debug();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void secondary_trap_init(void)
|
||||
{
|
||||
trap_init_excsave();
|
||||
trap_init_debug();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -601,7 +601,9 @@ ENDPROC(window_overflow_restore_a0_fixup)
|
|||
|
||||
ENTRY(_DebugInterruptVector)
|
||||
|
||||
xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
s32i a0, a3, DT_DEBUG_SAVE
|
||||
l32i a0, a3, DT_DEBUG_EXCEPTION
|
||||
jx a0
|
||||
|
||||
ENDPROC(_DebugInterruptVector)
|
||||
|
|
|
|||
|
|
@ -3,5 +3,5 @@
|
|||
#
|
||||
|
||||
obj-y := init.o misc.o
|
||||
obj-$(CONFIG_MMU) += cache.o fault.o mmu.o tlb.o
|
||||
obj-$(CONFIG_MMU) += cache.o fault.o ioremap.o mmu.o tlb.o
|
||||
obj-$(CONFIG_HIGHMEM) += highmem.o
|
||||
|
|
|
|||
|
|
@ -97,11 +97,11 @@ void clear_user_highpage(struct page *page, unsigned long vaddr)
|
|||
unsigned long paddr;
|
||||
void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
|
||||
|
||||
pagefault_disable();
|
||||
preempt_disable();
|
||||
kmap_invalidate_coherent(page, vaddr);
|
||||
set_bit(PG_arch_1, &page->flags);
|
||||
clear_page_alias(kvaddr, paddr);
|
||||
pagefault_enable();
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
void copy_user_highpage(struct page *dst, struct page *src,
|
||||
|
|
@ -113,11 +113,11 @@ void copy_user_highpage(struct page *dst, struct page *src,
|
|||
void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
|
||||
&src_paddr);
|
||||
|
||||
pagefault_disable();
|
||||
preempt_disable();
|
||||
kmap_invalidate_coherent(dst, vaddr);
|
||||
set_bit(PG_arch_1, &dst->flags);
|
||||
copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
|
||||
pagefault_enable();
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* ioremap implementation.
|
||||
*
|
||||
* Copyright (C) 2015 Cadence Design Systems Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
static void __iomem *xtensa_ioremap(unsigned long paddr, unsigned long size,
|
||||
pgprot_t prot)
|
||||
{
|
||||
unsigned long offset = paddr & ~PAGE_MASK;
|
||||
unsigned long pfn = __phys_to_pfn(paddr);
|
||||
struct vm_struct *area;
|
||||
unsigned long vaddr;
|
||||
int err;
|
||||
|
||||
paddr &= PAGE_MASK;
|
||||
|
||||
WARN_ON(pfn_valid(pfn));
|
||||
|
||||
size = PAGE_ALIGN(offset + size);
|
||||
|
||||
area = get_vm_area(size, VM_IOREMAP);
|
||||
if (!area)
|
||||
return NULL;
|
||||
|
||||
vaddr = (unsigned long)area->addr;
|
||||
area->phys_addr = paddr;
|
||||
|
||||
err = ioremap_page_range(vaddr, vaddr + size, paddr, prot);
|
||||
|
||||
if (err) {
|
||||
vunmap((void *)vaddr);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
flush_cache_vmap(vaddr, vaddr + size);
|
||||
return (void __iomem *)(offset + vaddr);
|
||||
}
|
||||
|
||||
void __iomem *xtensa_ioremap_nocache(unsigned long addr, unsigned long size)
|
||||
{
|
||||
return xtensa_ioremap(addr, size, pgprot_noncached(PAGE_KERNEL));
|
||||
}
|
||||
EXPORT_SYMBOL(xtensa_ioremap_nocache);
|
||||
|
||||
void __iomem *xtensa_ioremap_cache(unsigned long addr, unsigned long size)
|
||||
{
|
||||
return xtensa_ioremap(addr, size, PAGE_KERNEL);
|
||||
}
|
||||
EXPORT_SYMBOL(xtensa_ioremap_cache);
|
||||
|
||||
void xtensa_iounmap(volatile void __iomem *io_addr)
|
||||
{
|
||||
void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
|
||||
|
||||
vunmap(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(xtensa_iounmap);
|
||||
|
|
@ -96,21 +96,23 @@ static void rs_poll(unsigned long priv)
|
|||
{
|
||||
struct tty_port *port = (struct tty_port *)priv;
|
||||
int i = 0;
|
||||
int rd = 1;
|
||||
unsigned char c;
|
||||
|
||||
spin_lock(&timer_lock);
|
||||
|
||||
while (simc_poll(0)) {
|
||||
simc_read(0, &c, 1);
|
||||
rd = simc_read(0, &c, 1);
|
||||
if (rd <= 0)
|
||||
break;
|
||||
tty_insert_flip_char(port, c, TTY_NORMAL);
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i)
|
||||
tty_flip_buffer_push(port);
|
||||
|
||||
|
||||
mod_timer(&serial_timer, jiffies + SERIAL_TIMER_VALUE);
|
||||
if (rd)
|
||||
mod_timer(&serial_timer, jiffies + SERIAL_TIMER_VALUE);
|
||||
spin_unlock(&timer_lock);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -223,6 +223,7 @@ static struct ethoc_platform_data ethoc_pdata = {
|
|||
*/
|
||||
.hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
|
||||
.phy_id = -1,
|
||||
.big_endian = XCHAL_HAVE_BE,
|
||||
};
|
||||
|
||||
static struct platform_device ethoc_device = {
|
||||
|
|
@ -283,7 +284,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.irq = DUART16552_INTNUM,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
||||
UPF_IOREMAP,
|
||||
.iotype = UPIO_MEM32,
|
||||
.iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,
|
||||
.regshift = 2,
|
||||
.uartclk = 0, /* set in xtavnet_init() */
|
||||
},
|
||||
|
|
|
|||
|
|
@ -0,0 +1,531 @@
|
|||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2014 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 1000004 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "test_kc705_hifi" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x0004983D /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC1B3FFFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1904983D /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX5.0.4" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2500 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 250004 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX5 1
|
||||
#define XCHAL_HW_REL_LX5_0 1
|
||||
#define XCHAL_HW_REL_LX5_0_4 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2500 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 250004 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2500 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 250004 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 7
|
||||
#define XCHAL_DCACHE_SETWIDTH 7
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS 4
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 8
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 8
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F00BF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000140
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00009000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00002000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F01FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F0FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 2
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 4
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 4
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F0000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00008000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
#define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL5_NUM 13
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3, 4.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
|
||||
#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
|
||||
#define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00002000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x00002340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00002340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
|
||||
*
|
||||
* NOTE: This header file is not meant to be included directly.
|
||||
*/
|
||||
|
||||
/* This header file contains assembly-language definitions (assembly
|
||||
macros, etc.) for this specific Xtensa processor's TIE extensions
|
||||
and options. It is customized to this Xtensa processor configuration.
|
||||
|
||||
Copyright (c) 1999-2014 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_ASM_H
|
||||
#define _XTENSA_CORE_TIE_ASM_H
|
||||
|
||||
/* Selection parameter values for save-area save/restore macros: */
|
||||
/* Option vs. TIE: */
|
||||
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
|
||||
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
|
||||
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
|
||||
/* Whether used automatically by compiler: */
|
||||
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
|
||||
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
|
||||
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
|
||||
/* ABI handling across function calls: */
|
||||
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
|
||||
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
|
||||
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
|
||||
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
|
||||
/* Misc */
|
||||
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
|
||||
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
|
||||
| ((ccuse) & XTHAL_SAS_ANYCC) \
|
||||
| ((abi) & XTHAL_SAS_ANYABI) )
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Macro to save all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger store sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to store. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to store, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any store.
|
||||
*/
|
||||
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global register used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
rur.THREADPTR \at1 // threadptr option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
rsr.ACCLO \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.ACCHI \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
rsr.M0 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rsr.M1 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rsr.M2 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
rsr.M3 \at1 // MAC16 option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
rsr.BR \at1 // boolean option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
rsr.SCOMPARE1 \at1 // conditional store option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
|
||||
/*
|
||||
* Macro to restore all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 4 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters:
|
||||
* continue If macro invoked as part of a larger load sequence, set to 1
|
||||
* if this is not the first in the sequence. Defaults to 0.
|
||||
* ofs Offset from start of larger sequence (from value of first ptr
|
||||
* in sequence) at which to load. Defaults to next available space
|
||||
* (or 0 if <continue> is 0).
|
||||
* select Select what category(ies) of registers to load, as a bitmask
|
||||
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
|
||||
* alloc Select what category(ies) of registers to allocate; if any
|
||||
* category is selected here that is not in <select>, space for
|
||||
* the corresponding registers is skipped without doing any load.
|
||||
*/
|
||||
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Optional global register used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.THREADPTR \at1 // threadptr option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1020, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
// Optional caller-saved registers used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.ACCLO \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.ACCHI \at1 // MAC16 option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
// Optional caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wsr.M0 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wsr.M1 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wsr.M2 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
wsr.M3 \at1 // MAC16 option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
wsr.BR \at1 // boolean option
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
wsr.SCOMPARE1 \at1 // conditional store option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1000, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
|
||||
|
||||
#define XCHAL_NCP_NUM_ATMPS 1
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Macro to save the state of TIE coprocessor AudioEngineLX.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 8 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_store.
|
||||
*/
|
||||
#define xchal_cp_AudioEngineLX_store xchal_cp1_store
|
||||
.macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
rur.AE_OVF_SAR \at1 // ureg 240
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
rur.AE_BITHEAD \at1 // ureg 241
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
rur.AE_TS_FTS_BU_BP \at1 // ureg 242
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
rur.AE_CW_SD_NO \at1 // ureg 243
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
rur.AE_CBEGIN0 \at1 // ureg 246
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
rur.AE_CEND0 \at1 // ureg 247
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
AE_S64.I aed0, \ptr, .Lxchal_ofs_+24
|
||||
AE_S64.I aed1, \ptr, .Lxchal_ofs_+32
|
||||
AE_S64.I aed2, \ptr, .Lxchal_ofs_+40
|
||||
AE_S64.I aed3, \ptr, .Lxchal_ofs_+48
|
||||
AE_S64.I aed4, \ptr, .Lxchal_ofs_+56
|
||||
addi \ptr, \ptr, 64
|
||||
AE_S64.I aed5, \ptr, .Lxchal_ofs_+0
|
||||
AE_S64.I aed6, \ptr, .Lxchal_ofs_+8
|
||||
AE_S64.I aed7, \ptr, .Lxchal_ofs_+16
|
||||
AE_S64.I aed8, \ptr, .Lxchal_ofs_+24
|
||||
AE_S64.I aed9, \ptr, .Lxchal_ofs_+32
|
||||
AE_S64.I aed10, \ptr, .Lxchal_ofs_+40
|
||||
AE_S64.I aed11, \ptr, .Lxchal_ofs_+48
|
||||
AE_S64.I aed12, \ptr, .Lxchal_ofs_+56
|
||||
addi \ptr, \ptr, 64
|
||||
AE_S64.I aed13, \ptr, .Lxchal_ofs_+0
|
||||
AE_S64.I aed14, \ptr, .Lxchal_ofs_+8
|
||||
AE_S64.I aed15, \ptr, .Lxchal_ofs_+16
|
||||
AE_SALIGN64.I u0, \ptr, .Lxchal_ofs_+24
|
||||
AE_SALIGN64.I u1, \ptr, .Lxchal_ofs_+32
|
||||
AE_SALIGN64.I u2, \ptr, .Lxchal_ofs_+40
|
||||
AE_SALIGN64.I u3, \ptr, .Lxchal_ofs_+48
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 56
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 184
|
||||
.endif
|
||||
.endm // xchal_cp1_store
|
||||
|
||||
/*
|
||||
* Macro to restore the state of TIE coprocessor AudioEngineLX.
|
||||
* Required parameters:
|
||||
* ptr Save area pointer address register (clobbered)
|
||||
* (register must contain a 8 byte aligned address).
|
||||
* at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
|
||||
* registers are clobbered, the remaining are unused).
|
||||
* Optional parameters are the same as for xchal_ncp_load.
|
||||
*/
|
||||
#define xchal_cp_AudioEngineLX_load xchal_cp1_load
|
||||
.macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
|
||||
xchal_sa_start \continue, \ofs
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+0
|
||||
wur.AE_OVF_SAR \at1 // ureg 240
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+4
|
||||
wur.AE_BITHEAD \at1 // ureg 241
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+8
|
||||
wur.AE_TS_FTS_BU_BP \at1 // ureg 242
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+12
|
||||
wur.AE_CW_SD_NO \at1 // ureg 243
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+16
|
||||
wur.AE_CBEGIN0 \at1 // ureg 246
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+20
|
||||
wur.AE_CEND0 \at1 // ureg 247
|
||||
AE_L64.I aed0, \ptr, .Lxchal_ofs_+24
|
||||
AE_L64.I aed1, \ptr, .Lxchal_ofs_+32
|
||||
AE_L64.I aed2, \ptr, .Lxchal_ofs_+40
|
||||
AE_L64.I aed3, \ptr, .Lxchal_ofs_+48
|
||||
AE_L64.I aed4, \ptr, .Lxchal_ofs_+56
|
||||
addi \ptr, \ptr, 64
|
||||
AE_L64.I aed5, \ptr, .Lxchal_ofs_+0
|
||||
AE_L64.I aed6, \ptr, .Lxchal_ofs_+8
|
||||
AE_L64.I aed7, \ptr, .Lxchal_ofs_+16
|
||||
AE_L64.I aed8, \ptr, .Lxchal_ofs_+24
|
||||
AE_L64.I aed9, \ptr, .Lxchal_ofs_+32
|
||||
AE_L64.I aed10, \ptr, .Lxchal_ofs_+40
|
||||
AE_L64.I aed11, \ptr, .Lxchal_ofs_+48
|
||||
AE_L64.I aed12, \ptr, .Lxchal_ofs_+56
|
||||
addi \ptr, \ptr, 64
|
||||
AE_L64.I aed13, \ptr, .Lxchal_ofs_+0
|
||||
AE_L64.I aed14, \ptr, .Lxchal_ofs_+8
|
||||
AE_L64.I aed15, \ptr, .Lxchal_ofs_+16
|
||||
AE_LALIGN64.I u0, \ptr, .Lxchal_ofs_+24
|
||||
AE_LALIGN64.I u1, \ptr, .Lxchal_ofs_+32
|
||||
AE_LALIGN64.I u2, \ptr, .Lxchal_ofs_+40
|
||||
AE_LALIGN64.I u3, \ptr, .Lxchal_ofs_+48
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 56
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 8, 8
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 184
|
||||
.endif
|
||||
.endm // xchal_cp1_load
|
||||
|
||||
#define XCHAL_CP1_NUM_ATMPS 1
|
||||
#define XCHAL_SA_NUM_ATMPS 1
|
||||
|
||||
/* Empty macros for unconfigured coprocessors: */
|
||||
.macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
|
||||
*
|
||||
* NOTE: This header file is not meant to be included directly.
|
||||
*/
|
||||
|
||||
/* This header file describes this specific Xtensa processor's TIE extensions
|
||||
that extend basic Xtensa core functionality. It is customized to this
|
||||
Xtensa processor configuration.
|
||||
|
||||
Copyright (c) 1999-2014 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_H
|
||||
#define _XTENSA_CORE_TIE_H
|
||||
|
||||
#define XCHAL_CP_NUM 2 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
|
||||
|
||||
/* Basic parameters of each coprocessor: */
|
||||
#define XCHAL_CP1_NAME "AudioEngineLX"
|
||||
#define XCHAL_CP1_IDENT AudioEngineLX
|
||||
#define XCHAL_CP1_SA_SIZE 184 /* size of state save area */
|
||||
#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
|
||||
#define XCHAL_CP7_NAME "XTIOP"
|
||||
#define XCHAL_CP7_IDENT XTIOP
|
||||
#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
|
||||
#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
|
||||
|
||||
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
|
||||
#define XCHAL_CP0_SA_SIZE 0
|
||||
#define XCHAL_CP0_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP3_SA_SIZE 0
|
||||
#define XCHAL_CP3_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 36
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
* Detailed contents of save areas.
|
||||
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
|
||||
* before expanding the XCHAL_xxx_SA_LIST() macros.
|
||||
*
|
||||
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
*
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
*
|
||||
* To filter out certain registers, e.g. to expand only the non-global
|
||||
* registers used by the compiler, you can do something like this:
|
||||
*
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define SELCC0(p...)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELAK2(p...)
|
||||
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 9
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 0
|
||||
#define XCHAL_CP0_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP1_SA_NUM 26
|
||||
#define XCHAL_CP1_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1010, aed,0 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1011, aed,1 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1012, aed,2 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1013, aed,3 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1014, aed,4 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1015, aed,5 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1016, aed,6 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1017, aed,7 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1018, aed,8 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1019, aed,9 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x101A, aed,10 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x101B, aed,11 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x101C, aed,12 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x101D, aed,13 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x101E, aed,14 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x101F, aed,15 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1020, u,0 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1021, u,1 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1022, u,2 , 64,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1023, u,3 , 64,0,0,0)
|
||||
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 0
|
||||
#define XCHAL_CP3_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
|
||||
/* Byte length of instruction from its first byte, per FLIX. */
|
||||
#define XCHAL_BYTE0_FORMAT_LENGTHS \
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
|
|
@ -0,0 +1,383 @@
|
|||
/*
|
||||
* Xtensa processor core configuration information.
|
||||
*
|
||||
* This file is subject to the terms and conditions of version 2.1 of the GNU
|
||||
* Lesser General Public License as published by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (c) 1999-2009 Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 1 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 1 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* floating point pkg */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 800000 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "test_mmuhifi_c3" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_CORE_DESCRIPTION "test_mmuhifi_c3"
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x00005A6A /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC1B3CBFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x10405A6A /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX3.0.0" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 230000 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX3 1
|
||||
#define XCHAL_HW_REL_LX3_0 1
|
||||
#define XCHAL_HW_REL_LX3_0_0 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 230000 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 230000 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 8
|
||||
#define XCHAL_DCACHE_SETWIDTH 8
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 2
|
||||
#define XCHAL_DCACHE_WAYS 2
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 8
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 8
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 12 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00000000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00000FFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00000FFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 1
|
||||
#define XCHAL_INT9_LEVEL 1
|
||||
#define XCHAL_INT10_LEVEL 1
|
||||
#define XCHAL_INT11_LEVEL 1
|
||||
#define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFF000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000004
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00000E3B
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00000140
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 8 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
/* (There are many interrupts each at level(s) 1.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt vectors/levels.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT7_NUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT8_NUM 11 /* (intlevel 1) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00000500
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0xD0000340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00000340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000280
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 0 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* This header file contains assembly-language definitions (assembly
|
||||
* macros, etc.) for this specific Xtensa processor's TIE extensions
|
||||
* and options. It is customized to this Xtensa processor configuration.
|
||||
*
|
||||
* This file is subject to the terms and conditions of version 2.1 of the GNU
|
||||
* Lesser General Public License as published by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 1999-2009 Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_ASM_H
|
||||
#define _XTENSA_CORE_TIE_ASM_H
|
||||
|
||||
/* Selection parameter values for save-area save/restore macros: */
|
||||
/* Option vs. TIE: */
|
||||
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
|
||||
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
|
||||
/* Whether used automatically by compiler: */
|
||||
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
|
||||
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
|
||||
/* ABI handling across function calls: */
|
||||
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
|
||||
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
|
||||
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
|
||||
/* Misc */
|
||||
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
|
||||
|
||||
|
||||
|
||||
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Save area ptr (clobbered): ptr (8 byte aligned)
|
||||
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
|
||||
*/
|
||||
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
|
||||
xchal_sa_start \continue, \ofs
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
rsr \at1, BR // boolean option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
rsr \at1, SCOMPARE1 // conditional store option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
rur \at1, THREADPTR // threadptr option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
|
||||
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Save area ptr (clobbered): ptr (8 byte aligned)
|
||||
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
|
||||
*/
|
||||
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
|
||||
xchal_sa_start \continue, \ofs
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wsr \at1, BR // boolean option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wsr \at1, SCOMPARE1 // conditional store option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wur \at1, THREADPTR // threadptr option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
|
||||
|
||||
|
||||
#define XCHAL_NCP_NUM_ATMPS 1
|
||||
|
||||
|
||||
|
||||
/* Macro to save the state of TIE coprocessor AudioEngineLX.
|
||||
* Save area ptr (clobbered): ptr (8 byte aligned)
|
||||
* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed)
|
||||
*/
|
||||
#define xchal_cp_AudioEngineLX_store xchal_cp1_store
|
||||
/* #define xchal_cp_AudioEngineLX_store_a2 xchal_cp1_store a2 a3 a4 a5 a6 */
|
||||
.macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
|
||||
xchal_sa_start \continue, \ofs
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 0, 1, 8
|
||||
rur240 \at1 // AE_OVF_SAR
|
||||
s32i \at1, \ptr, 0
|
||||
rur241 \at1 // AE_BITHEAD
|
||||
s32i \at1, \ptr, 4
|
||||
rur242 \at1 // AE_TS_FTS_BU_BP
|
||||
s32i \at1, \ptr, 8
|
||||
rur243 \at1 // AE_SD_NO
|
||||
s32i \at1, \ptr, 12
|
||||
AE_SP24X2S.I aep0, \ptr, 16
|
||||
AE_SP24X2S.I aep1, \ptr, 24
|
||||
AE_SP24X2S.I aep2, \ptr, 32
|
||||
AE_SP24X2S.I aep3, \ptr, 40
|
||||
AE_SP24X2S.I aep4, \ptr, 48
|
||||
AE_SP24X2S.I aep5, \ptr, 56
|
||||
addi \ptr, \ptr, 64
|
||||
AE_SP24X2S.I aep6, \ptr, 0
|
||||
AE_SP24X2S.I aep7, \ptr, 8
|
||||
AE_SQ56S.I aeq0, \ptr, 16
|
||||
AE_SQ56S.I aeq1, \ptr, 24
|
||||
AE_SQ56S.I aeq2, \ptr, 32
|
||||
AE_SQ56S.I aeq3, \ptr, 40
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 64
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 112
|
||||
.endif
|
||||
.endm // xchal_cp1_store
|
||||
|
||||
/* Macro to restore the state of TIE coprocessor AudioEngineLX.
|
||||
* Save area ptr (clobbered): ptr (8 byte aligned)
|
||||
* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP1_NUM_ATMPS needed)
|
||||
*/
|
||||
#define xchal_cp_AudioEngineLX_load xchal_cp1_load
|
||||
/* #define xchal_cp_AudioEngineLX_load_a2 xchal_cp1_load a2 a3 a4 a5 a6 */
|
||||
.macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
|
||||
xchal_sa_start \continue, \ofs
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 0, 1, 8
|
||||
l32i \at1, \ptr, 0
|
||||
wur240 \at1 // AE_OVF_SAR
|
||||
l32i \at1, \ptr, 4
|
||||
wur241 \at1 // AE_BITHEAD
|
||||
l32i \at1, \ptr, 8
|
||||
wur242 \at1 // AE_TS_FTS_BU_BP
|
||||
l32i \at1, \ptr, 12
|
||||
wur243 \at1 // AE_SD_NO
|
||||
addi \ptr, \ptr, 80
|
||||
AE_LQ56.I aeq0, \ptr, 0
|
||||
AE_LQ56.I aeq1, \ptr, 8
|
||||
AE_LQ56.I aeq2, \ptr, 16
|
||||
AE_LQ56.I aeq3, \ptr, 24
|
||||
AE_LP24X2.I aep0, \ptr, -64
|
||||
AE_LP24X2.I aep1, \ptr, -56
|
||||
AE_LP24X2.I aep2, \ptr, -48
|
||||
AE_LP24X2.I aep3, \ptr, -40
|
||||
AE_LP24X2.I aep4, \ptr, -32
|
||||
AE_LP24X2.I aep5, \ptr, -24
|
||||
AE_LP24X2.I aep6, \ptr, -16
|
||||
AE_LP24X2.I aep7, \ptr, -8
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 80
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 112
|
||||
.endif
|
||||
.endm // xchal_cp1_load
|
||||
|
||||
#define XCHAL_CP1_NUM_ATMPS 1
|
||||
#define XCHAL_SA_NUM_ATMPS 1
|
||||
|
||||
/* Empty macros for unconfigured coprocessors: */
|
||||
.macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* This header file describes this specific Xtensa processor's TIE extensions
|
||||
* that extend basic Xtensa core functionality. It is customized to this
|
||||
* Xtensa processor configuration.
|
||||
*
|
||||
* This file is subject to the terms and conditions of version 2.1 of the GNU
|
||||
* Lesser General Public License as published by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 1999-2009 Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_H
|
||||
#define _XTENSA_CORE_TIE_H
|
||||
|
||||
#define XCHAL_CP_NUM 1 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
|
||||
|
||||
/* Basic parameters of each coprocessor: */
|
||||
#define XCHAL_CP1_NAME "AudioEngineLX"
|
||||
#define XCHAL_CP1_IDENT AudioEngineLX
|
||||
#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */
|
||||
#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
|
||||
|
||||
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
|
||||
#define XCHAL_CP0_SA_SIZE 0
|
||||
#define XCHAL_CP0_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP3_SA_SIZE 0
|
||||
#define XCHAL_CP3_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
#define XCHAL_CP7_SA_SIZE 0
|
||||
#define XCHAL_CP7_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 12
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
* Detailed contents of save areas.
|
||||
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
|
||||
* before expanding the XCHAL_xxx_SA_LIST() macros.
|
||||
*
|
||||
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
*
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
*
|
||||
* To filter out certain registers, e.g. to expand only the non-global
|
||||
* registers used by the compiler, you can do something like this:
|
||||
*
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define SELCC0(p...)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELAK2(p...)
|
||||
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 3
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 0
|
||||
#define XCHAL_CP0_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP1_SA_NUM 16
|
||||
#define XCHAL_CP1_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0)
|
||||
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 0
|
||||
#define XCHAL_CP3_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
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Reference in New Issue