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Author SHA1 Message Date
Thomas Gleixner 9952f6918d treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:29:52 -07:00
Thierry Reding 755c47ed94 ARM: tegra: cpuidle: Add missing cpuidle.h include
Some of the functions implemented are flagged as not having a prototype
defined when building with W=1. Include the header to avoid these build
warnings and add a prototype as well as a dummy implementation for the
tegra_cpuidle_pcie_irqs_in_use() function.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-10 16:17:59 +02:00
Stephen Warren b4f173752a ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
Tegra20 HW appears to have a bug such that PCIe device interrupts,
whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To
work around this, simply disable LP2 if any PCIe devices with interrupts
are present. Detect this via the IRQ domain map operation. This is
slightly over-conservative; if a device with an interrupt is present but
the driver does not actually use them, LP2 will still be disabled.
However, this is a reasonable trade-off which enables a simpler
workaround.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2013-08-13 12:07:56 -06:00
Joseph Lo b046a65f23 ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func
Clean up the Tegra CPUidle init function by using IS_ENABLED for multi
SoCs management in the init function.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-06-05 11:44:54 -06:00
Joseph Lo e22dc2b256 ARM: tegra: cpuidle: move the init function behind the suspend init function
One of the state of CPUidle on Tegra can power gate the CPU and the
vdd_cpu rail. But it depends on some configurations from DT and a common
hook function for different Tegra SoCs to power gate the CPU rail. And
these stuffs are initialized after common Tegra suspend init function. So
we move the CPUidle init behind the suspend init function. And making the
CPUidle driver more generic.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-06-05 11:44:53 -06:00
Joseph Lo 51dc5259e8 ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support
Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-29 11:01:23 -07:00
Joseph Lo 0b25e25bef ARM: tegra: cpuidle: separate cpuidle driver for different chips
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15 15:09:20 -07:00