commit 634f0348fe upstream.
Commit cad6fade6e ("xtensa: clean up WSR*/RSR*/get_sr/set_sr") removed
{RSR,WSR}_CPENABLE from xtensa code, but did not fix up all users,
breaking gpio-xtensa driver build. Update gpio-xtensa to use
new xtensa_{get,set}_sr API.
Cc: stable@vger.kernel.org # v5.0+
Fixes: cad6fade6e ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This is a GPIO driver so include only <linux/gpio/driver.h>.
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For completion, sweep the floor from all gpiochip_add() usage so
we can remove that function and get rid of the function wrapper
gpiochip_add().
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In xtensa coprocessors may exist without coprocessor context, i.e. they cannot
be disabled/enabled. In this case the RSR_CPENABLE/WSR_CPENABLE are undefined,
thus breaking the build. Fix the build by adding dummy versions of
enable_cp/disable_cp in this case.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIO32 is a standard optional extension to the Xtensa architecture
core that provides preconfigured output and input ports for intra
SoC signaling. The GPIO32 option is implemented as 32bit Tensilica
Instruction Extension (TIE) output state called EXPSTATE, and 32bit
input wire called IMPWIRE. This driver treats input and output
states as two distinct devices.
v3:
* Use BUG() in xtensa_impwire_set_value() to indicate that
it should never be called (Linus Walleij)
v2:
* Address the comments of Linus Walleij:
- Add a few comments
- Expand commit log message
- Use the BIT() macro for bit offsets
- Rewrite CPENABLE handling as static inlines
- Use device_initcall()
* Depend on !SMP for reason explained in the comments (Marc Gauthier)
* Use XCHAL_CP_ID_XTIOP to enable/disable GPIO32 only
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Max Filippov