commit 3b7f9dbb82 upstream.
The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware
does not have a FIFO, which means it generates an interrupt for each
conversion sequence. At one 1MSPS this creates an interrupt storm that
causes the system to soft-lock.
For this reason the driver limits the maximum samplerate to 150kSPS.
Currently this check is only done when setting a new samplerate. But it is
also possible that the initial samplerate configured in the FPGA bitstream
exceeds the limit.
In this case when starting to capture data without first changing the
samplerate the system can overload.
To prevent this check the currently configured samplerate in the probe
function and reduce it to the maximum if necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes: bdc8cda1d0 ("iio:adc: Add Xilinx XADC driver")
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 8bef455c8b upstream.
The XADC has two internal ADCs. Depending on the mode it is operating in
either one or both of them are used. The device manual calls this
continuous (one ADC) and simultaneous (both ADCs) mode.
The meaning of the sequencing register for the aux channels changes
depending on the mode.
In continuous mode each bit corresponds to one of the 16 aux channels. And
the single ADC will convert them one by one in order.
In simultaneous mode the aux channels are split into two groups the first 8
channels are assigned to the first ADC and the other 8 channels to the
second ADC. The upper 8 bits of the sequencing register are unused and the
lower 8 bits control both ADCs. This means a bit needs to be set if either
the corresponding channel from the first group or the second group (or
both) are set.
Currently the driver does not have the special handling required for
simultaneous mode. Add it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes: bdc8cda1d0 ("iio:adc: Add Xilinx XADC driver")
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit f954b098fb upstream.
When enabling the trigger and unmasking the end-of-sequence (EOS) interrupt
the EOS interrupt should be cleared from the status register. Otherwise it
is possible that it was still set from a previous capture. If that is the
case the interrupt would fire immediately even though no conversion has
been done yet and stale data is being read from the device.
The old code only clears the interrupt if the interrupt was previously
unmasked. Which does not make much sense since the interrupt is always
masked at this point and in addition masking the interrupt does not clear
the interrupt from the status register. So the clearing needs to be done
unconditionally.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes: bdc8cda1d0 ("iio:adc: Add Xilinx XADC driver")
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit e44ec7794d upstream.
The check for shutting down the second ADC is inverted. This causes it to
be powered down when it should be enabled. As a result channels that are
supposed to be handled by the second ADC return invalid conversion results.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes: bdc8cda1d0 ("iio:adc: Add Xilinx XADC driver")
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Based on 1 normalized pattern(s):
licensed under the gpl 2
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 135 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Steve Winslow <swinslow@gmail.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528170026.071193225@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In remove, the clock is disabled before canceling the
delayed work. This means that the delayed work may be
touching unclocked hardware.
Fix by disabling the clock after the delayed work is
fully canceled. This is consistent with the probe error
path order.
Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
If probe errors out after request_irq(), its error path
does not explicitly cancel the delayed work, which may
have been scheduled by the interrupt handler.
This means the delayed work may still be running when
the core frees the private structure (struct xadc).
This is a potential use-after-free.
Fix by inserting cancel_delayed_work_sync() in the probe
error path.
Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
When cancel_delayed_work() returns, the delayed work may still
be running. This means that the core could potentially free
the private structure (struct xadc) while the delayed work
is still using it. This is a potential use-after-free.
Fix by calling cancel_delayed_work_sync(), which waits for
any residual work to finish before returning.
Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
In function xadc_probe, xadc_write_adc_reg can return an error value
when write fails. The fix checks for the return value consistent with
other invocations of the latter function.
Signed-off-by: Aditya Pakki <pakki001@umn.edu>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Enabling the Interrupts before registering the irq handler is a bad
idea. This patch corrects the same for XADC driver.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This patch avoids getting irq number in xadc_remove function. Instead
store 'irq' in xadc struct and use xadc->irq wherever needed.
This patch also resolves a warning reported by coverity where it asks to
check return value of platform_get_irq() for any errors in xadc_remove.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This patch limits the xadc pcap clock frequency value to be less than
200MHz. This fixes the issue when zynq is booted at higher frequency
values, pcap crosses the maximum limit of 200MHz(Fmax) as it is derived
from IOPLL.
If this limit is crossed it is required to alter the WEDGE and REDGE
bits of XADC_CFG register to make timings better in the interface. So to
avoid alteration of these bits every time, the pcap value should not
cross the Fmax limit.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This patch adds check for return values from clock related functions.
This was reported by static code analysis tool.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This patch removes dead code from xadc_zynq_setup. The condition
"if (tck_rate > XADC_ZYNQ_TCK_RATE_MAX)" cannot be true at any point of
time. There is also an incompatible parameter used in the code.
This patch fixes the same reported by coverity.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
The equivalent of both of these are now done via macro magic when
the relevant register calls are made. The actual structure
elements will shortly go away.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
clk_prepare_enable() can fail here and we must check its return value.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Reorder error handling labels in order to match the way resources have
been allocated.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Usual mixed bag, but the big item perhaps in this series is the DMA buffer
support added by Lars-Peter Clausen. It's been in the works for a long time
and it will be interesting to see what hardware support shows up now that
this is available.
New core features + associate cleanup.
* Add generic DMA buffer infrastructure
* Add a DMAengine framework based buffer
Also associated minor changes.
- Set the device buffer watermark based on the minimum watermark for all
attached buffers rather than just the 'primary' one.
- iio_buffer_init - only set the watermark default if one hasn't already
been provided. This allows simple support for devices with a fixed
watermark.
- read only attribute for watermark on fixed watermark devices.
- add explicit buffer enable/disable callbacks to allow the buffer to
do more than trivial actions when it is being turned on and off.
* IIO_VAL_INT support in write_raw_get_fmt function.
New device support
* Freescale MMA7455/7456L accelerometers
* Memsic MXC6255XC accelerometer
* ST lis2dh12 accelerometer
* TI ADS8688 ADC
* TI Palamas (twl6035/7) gpadc
New driver features
* mma8452
- support either of the available interrupt pins to cope with the case
where board layout has lead to a particular one being connected.
Staging graduation
* Dummy driver
- this driver acts as both an example and a test device for those with
out hardware to develop userspace code against.
Cleanups and minor bits and bobs.
* treewide
- Sort out the ordering of iio_device_register/unregister vs runtime
pm function calls so that it's all nice and consistent and not race
prone.
- Check sscanf return values. None of the cases will actually happen as
the strings are supplied internally, but best to be consistent on this.
* ad7780
- switch over to the gpio descriptor interface and remove the now unused
platform data which gets rid of a header entirely.
* ad7793
- drop a pointless else statement.
* at91_adc
- Swap kmalloc_array in for a kmalloc doing the same job.
* dummy
- get rid of some commented out lines that snuck in during the move of
the driver.
* lm3533-als
- Print an error message on provision of an invalid resistance.
* mcp320x
- Add compatible strings with vendor prefix and deprecate those with
no vendor prefix.
* mxs-lradc
- Use BIT macro in various places rather than shifted ones.
* pa12203001
- Power off the chip if the registration fails.
* pulsedlight-lidar-lite
- add runtime PM support.
* xilinx XADC
- constify an iio_buffer_setup_ops structure.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJWUcmhAAoJEFSFNJnE9BaIyjYP/0A+CZMUqIGbYG9qFxnq7yYZ
977Wt/gGI8+Jq5RwNw6gTfhp2GrCN+5gzDbE2mBEn94c6SKBrj2Q9trW1FQ+Nhfx
9bZoyq3ZPRCV+efEDGfeK/JWRwv+V6IWwAF2J/iCPWpRMTEsIW5kM1JSO3ISlnma
diyil1hefGTJY8aCqGApthfX4fyZK98oCV6zojxpCZfFPdsa+vf5n1RQ143odnOk
6NSfXHYLI+2e+mJ1lw4GdpZdF+rF+7jWsUYC5EDNmvlIJYiKmm13whSQeWO0NHo8
oD0pYboSIWnmdXx4s3RbWF2+Y28O1+oJDKZfXabB8DjVwtvlGnmWBRhgKji2e6E6
Hhct83YbDWtEpbNkXcWpnc5v5ynmAMTYTxADhinTGUtVQh3Q4wWduuoHK6IyeI4s
dbfpO2Wh6N/5k3a4UoA69IcI2DzPzb2sIFWpdS8wuNv5xDhV2OmmY2PjTfq2w+Qz
hEoMCNDUG6rQAYf4auXK5JjhI4CaG/mz/qjIibTUqGODYECzQQyvq+c2Gdq0S8O/
CUHOgui6aHbyuhWmXlEzhhkjuvBQZYaTxCA+LGMzy8w7UY9m4n5L/fX9M9IfFsMH
NFCPrUfmxKPQj/mHlhu7KHaTMUlQ0pTqV5flSwqsjstZ2QddvI5EAKiLwIEhg7/2
RpnOZoiFIxykduEYLxeh
=CfCl
-----END PGP SIGNATURE-----
Merge tag 'iio-for-4.5a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next
Jonathan writes:
First set of new device support, features and cleanups for IIO in the 4.5 cycle
Usual mixed bag, but the big item perhaps in this series is the DMA buffer
support added by Lars-Peter Clausen. It's been in the works for a long time
and it will be interesting to see what hardware support shows up now that
this is available.
New core features + associate cleanup.
* Add generic DMA buffer infrastructure
* Add a DMAengine framework based buffer
Also associated minor changes.
- Set the device buffer watermark based on the minimum watermark for all
attached buffers rather than just the 'primary' one.
- iio_buffer_init - only set the watermark default if one hasn't already
been provided. This allows simple support for devices with a fixed
watermark.
- read only attribute for watermark on fixed watermark devices.
- add explicit buffer enable/disable callbacks to allow the buffer to
do more than trivial actions when it is being turned on and off.
* IIO_VAL_INT support in write_raw_get_fmt function.
New device support
* Freescale MMA7455/7456L accelerometers
* Memsic MXC6255XC accelerometer
* ST lis2dh12 accelerometer
* TI ADS8688 ADC
* TI Palamas (twl6035/7) gpadc
New driver features
* mma8452
- support either of the available interrupt pins to cope with the case
where board layout has lead to a particular one being connected.
Staging graduation
* Dummy driver
- this driver acts as both an example and a test device for those with
out hardware to develop userspace code against.
Cleanups and minor bits and bobs.
* treewide
- Sort out the ordering of iio_device_register/unregister vs runtime
pm function calls so that it's all nice and consistent and not race
prone.
- Check sscanf return values. None of the cases will actually happen as
the strings are supplied internally, but best to be consistent on this.
* ad7780
- switch over to the gpio descriptor interface and remove the now unused
platform data which gets rid of a header entirely.
* ad7793
- drop a pointless else statement.
* at91_adc
- Swap kmalloc_array in for a kmalloc doing the same job.
* dummy
- get rid of some commented out lines that snuck in during the move of
the driver.
* lm3533-als
- Print an error message on provision of an invalid resistance.
* mcp320x
- Add compatible strings with vendor prefix and deprecate those with
no vendor prefix.
* mxs-lradc
- Use BIT macro in various places rather than shifted ones.
* pa12203001
- Power off the chip if the registration fails.
* pulsedlight-lidar-lite
- add runtime PM support.
* xilinx XADC
- constify an iio_buffer_setup_ops structure.
This set does not include those for issues introduced during the merge
window. Fixes of those will follow in a future series.
* ad5064
- Make sure the local i2c_write returns 0 on success rather than the
number of bytes transfered. Otherwise we report an error on all writes.
- Fix a shift for ad5629 and ad5669 which gives incorrect DAC output on
these parts.
* ad7793
- The product ID on the datasheet is wrong. Fix it in the driver.
* IIO_DUMMY_EVGEN
- select IRQ_WORK as a dependency.
* lpc32xx
- make sure clock is prepared before enabling.
* si7020
- data byte order was reversed. Fix it.
* vf610
- Internal temperature calculation was wrong if a different
reference voltage was used. Now use a linear interpolation
function to make it work over the full range.
- Fix a division by zero in the case of a device tree property
not being present (same issue two fixes).
* xilinx XADC
- VREFN scale was wrong - fix it.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJWSH0iAAoJEFSFNJnE9BaILcYP/Rb70yJE23oTx6iyMDLip/Im
7yG+TMh/mFJCrwmpvloRX4IxQ20WApQPEQRaO6ivcoykQ/8eGDK3hrHWiHwYNs9z
P+q1qxz0F0pnvWHPZ2UZ+p8ZNzuy9ovTSeeuAHQWMVSsPCgiQR3kq0hBVrvV4mVn
4AQejD0M/x69TWdisZtGJqKBZs44mXHbgqC6Xw/6u0MLpA8ZLHO2XAr9vaSA042T
PsYXbEMmb/ElRKwadbX4JCqrMsA3FhPx+qD7qPu14bsC8WR4tlNLIBzEmBQJotWf
8wjK7AF7Af/HMO5KjO6uJe+EdypMq1UjlmqeRWUZIGUlLtmjmkhnRzO4Qahsbx2K
6TEO1uNhOjg7JQGfeuL9fKMHI6QKkeFIJ/cl2ekRWRwbxS2kOmXA9HTCsxynrdAR
qC49Eqkbfr/F1vdgDx61JAWgWuZNdxFg3tiD3wP2BMjOipKBuKRt9CvHuOORW7Tp
aUPruyJduIpcVQBL+wbSElAc4XsjgL4+/KROcfG3x3zWKUjOux73G8WsgaSSQ4Fe
rP2stYFmZUigIpSW/vTwbdcN8tIT9S/XZjxF/mlP7azIQHyafWTVl6CUlphtewtY
YZVT2K+t07zQV2NgOi9J+H5yCPG39d1Fb1R4OsWF1Brq2QsQJwqR9Y1ERXiPEJzZ
DvylTHu0lxP+xgE/Xjuz
=362F
-----END PGP SIGNATURE-----
Merge tag 'iio-fixes-for-4.4a' of ssh://ra.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus
Jonathan writes:
First set of IIO fixes for the 4.4 cycle.
This set does not include those for issues introduced during the merge
window. Fixes of those will follow in a future series.
* ad5064
- Make sure the local i2c_write returns 0 on success rather than the
number of bytes transfered. Otherwise we report an error on all writes.
- Fix a shift for ad5629 and ad5669 which gives incorrect DAC output on
these parts.
* ad7793
- The product ID on the datasheet is wrong. Fix it in the driver.
* IIO_DUMMY_EVGEN
- select IRQ_WORK as a dependency.
* lpc32xx
- make sure clock is prepared before enabling.
* si7020
- data byte order was reversed. Fix it.
* vf610
- Internal temperature calculation was wrong if a different
reference voltage was used. Now use a linear interpolation
function to make it work over the full range.
- Fix a division by zero in the case of a device tree property
not being present (same issue two fixes).
* xilinx XADC
- VREFN scale was wrong - fix it.
The iio_buffer_setup_ops structures are never modified, so declare this one
as const, like the others.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The scaling factor for VREFN is 3.0/4096 (not 1.0/4096), just as for
VREFP. This is not immediately obvious from the specification (Xilinx
UG480), but has been confirmed by Xilinx support.
Suggested-by: Hartmut Knaack <knaack.h@gmx.de>
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The driver currently registers a pair of irq handlers using
request_threaded_irq(), however the synchronization mechanism between the
hardirq and the threadedirq handler is a regular spinlock.
Unfortunately, this breaks PREEMPT_RT builds, where a spinlock can sleep,
and is thus not able to be acquired from a hardirq handler. This patch gets
rid of the threaded handler and pushes all interrupt handling into the
hardirq context, and uses request_irq().
To validate that this change has no impact on RT performance, here are
cyclictest values with no processes running:
$ sudo cyclictest -S -m -p 98
policy: fifo: loadavg: 0.00 0.01 0.05 1/174 2539
T: 0 ( 1405) P:98 I:1000 C:167010520 Min: 9 Act: 12 Avg: 12 Max: 75
T: 1 ( 1862) P:98 I:1500 C:111340339 Min: 9 Act: 12 Avg: 12 Max: 73
Then, all xadc raw handles were accessed in a continuous loop via
/sys/bus/iio/devices/iio:device0:
$ sudo cyclictest -S -m -p 98
policy: fifo: loadavg: 7.84 7.70 7.63 3/182 4260
T: 0 ( 2559) P:98 I:1000 C:241557018 Min: 11 Act: 18 Avg: 21 Max: 74
T: 1 ( 2560) P:98 I:1500 C:161038006 Min: 10 Act: 21 Avg: 20 Max: 73
Signed-off-by: Xander Huff <xander.huff@ni.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The VREFN channel is bipolar, not unipolar. Small negative values do
occur (e.g., -1mV), and unsigned conversion maps them incorrectly to
large positive values (about +1V), so fix this.
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The scaling factor for VREFP is 3.0/4096, not 1.0/4096; fix this to get
correct readings.
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
For the "vccaux" channel, read the VCCAUX register, not VCCINT.
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
We want the fixes in there, and it resolves a merge issue with
drivers/iio/accel/bma180.c
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
There is no need to init .owner field.
Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"
This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Convert a zero return value on error to a negative one, as returned
elsewhere in the function.
A simplified version of the semantic match that finds this problem is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
(
if@p1 (\(ret < 0\|ret != 0\))
{ ... return ret; }
|
ret@p1 = 0
)
... when != ret = e1
when != &ret
*if(...)
{
... when != ret = e2
when forall
return ret;
}
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
argument has been ignored; adjust drivers accordingly
Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This driver
supports both interfaces and internally has a small abstraction layer that hides
the specifics of these interfaces from the main driver logic.
The ADC has a couple of internal channels which are used for voltage and
temperature monitoring of the FPGA as well as one primary and up to 16 channels
auxiliary channels for measuring external voltages. The external auxiliary
channels can either be directly connected each to one physical pin on the FPGA
or they can make use of an external multiplexer which is responsible for
multiplexing the external signals onto one pair of physical pins.
The voltage and temperature monitoring channels also have an event capability
which allows to generate a interrupt when their value falls below or raises
above a set threshold.
Buffered sampling mode is supported by the driver, but only for AXI-XADC since
the ZYNQ XADC interface does not have capabilities for supporting buffer mode
(no end-of-conversion interrupt). If buffered mode is supported the driver will
register two triggers. One "xadc-samplerate" trigger which will generate samples
with the configured samplerate. And one "xadc-convst" trigger which will
generate one sample each time the CONVST (conversion start) signal is asserted.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Lars-Peter Clausen