Update the R-Car H2 pin control driver to use the new macros for
describing pins without GPIO functionality. This replaces the use of
physical pin numbers on the R-Car H2 SoC (in 31x31 FCBGA package) by
symbolic enum values, referring to signal names.
Note that the user-visible names of these pins are still based on pin
numbers instead of signal names, to preserve DT backwards compatibility.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
There are two variants of the CPU_ALL_PORT() macro in use:
1. A three-parameter variant, to be provided for SoCs with a linear
GPIO pin space ("PORT style"),
2. A two-parameter variant, to be provided for SoCs with 32-port GPIO
banks ("GP port style").
Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and
to increase naming consistency.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Currently the PINMUX_CFG_REG_VAR() macro must be followed by
initialization data, specifying all enum IDs. Hence the macro itself
does not know anything about the enum IDs, preventing the macro from
performing any validation on it.
Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence both the register field widths and the enum
IDs are wrapped using the GROUP() macro.
No functional changes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Currently the PINMUX_CFG_REG() macro must be followed by initialization
data, specifying all enum IDs. Hence the macro itself does not know
anything about the enum IDs, preventing the macro from performing any
validation on it.
Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence the enum IDs are wrapped using a new macro
GROUPS().
No functional changes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Source files using -Exxx error codes should include <linux/errno.h>.
On ARM, this header file is included indirectly; on SuperH, it is not,
leading to "error: ‘EINVAL’ undeclared" failures when enabling
compile-testing later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Documentation for ES1.0 says that some bits in TDSEL must be set (ch
5.3.39 in R-Car H2 v0.91). However, the reset value of the register is
0, so software has to do it. Add this to the kernel driver to ensure
this is really done independent of firmware versions and use
whitelisting for ES versions known to need this.
This is needed for some SD cards supporting SDR104 transfer mode. For
me, TDSEL was not initialized by the firmware and I had problems with
the card when re-inserting it.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch updates license to use SPDX-License-Identifier
instead of verbose license text.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The pin controller drivers for all R-Car Gen2 SoCs have entries for the
EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2.
Add the missing pin to restore consistency.
Note that technically TX_ER is an optional signal in the MII bus, and
thus could have its own group, but this is currently not supported by
any R-Car Gen2 pin controller driver.
Fixes: 19ef697d1e ("sh-pfc: r8a7790: add EtherAVB pin groups")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
The Renesas Pin Function Controller uses two header files:
- sh_pfc.h, for use by both core code and SoC-specific drivers,
- core.h, for internal use by the core code only.
Several SoC-specific drivers include core.h, as they need the sh_pfc
structure, which is passed explicitly to the various SoC-specific
callbacks, and used there.
Hence move its definition from core.h to sh_pfc.h, and remove the
inclusion of core.h from all SoC-specific files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
All known hardware being able to switch voltages has the same POCCTRL
register. So, factor out the common code to the core and keep only
the pin-to-bit mapping SoC specific. Convert the only user, r8a7790.
In case POCCTRL should ever get more complex (more voltages to select?),
we should probably switch over to a describing array like drive strength
does currently.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.
Implement the {get,set}_io_voltage operations and set the related
capability flag for the associated pins.
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This macro describes a pinmux configuration that needs configuration in
both a Peripheral Function Select Register (IPSR) and in a
GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the
macro name for clarity.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Add pins, groups, and a function for SCIF_CLK, which is the external
clock source for the Baud Rate Generator for External Clock (BRG) on
(H)SCIF.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Many SoC needs each PORT_GP_x() macros, but we can share/reuse
same one.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This header file will be removed soon.
Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl
drivers only, to sh_pfc.h, and drop the #include.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but
also various other pinmux-related data (functions and marks).
Every single driver already calls its local array pinmux_data[].
Hence rename the sh_pfc_soc_info member to "pinmux_data".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
R8A7790/1 PFC drivers use almost identical 'union vin_data' and completely
identical VIN_DATA_PIN_GROUP() macro; we thus can move them into the shared
header file...
Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same.
Current PFC driver is very difficult to read, because macro names are
using different length.
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
PINMUX_IPSR_MODSEL_DATA(ipsr, ...)
It can be readable if we can use PINMUX_IPSR_MSEL() instead
of PINMUX_IPSR_MODSEL_DATA()
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add EtherAVB pin groups to R8A7790 PFC driver.
Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add MLB+ 3-pin mode pin group to R8A7790 PFC driver.
Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
development cycle:
- Antoine Tenart made the get_group_pins() vtable entry
optional.
- Antoine also provides an entirely new driver for the
Marvell Berlin SoC. This is unrelated to the existing
MVEBU hardware driver and warrants its own separate
driver.
- Reflected from the GPIO subsystem there is a number of
refactorings to make pin control drivers with gpiochips
use the new gpiolib irqchip helpers. The following
drivers were converted to use the new infrastructure:
- ST Microelectronics STiH416 and friends
- The Atmel AT91
- The CSR SiRF (Prima2)
- The Qualcomm MSM series
- Massive improvements in the Qualcomm MSM driver from
Bjorn Andersson, Andy Gross and Kumar Gala. Among those
new support for the IPQ8064 and MSM8x74 SoC variants.
- Support for the Freescale i.MX6 SoloX SoC variant.
- Massive improvements in the Allwinner sunxi driver from
Boris Brezillon, Maxime Ripard and Chen-Yu Tsai.
- Renesas PFC updates from Laurent Pinchart, Kuninori
Morimoto, Wolfram Sang and Magnus Damm.
- Cleanups and refactorings of the nVidia Tegra driver from
Stepgen Warren.
- The Exynos driver now supports the Exynos3250 SoC.
- Intel BayTrail updates from Jin Yao, Mika Westerberg.
- The MVEBU driver now supports the Orion5x SoC
variants, which is part of the effort of getting rid of
the old Marvell kludges in arch/arm/mach-orion5x
- Rockchip driver updates from Heiko Stuebner.
- A ton of cleanups and janitorial patches from Axel Lin.
- Some minor fixes and improvements here and there.
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Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next
Pull pin control changes from Linus Walleij:
"This is the bulk of pin control changes for the v3.16 development
cycle:
- Antoine Tenart made the get_group_pins() vtable entry optional.
- Antoine also provides an entirely new driver for the Marvell Berlin
SoC. This is unrelated to the existing MVEBU hardware driver and
warrants its own separate driver.
- reflected from the GPIO subsystem there is a number of refactorings
to make pin control drivers with gpiochips use the new gpiolib
irqchip helpers. The following drivers were converted to use the
new infrastructure:
* ST Microelectronics STiH416 and friends
* The Atmel AT91
* The CSR SiRF (Prima2)
* The Qualcomm MSM series
- massive improvements in the Qualcomm MSM driver from Bjorn
Andersson, Andy Gross and Kumar Gala. Among those new support for
the IPQ8064 and MSM8x74 SoC variants.
- support for the Freescale i.MX6 SoloX SoC variant.
- massive improvements in the Allwinner sunxi driver from Boris
Brezillon, Maxime Ripard and Chen-Yu Tsai.
- Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto,
Wolfram Sang and Magnus Damm.
- Cleanups and refactorings of the nVidia Tegra driver from Stepgen
Warren.
- the Exynos driver now supports the Exynos3250 SoC.
- Intel BayTrail updates from Jin Yao, Mika Westerberg.
- the MVEBU driver now supports the Orion5x SoC variants, which is
part of the effort of getting rid of the old Marvell kludges in
arch/arm/mach-orion5x
- Rockchip driver updates from Heiko Stuebner.
- a ton of cleanups and janitorial patches from Axel Lin.
- some minor fixes and improvements here and there"
* tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
pinctrl: sirf: fix a bad conflict resolution
pinctrl: msm: Add more MSM8X74 pin definitions
pinctrl: qcom: ipq8064: Fix naming convention
pinctrl: msm: Add missing sdc1 and sdc3 groups
pinctrl: sirf: switch to using allocated state container
pinctrl: Enable "power-source" to be extracted from DT files
pinctrl: sunxi: create irq/pin mapping during init
pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy
pinctrl: berlin: Use devm_ioremap_resource()
pinctrl: sirf: fix typo for GPIO bank number
pinctrl: sunxi: depend on RESET_CONTROLLER
pinctrl: sunxi: fix pin numbers passed to register offset helpers
pinctrl: add pinctrl driver for imx6sx
pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
pinctrl: msm: switch to using generic GPIO irqchip helpers
pinctrl: sunxi: Fix multiple registration issue
pinctrl: sunxi: Fix recursive dependency
pinctrl: berlin: add the BG2CD pinctrl driver
pinctrl: berlin: add the BG2 pinctrl driver
pinctrl: berlin: add the BG2Q pinctrl driver
...
The extra entry in the table makes SCIFA0_B, and all
peripherals after it, fail.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the muxing for the last missing i2c rcar core. Fix the sorting for
SH_PFC_PIN_NAMED while we are here.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A QSPI function set consists of 3 groups:
- qspi_ctrl (2 control wires)
- qspi_data2 (2 data wires, for Single/Dual SPI)
- qspi_data4 (4 data wires, for Quad SPI)
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Create a new group for the USB0 OVC/VBUS pin by itself. This
allows us to monitor PWEN as GPIO on the Lager board.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The arrays are never modified, declare them as const.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are VIN2 and VIN3 channels available on the R8A7790 SoC.
VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit.
Add both here, covering all possible data pin configurations.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Both VIN0 and VIN1 channels support identical input interfaces.
Add missing VIN1 pins here and organize them in the same pin
groups as VIN0.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
This reorganizes and renames VIN0 data pin groups to cover
all possible configurations. There's total of eight data
pin groups, one per each configuration. Most of the groups
share the same pin/mux array. Only the 18-bit configuration
needs a separate pin/mux array since in combines interleaved
data pins.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
This groups VIN0 HSYNC and VSYNC pins together
since one cannot be used without another.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
This drops superfluous "signal" word from the pin group names
and renames data_enable group to clkenb as in the h/w manual.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
There are four I2C interfaces on r8a7790, each of them can be connected to
one of the two respective I2C controllers, e.g. interface #0 can be
configured to work with I2C0 or with IIC0. Additionally some of those
interfaces can also use one of several pin sets. Interface #3 is special,
because it can be used in automatic mode for DVFS. It only has one set
of pins available and those pins cannot be used for anything else, they
also lack the GPIO function.
This patch uses the sh-pfc ability to configure pins, not associated with
GPIOs and adds support for I2C3 to the r8a7790 PFC set up.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Adds pinmux for i2c bus 1 and 2. (Pins for 0 and 3 are not multiplexed.)
Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Name the DU clock input 1 consistently with clock inputs 0 and 2.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Navigating through the source code is hard enough without having to
manually search for groups and functions.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Geert Uytterhoeven