Use a specific compatible string for 850D in order to limit DSD MCLK
frequency for platforms newer than 850D.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
SAI interface now is able to change at runtime the pll parent of the
master clock, so enable both 8k and 11k range of rates for AK codecs.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
With the current multipliers SAI isn't able to derive a correct bitclk.
e.g: When playing at 786Khz with current multiplier
MCLK = 22579200, requested freq 22579200 but SAI wants:
MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution
is to add a 2x factor to mclk.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
[ Aisheng: split codec changes ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to AK4497 RM the MCLK freq need to be set
externaly as function of LRCK frequency.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
for dsd, specify the slot number is 1, SND_SOC_DAIFMT_PDM is
used for DSD, and add constraint for sample rate.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
For 768kHz sample rate, the codec can't support 64fs mclk, only
can support 32fs mclk, so we can't fix the slot_width to 32, which
is for S32_LE, use params_physical_width(params) to instead of
hard code.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
This glues SAI interface with AK4497 DAC codec on i.MX boards.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
[ Aisheng: Makefile clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Shengjiu Wang