Add fsl,imx-audio-ak5552 to imx-ak5558 machine ASoC
driver, limit actual number of channels for ak5552
ADC support
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
In order to support the odd channels for ASRC case, we
force to enable TDM mode. In non-tdm case, we enable
multi lane to support multi channels, but limitation
is odd multi channels can't be supported.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Support EASRC in this sound card with FE-BE structure
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
According to AK5558 MCLK frequence must not exceed 36.864 MHz.
Limit maximum supported rate as function of max MCLK frequency,
sample bits and number of slots.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 236796cad225daa39d5b77d763a1d964dd4de4c9)
SAI interface now is able to change at runtime the pll parent of the
master clock, so enable both 8k and 11k range of rates for AK codecs.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Using TDM256 mode (our only supported mode) in order to
support 192KHz we would need a MCLK of 192000 * 512 = 98304000.
But maximum frequency supported by the Audio PLL is 4.91 MHz.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
In order for TDM to correctly work we need that MCLK and
BCLK to follow the values in Table 9.
Thus,
* TDM128: BCLK = 128fs, MCLK = 128-1024fs
* TDM256: BCLK = 256fs, MCLK = 256-1024fs
* TDM512: BCLK = 512fs, MCLK = 512-1024fs
We assume only support TDM256 for the moment.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
With the current multipliers SAI isn't able to derive a correct bitclk.
e.g: When recording at 786Khz with current multiplier
MCLK = 24576000, requested freq 24576000 but SAI wants:
MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution
is to add a 2x factor to mclk.
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
MCLK frequency is determined based on LRCK frequency, according
to the operation mode. Because AK5558 runs in Auto Mode, we use
table 5 from datasheet to set the correct MCLK.
Multiplier must be set twice as value shown in RM because SAI
MCLK must be at least double the BCLK.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Cosmin Samoila <cosmin.samoila@nxp.com>
In normal mode we need to test SAI capability of supporting
higher rates so adjust constraints list to allow 384KHz
and 768KHz.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Support only even number of channels greater than 2 and
rates multiple of 8000.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
For 768kHz sample rate, the codec can't support 64fs mclk, only
can support 32fs mclk, so we can't fix the slot_width to 32, which
is for S32_LE, use params_physical_width(params) to instead of
hard code.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add machine driver for i.MX boards that have AK5558 ADC attached to SAI.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
[ Aisheng: clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Adrian Alonso