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29 Commits (1ccea77e2a2687cae171b7987eb44730ec8c6d5f)

Author SHA1 Message Date
Gregory CLEMENT 69f5689b6b arm: dts: armada-*.dtsi: use SPDX-License-Identifier for most of the Armada SoCs
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html

Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-27 15:07:53 +02:00
Rob Herring 28fbb9c539 ARM: dts: marvell: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-08-03 14:29:22 +02:00
Andrew Lunn 0c8c9ff8ec ARM: dts: mvebu: Add PWM properties to .dtsi files
Add properties to the GPIO nodes for Armada 370/XP to allow them to be
also used as PWM lines.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
URL: https://patchwork.ozlabs.org/patch/427294/
[Ralph Sennhauser: Add new compatible string marvell,armada-370-gpio]
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-17 08:16:45 +02:00
Alexandre Belloni 24f0b6fe52 ARM: dts: mvebu: Correct license text
The license text has been mangled at some point then copy pasted across
multiple files. Restore it to what it should be.
Note that this is not intended as a license change.

Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-01-03 17:04:05 +01:00
Gregory CLEMENT 007d05d898 ARM: dts: armada-xp: Fixup pcie DT warnings
PCIe has a range property, so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-11-19 09:16:35 +01:00
Gregory CLEMENT 11f7135bb9 ARM: dts: armada-370-xp: add node labels
As it was previously done for kirkwood, this adds missing node labels to
Armada 370 and XP common and SoC specific nodes to allow to reference
them more easily.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-11-19 09:16:30 +01:00
Gregory CLEMENT 6cb51fac70 ARM: mvebu: armada-xp-mv78230: Relicense the device tree under GPLv2+/X11
The current GPL only licensing on the device tree makes it very
impractical for other software components licensed under another
license.

In order to make it easier for them to reuse our device trees,
relicense our device trees under a GPL/X11 dual-license.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2015-01-26 19:28:13 -06:00
Sebastian Hesselbarth 01c434225e ARM: mvebu: armada-xp: Use pinctrl node alias
Armada XP pinctrl node gained an alias, make use of it.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-02 18:57:16 +00:00
Sebastian Hesselbarth 264a05e19b ARM: mvebu: armada-xp: Add node alias to pinctrl and add base address
In other MVEBU SoCs, the pin controller node is called pin-ctrl with
its base address added. Also, we have a node alias to access the pinctrl
node easily. Fix this for Armada XP pinctrl nodes to be consistent with
other SoCs.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-02 18:52:06 +00:00
Sebastian Hesselbarth b324fa60ac ARM: mvebu: armada-xp: Consolidate pinctrl node
All current Armada XP SoCs have their pin controller at 0x18000/0x38.
Move the common properties of pinctrl nodes to armada-xp.dtsi to allow
to share pinctrl settings later.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-By: Benoit Masson <yahoo@perenite.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-02 18:50:16 +00:00
Thomas Petazzoni 3843607838 ARM: mvebu: update Armada XP DT for dynamic frequency scaling
In order to support dynamic frequency scaling:

 * the cpuclk Device Tree node needs to be updated to describe a
   second set of registers describing the PMU DFS registers.

 * the clock-latency property of the CPUs must be filled, otherwise
   the ondemand and conservative cpufreq governors refuse to work. The
   latency is high because the cost of a frequency transition is quite
   high on those CPUs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-16 12:54:13 +00:00
Thomas Petazzoni 231578565d ARM: mvebu: add enable-method property for CPUs
This commit updates the Armada XP Device Trees (for the three variants
of Armada XP) to declare the "enable-method" property for the CPUs,
which helps operating systems find the appropriate logic to manage the
CPUs, especially to boot secondary CPUs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:50:14 +00:00
Arnaud Ebalard 12b69a5997 ARM: mvebu: second PCIe unit of Armada XP mv78230 is only x1 capable
Various Marvell datasheets advertise second PCIe unit of mv78230
flavour of Armada XP as x4/quad x1 capable. This second unit is in
fact only x1 capable. This patch fixes current mv78230 .dtsi to
reflect that, i.e. makes 1.0 the second interface (instead of 2.0
at the moment). This was successfully tested on a mv78230-based
ReadyNAS 2120 platform with a x1 device (FL1009 XHCI controller)
connected to this second interface.

Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.10.x
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-11-23 15:29:06 +00:00
Thomas Petazzoni d4fa99417a ARM: mvebu: link PCIe controllers to the MSI controller
This commit adjusts the Armada 370 and Armada XP PCIe controllers
Device Tree informations to reference their MSI controller. In the
case of this platform, the MSI controller is implemented by the MPIC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Daniel Price <daniel.price@gmail.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-09-30 15:00:27 +00:00
Olof Johansson 6cbe0e1fea mvebu dt changes for v3.12
- kirkwood
     - add ZyXEL NSA310 board, fan for ReadyNAS Duo v2
 
  - mvebu
     - add ReadyNAS 102 board
 
  - misc dts updates and changes.
 
 v2:
  - dropped mv64xxx-i2c change
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Merge tag 'dt-3.12' of git://git.infradead.org/linux-mvebu into next/soc

From Jason Cooper:
mvebu dt changes for v3.12
 - kirkwood
    - add ZyXEL NSA310 board, fan for ReadyNAS Duo v2
 - mvebu
    - add ReadyNAS 102 board
 - misc dts updates and changes.

v2:
 - dropped mv64xxx-i2c change

* tag 'dt-3.12' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Fix the Armada 370/XP timer compatible strings
  ARM: mvebu: use dts pre-processor for readynas 102
  ARM: kirkwood: use dts pre-processor for nsa310 boards
  ARM: mvebu: use correct #interrupt-cells instead of #interrupts-cells
  ARM: Kirkwood: Add support for another ZyXEL NSA310 variant
  ARM: mvebu: Add Netgear ReadyNAS 102 board
  arm: kirkwood: readynas duo v2: Add GMT G762 Fan Controller

Signed-off-by: Olof Johansson <olof@lixom.net>

Conflicts:
	arch/arm/boot/dts/kirkwood-nsa310.dts
2013-08-29 10:01:40 -07:00
Thomas Petazzoni ca60985c00 ARM: mvebu: use correct #interrupt-cells instead of #interrupts-cells
The Device Tree information for the GPIO banks of the Armada 370 and
Armada XP SOCs was incorrectly using #interrupts-cells instead of
controller when using GPIO interrupts, since the GPIO bank DT node
wasn't recognized as a valid interrupt controller by the OF code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-08-16 13:02:07 +00:00
Jason Cooper f72b720ffe ARM: mvebu: use dts pre-processor for mv78230
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-08-07 20:05:02 +00:00
Ezequiel Garcia 14fd8ed0a7 ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.

Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-08-06 14:11:27 +00:00
Gregory CLEMENT 467f54b215 ARM: dts: mvebu: introduce internal-regs node
Introduce a 'internal-regs' subnode, under which all devices are
moved. This is not really needed for now, but will be for the
mvebu-mbus driver. This generates a lot of code movement since it's
indenting by one more tab all the devices.  So it was a good
opportunity to fix all the bad indentation.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15 15:00:24 +00:00
Gregory CLEMENT 82a682676c ARM: dts: mvebu: Convert all the mvebu files to use the range property
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15 15:00:21 +00:00
Thomas Petazzoni 1b2529d018 ARM: dts: mvebu: fix cpus section indentation
Align the cpu node indentation with the rest of the file

[gc]: added a commit description
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15 15:00:12 +00:00
Thomas Petazzoni 9d8f44f02d arm: mvebu: add PCIe Device Tree informations for Armada XP
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
units (two 4x or quad 1x and two 4x/1x). We therefore add the
necessary Device Tree informations to make those PCIe interfaces
usable.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-04-15 14:53:19 +00:00
Thomas Petazzoni 6d36e8e08f arm: mvebu: add pin muxing options for the SDIO interface on Armada XP
The SDIO interface is only available on pins MPP30/31/32/33/34/35 on
the various Armada XP variants, so we provide a pin muxing option for
this in the Armada XP .dtsi files.

Even though those muxing options are the same for MV78230, MV78260 and
MV78460, we keep them in each .dtsi file, because the number of pins,
and therefore the declaration of the pinctrl node, is different for
each SoC variant.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-02-28 18:57:09 +01:00
Thomas Petazzoni 5f79c651e8 arm: mvebu: use global interrupts for GPIOs on Armada XP
The Armada XP GPIO controller has two ways of notifying interrupts:
using global interrupts or using per-CPU interrupts. In an attempt to
use the best available features, the 'marvell,armadaxp-gpio'
compatible string selects a variant of the gpio-mvebu driver that
makes use of the per-CPU interrupts.

Unfortunately, this doesn't work properly in a SMP context, because we
fall into cases where the GPIO interrupt is enabled on CPU X at the
GPIO controller level, but on CPU Y at the interrupt controller
level. It is not yet clear how to fix that easily.

So for 3.8, our approach is to switch to global interrupts for GPIOs,
so that we do not fall into this per-CPU interrupts problem.

This patch therefore fixes GPIO interrupts on Armada XP
platforms. Without this patch, GPIO interrupts simply do not work
reliably, because their proper operation depends on which CPU the code
requesting the interrupt is running.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-01-08 12:35:46 +00:00
Andrew Lunn 41be8dc1a4 arm: mvebu: Add missing ; for cpu node.
The Armada XP MV78230 DT include file is missing a ; at the
end of the cpu node.

Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-01-06 17:53:22 +00:00
Thomas Petazzoni 44cfae9ac6 arm: mvebu: Armada XP MV78230 has two cores, not one
Contrary to our understanding at the time armada-xp-mv78230.dtsi was
written, the MV78230 variant of the Armada XP SoC has two cores and
not one. This patch updates the .dtsi file to take into account this
reality.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-01-06 17:53:16 +00:00
Gregory CLEMENT 9d2027830c clk: armada-370-xp: add support for clock framework
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
2012-11-20 14:46:48 +01:00
Thomas Petazzoni 397d59f3b5 arm: mvebu: add DT information for GPIO banks on Armada 370 and XP
The gpioX aliases are needed so that the driver can use
of_alias_get_id() to get a 0-based number of the GPIO bank, which we
then use to compute the base GPIO of the bank being probed. This is
similar to what gpio-mxs.c is doing.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22 14:51:40 +00:00
Thomas Petazzoni f3b42b7ce0 ARM: mvebu: Add pinctrl support to Armada XP SoCs
This commits adds the necessary device tree information to define the
compatible property for the pinctrl driver instance of Armada XP SoCs.

Until now, the device tree representation considered the Armada XP as
a single SoC. But in fact, there are three different SoCs in the
Armada XP families, with different number of CPU cores, different
number of Ethernet interfaces... and different number of muxable pins
or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for
the three SoCs of the Armada XP family. The current armada-xp-db.dts
evaluation board uses the MV78460 variant of the SoC.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22 14:50:21 +00:00