The fixes for this round are in drivers:
- jz4780 transfer fix for acking descriptors early
- fsl-qdma: clean registers on error
- dw-axi-dmac: null pointer dereference fix
- mediatek-cqdma: fix sleeping in atomic context
- tegra210-adma: fix bunch os issues like crashing in driver
probe, channel FIFO configuration etc.
- sprd: Fixes for possible crash on descriptor status, block
length overflow. For 2-stage transfer fix incorrect start,
configuration and interrupt handling.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJc+3afAAoJEHwUBw8lI4NHYe0P/RVwZso3RKbAALFg6MJLyWun
UpIJ9NA28xcKyghXa3mbq5gFgqkwJedACaXaik/wZr23+FJodg1afy7cfZRq3l5I
arOmc7U2HK78L+h6T6JbIRP+pxIHHlrMaVwyO2ZwQ2jJmwwV/KyXgfxmv2ZIc1cg
0M2C22pgy7oacK47eyjfcF/yH6PWARVaUlUHB+0pXXgwpImNl9IO+ritEzJg6hA2
boltBfHX86XB/qfbnHaqo7bGUhEY4kqQafHKDNUh+jm7GgoI5biVC7dtH7liI0es
U3I+RXFbOi4sxaY/j5aRgCNCnc7nUdU806ma3DPuTwybeca0ixttazjtB1p56ewU
/NkhiuWf/qShZkepGlB50l7CAJ4Q0of2tPFr8pnI9OdZl8MzcoHIhN95IT/aEByf
f0cbwv8lAeU948zm63axs5eS36M1yoV/cUzzeLatXWY3CS82FlTiEaWGnYkfZJ9j
DNOr7WGk81A66kNEDIq65H9qQd86kRdNgoy1f7DNxBOjzVTzXGIATM+zpb3W/tsb
Qb3i8OD9Lo4TzWCiDqbasGYKjAwGougcRKZWvSv/qfuItq/vGnChSNs7cMx73znJ
EfgG+/kiKEn2hj9E5eSduqOrBaL4g+AJlqb93fpH54Jjr3QaupvhCZ2bYhrb9QrU
rW3FZfGsAcrlsPbOlIOW
=Ca0d
-----END PGP SIGNATURE-----
Merge tag 'dmaengine-fix-5.2-rc4' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine fixes from Vinod Koul:
- jz4780 transfer fix for acking descriptors early
- fsl-qdma: clean registers on error
- dw-axi-dmac: null pointer dereference fix
- mediatek-cqdma: fix sleeping in atomic context
- tegra210-adma: fix bunch os issues like crashing in driver probe,
channel FIFO configuration etc.
- sprd: Fixes for possible crash on descriptor status, block length
overflow. For 2-stage transfer fix incorrect start, configuration and
interrupt handling.
* tag 'dmaengine-fix-5.2-rc4' of git://git.infradead.org/users/vkoul/slave-dma:
dmaengine: sprd: Add interrupt support for 2-stage transfer
dmaengine: sprd: Fix the right place to configure 2-stage transfer
dmaengine: sprd: Fix block length overflow
dmaengine: sprd: Fix the incorrect start for 2-stage destination channels
dmaengine: sprd: Add validation of current descriptor in irq handler
dmaengine: sprd: Fix the possible crash when getting descriptor status
dmaengine: tegra210-adma: Fix spelling
dmaengine: tegra210-adma: Fix channel FIFO configuration
dmaengine: tegra210-adma: Fix crash during probe
dmaengine: mediatek-cqdma: sleeping in atomic context
dmaengine: dw-axi-dmac: fix null dereference when pointer first is null
dmaengine: fsl-qdma: Add improvement
dmaengine: jz4780: Fix transfers being ACKed too soon
The mtk_cqdma_poll_engine_done() function takes a true/false parameter
where true means it's called from atomic context. There are a couple
places where it was set to false but it's actually in atomic context
so it should be true.
All the callers for mtk_cqdma_hard_reset() are holding a spin_lock and
in mtk_cqdma_free_chan_resources() we take a spin_lock before calling
the mtk_cqdma_poll_engine_done() function.
Fixes: b1f01e48df ("dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
We already need to zero out memory for dma_alloc_coherent(), as such
using dma_zalloc_coherent() is superflous. Phase it out.
This change was generated with the following Coccinelle SmPL patch:
@ replace_dma_zalloc_coherent @
expression dev, size, data, handle, flags;
@@
-dma_zalloc_coherent(dev, size, handle, flags)
+dma_alloc_coherent(dev, size, handle, flags)
Suggested-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
[hch: re-ran the script on the latest tree]
Signed-off-by: Christoph Hellwig <hch@lst.de>
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu <shun-chih.yu@mediatek.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has
a single ring is dedicated to memory-to-memory transfer through ring based
descriptor management.
Even though there is only one physical ring available inside HSDMA, the
driver can be easily extended to the support of multiple virtual channels
processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
