Commit graph

6 commits

Author SHA1 Message Date
Maxime Ripard 6f97dc8d46 ARM: sun6i: dt: Fix interrupt trigger types
The Allwinner A31 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A31 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org # 3.12+
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-11 17:15:24 -08:00
Maxime Ripard 439d9f5801 ARM: sun6i: Fix the APB2 clock gates register size
The APB2 clocks gates are only a 32 bits register wide, and not 2 as set
currently in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-10-05 15:36:10 +02:00
Maxime Ripard 98096560eb ARM: sun6i: Enable clock support in the DTSI
Now that the clock driver has support for the A31 clocks, we can add
them to the DTSI and start using them in the relevant hardware blocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-26 10:51:18 +02:00
Maxime Ripard ab4238cd05 ARM: sun6i: Add UART0 muxing options
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-22 00:19:16 +02:00
Maxime Ripard 140e1721d1 ARM: sunxi: dt: Add PIO controller to A31 DTSI
The A31 has a different set of pins than the one found on the A10 and
A13. Now that we have support for the A31 pin set in the pinctrl driver,
we can enable it in the DTSI with its own compatible.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-22 00:19:16 +02:00
Maxime Ripard 8aed3b3158 ARM: sunxi: Add Allwinner A31 DTSI
The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a
PowerVR GPU.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-16 23:18:22 +02:00