We ideally want the init_meminfo function to do nothing but return the
delta to be applied to PHYS_OFFSET - it should do nothing else. As we
can detect in platform init code whether we are running in the high
physical address space, move the platform notifier initialisation
entirely into the platform init code.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Tested-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The definition
static const char *axxia_dt_match[] __initconst = {
...
defines a changable array of constant strings. That is you must not do:
*axxia_dt_match[0] = 'k';
but
axxia_dt_match[0] = "different string";
is fine. So the annotation __initconst is wrong and yields a compiler
error when other really const variables are added with __initconst.
As the struct machine_desc member dt_compat is declared as
const char *const *dt_compat;
making the arrays const is the better alternative over changing all
annotations to __initdata.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Laura's series removed the meminfo structure and its no longer available.
Update keystone code to remove the usage of it.
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
With late code patching updates for LPAE machines has merged now and
memblock conversion from bootmem is on its way, Keystone can switch to
the coherent memory address space which starts beyond 4GB boundary.
The idmap alias needs are managed via virt_to_idmap() for boot purpose.
Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
As suggested by Olof Johansson at
http://www.spinics.net/lists/arm-kernel/msg314009.html.
It be better just keeping a "ti,keystone" top-level compatible and
just using that to probe. If so we don't have to touch the file
for new boards in the future.
So use common "ti,keystone" compatible in keystone.c for all boards.
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Keystone PM bus makes use of generic PM clock core backend. Since
generic PM clock core uses platform bus notifiers to track events like
ADD_DEVICE/DEL_DEVICE and to fill clock lists per each device, we need
to initialise Keystone PM domains before the platform devices have been
created.
Hence, fix it by moving keystone_pm_runtime_init() before platform
devices have been populated.
Reported-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Keystone II peripheral devices support 32-bit DMA and hence can access only
first 2GB of the memory address space. So set the platform dma_zone_size
to handle that case.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Fix the following compilation warning:
arch/arm/mach-keystone/keystone.c:74:2: warning: initialization from incompatible pointer type [enabled by default]
arch/arm/mach-keystone/keystone.c:74:2: warning: (near initialization for ‘__mach_desc_KEYSTONE.restart’) [enabled by default]
Signed-off-by: Vincent Stehlé <vincent.stehle@freescale.com>
Cc: Robin Holt <holt@sgi.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: trivial@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
Add basic SMP support for Keystone machines. This does not
include support for CPU hotplug for now.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: arm@kernel.org
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Texas Instruments Keystone family of multi-core devices are
based on ARM Cortex A15. Patch adds basic definitions for a
new Keystone sub-architecture in ARM.
The TCI66xxK2H Communications Infrastructure Keystone SoCs
are member of the C66x family based on TI's new KeyStone 2
multi-core SoC Architecture designed specifically for high
performance wireless and networking infrastructure applications.
The SOCs contains many subsystems like Cortex A15 ARM CorePacs,
C66XX DSP CorePacs, MSMC memory controller, Tera Net bus,
IP Network, Navigator, Hyperlink, 1G/10G Ethernet, Radio layers
and queue based communication systems.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: arm@kernel.org
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
