Commit graph

4 commits

Author SHA1 Message Date
Steve Longerbeam 46c121e03d media: staging/imx: Implement init_cfg subdev pad op
Implement the init_cfg pad op in all imx-media subdevices. The try
formats are initialized to the current active formats on all pads.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2018-02-26 10:32:06 -05:00
Krzysztof Hałasa 9ea57316a5 media: i.MX6: Fix MIPI CSI-2 LP-11 check
Bitmask for the MIPI CSI-2 data PHY status doesn't seem to be correct.
Fix it.

Signed-off-by: Krzysztof Ha?asa <khalasa@piap.pl>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-12-11 13:04:49 -05:00
Marek Vasut de2e04569d [media] media: imx: Drop warning upon multiple S_STREAM disable calls
Calling S_STREAM OFF multiple times on a video device is valid, although
dubious, practice. Instead of warning about it and setting stream count
lower than zero, just ignore the subsequent S_STREAM calls and correct
the stream count to zero.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-06-20 08:12:20 -03:00
Steve Longerbeam f5138526e4 [media] media: imx: Add MIPI CSI-2 Receiver subdev driver
Adds MIPI CSI-2 Receiver subdev driver. This subdev is required
for sensors with a MIPI CSI2 interface.

- Switch from the v4l2_of_ APIs to the v4l2_fwnode_ APIs.
- Add the function csi2ipu_gasket_init() to initialize the gasket at
  s_power(ON). The gasket needs to be programmed with the correct color
  component ordering to handle UYVY vs. YUYV ordered mbus formats from
  sensors. Note that the description of the CSI2IPU_GASKET register in
  the i.MX6 reference manual is wrong w.r.t bit 2 (the manual refers to
  this register as CSI2_SW_RST): setting bit 2 selects YUYV order, not UYVY.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
2017-06-20 07:42:41 -03:00