2 commits

Author	SHA1	Message	Date
Beniamino Galvani	550ab390d7	ARM: meson: DTS: enable L2 cache ... This enables the L2 cache controller available in Amlogic SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org>	2014-11-18 16:36:14 +01:00
Carlo Caione	6b112e2414	ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS ... The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2014-09-25 17:34:14 +02:00