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alistair23-linux
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2 Commits (4e8f2fc1a55d543717efb70e170b09e773d0542b)

Author SHA1 Message Date
Vineet Gupta ecd43afdbe ARCv2: save r30 on kernel entry as gcc uses it for code-gen 
This is not exposed to userspace debugers yet, which can be done
independently as a seperate patch !

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
 2017-01-10 11:51:33 -08:00
Vineet Gupta 1f6ccfff63 ARCv2: Support for ARCv2 ISA and HS38x cores 
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
 2015-06-22 14:06:55 +05:30