2 commits

Author	SHA1	Message	Date
Guo Ren	96354ad79e	csky: fixup CACHEV1 store instruction fast retire ... For I/O access, 810/807 store instruction fast retire will cause wrong primitive. For example: stw (clear interrupt source) stw (unmask interrupt controller) enable interrupt stw is fast retire instruction. When PC is run at enable interrupt stage, the clear interrupt source hasn't finished. It will cause another wrong irq-enter. So use mb() to prevent above. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Lu Baoquan <lu.baoquan@intellif.com>	2019-01-08 23:42:42 +08:00
Guo Ren	00a9730e10	csky: Cache and TLB routines ... This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>	2018-10-25 23:36:19 +08:00