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15 Commits (6e8fd6e493bfca83021cc6a8fd86d7f69bd14fc6)

Author SHA1 Message Date
Randy Dunlap ac3167257b headers: separate linux/mod_devicetable.h from linux/platform_device.h
At over 4000 #includes, <linux/platform_device.h> is the 9th most
#included header file in the Linux kernel.  It does not need
<linux/mod_devicetable.h>, so drop that header and explicitly add
<linux/mod_devicetable.h> to source files that need it.

   4146 #include <linux/platform_device.h>

After this patch, there are 225 files that use <linux/mod_devicetable.h>,
for a reduction of around 3900 times that <linux/mod_devicetable.h>
does not have to be read & parsed.

    225 #include <linux/mod_devicetable.h>

This patch was build-tested on 20 different arch-es.

It also makes these drivers SubmitChecklist#1 compliant.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kbuild test robot <lkp@intel.com> # drivers/media/platform/vimc/
Reported-by: kbuild test robot <lkp@intel.com> # drivers/pinctrl/pinctrl-u300.c
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-07 17:52:26 +02:00
Katsuhiro Suzuki e8349221a0 pinctrl: uniphier: add LD20 MPEG2-TS I/O pin-mux settings
The MPEG2-TS input/output core both accepts serial TS and parallel TS.

The serial TS interface uses following pins:
  hscin0_s : HS0DOUT[0-3]
  hscin1_s : HS0DOUT[4-7]
  hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0
  hscin3_s : HS1DIN[2-5]
  hscout0_s: HS0DOUT[0-3]
  hscout1_s: HS0DOUT[4-7]

And the parallel TS interface uses following pins:
  hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7]
  hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7]
  hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7]

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-02 14:36:31 +02:00
Kunihiko Hayashi 4fc97ef94b pinctrl: uniphier: add UART hardware flow control pin-mux settings
UniPhier SoCs have the following pins for hardware flow control of UART:
  XRTS, XCTS
and for modem control of UART:
  XDTR, XDSR, XDCD, XRI

The port number with the flow control is SoC-dependent.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-27 15:14:43 +02:00
Katsuhiro Suzuki a5af5c9f87 pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group
This patch divides large pin-mux group 'aio' of UniPhier LD11/LD20
to 2 groups as following:
  aout1   : 8ch I2S output: AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2]
  aoutiec1: S/PDIF output : AO1IEC, AO1ARC

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-27 13:36:15 +02:00
Masahiro Yamada 0cc449f675 pinctrl: uniphier: remove eMMC hardware reset pin-mux
This is handled by the mmc-pwrseq-emmc driver, which controls
an eMMC hardware reset via a GPIO line.

Remove it from the function pin-mux settings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31 10:14:55 +01:00
Katsuhiro Suzuki abcac84fef pinctrl: uniphier: add Audio out pin-mux settings
The UniPhier LD11/20 SoC audio core use following 8 pins:
  AO1IEC, AO1ARC, AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2]

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22 14:35:03 +02:00
Masahiro Yamada 9697509e3f pinctrl: uniphier: add suspend / resume support
Save registers lost in the sleep when suspending, and restore them
when resuming.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14 15:01:00 +02:00
Masahiro Yamada 4e7679834b pinctrl: uniphier: omit redundant input enable bit information
For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit
number matches its pin number.  So, this is redundant information.
Instead, we just need a flag to know if the iectrl gating exists or not.

With this refactoring, 5 bits in pin data will be saved.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14 15:01:00 +02:00
Masahiro Yamada 7f6ee0a579 pinctrl: uniphier: clean up GPIO port muxing
There are a bunch of GPIO muxing data, but most of them are actually
unneeded because GPIO-to-pin mapping can be specified by "gpio-ranges"
DT properties.

Tables that contain a set of GPIO pins are still needed for the named
mapping by "gpio-ranges-group-names".  This is a much cleaner way for
UniPhier SoC family where GPIO numbers are not straight mapped to pin
numbers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14 15:01:00 +02:00
Masahiro Yamada 1bd303dc04 pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD20
The pingroups dump of debugfs hits WARN_ON() in pinctrl_groups_show().
Filling non-existing ports with '-1' turned out a bad idea.

Fixes: 336306ee1f ("pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-20 11:34:52 +02:00
Masahiro Yamada 2afd450d78 pinctrl: uniphier: make drivers non-modular
At first these drivers were written as tristate, but the module
usecases are actually not tested.  Make all of them boolean.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-03-23 10:09:51 +01:00
Masahiro Yamada df1539c25c pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20
Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins.

Fixes: 1e359ab128 ("pinctrl: uniphier: add Ethernet pin-mux settings")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-19 10:36:40 +01:00
Masahiro Yamada 1e359ab128 pinctrl: uniphier: add Ethernet pin-mux settings
Add the following Ethernet interfaces:

  PH1-LD4: MII, RMII
  PH1-Pro4: MII, RMII, RGMII
  PH1-sLD8: MII, RMII (Built-in PHY is also supported)
  ProXstream2: MII, RMII, RGMII
  PH1-LD6b: RMII, RGMII
  PH1-LD11: RMII (Built-in PHY is also supported)
  PH1-LD20: RMII, RGMII

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-11 09:53:25 +02:00
Masahiro Yamada 9467f5688b pinctrl: uniphier: fix NAND pin-mux settings for PH1-LD11/LD20
My mistake in the initial support patches.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-08 11:13:11 +02:00
Masahiro Yamada 336306ee1f pinctrl: uniphier: add UniPhier PH1-LD20 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-31 12:57:45 +02:00