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5 Commits (9d8f0bcca6ffa024a822ce4ab1008ab663f06672)

Author SHA1 Message Date
Laurent Pinchart 11df28ab76 gpio-rcar: Add RCAR_GP_PIN macro
Pins are numbered in the R-Car family documentation using a bank number
and a pin number in the bank. As the Linux pin number space is linear,
we need to flatten this by multiplying the bank number by 32 and adding
the pin number. The resulting number bear no directly visible
relationship  to the documentation, making it error-prone.

Add a RCAR_GP_PIN macro to convert from the documentation pin number
space to the linear Linux space.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas@verge.net.au: non-trivial rebase on top of
 "sh-pfc: r8a7779: Don't group USB OVC and PENC pins"]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-04 21:03:56 +09:00
Simon Horman 7e1092b5a2 gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
As hardware support for this feature is not universal for all SoCs a flag,
has_both_edge_trigger, has been added to the platform data of the driver to
allow this feature to be enabled.

The motivation for this is to allow use of the gpio-keys driver on the
lager board which is based on the r8a7790 SoC. The V2 of this patch has been
fully exercised using that driver on that board.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-04 20:28:36 +09:00
Laurent Pinchart 36cb0066ff gpio-rcar: Make the platform data gpio_base field signed
The gpio_base field is used to specify the desired GPIO base for the
GPIO controller. The GPIO core can automatically allocate a GPIO number
range when the base is set to -1. To make this possible, make the field
signed.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-04 20:28:36 +09:00
Laurent Pinchart dc3465a943 gpio-rcar: Add pinctrl support
Register the GPIO pin range, and request and free GPIO pins using the
pinctrl API.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03 10:30:34 +09:00
Magnus Damm 119f5e448d gpio: Renesas R-Car GPIO driver V3
This patch is V3 of a GPIO driver for the R-Car series of
SoCs from Renesas. This driver is designed to be reusable
between multiple SoCs that share the same basic building block,
but so far it has only been used on R-Car H1 (r8a7779).

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on a single I/O memory
range and the 32 GPIOs are hooked up a single interrupt.

In the case of R-Car H1 either external IRQ pins or GPIOs
with interrupts can be used for on-board interupts. For
external IRQs 4 pins are supported, and in the case of GPIO
there are 202 GPIOS as 202 interrupts hooked up via 6 driver
instances and to the GIC and the Cortex-A9 Quad.

At this point this driver is interfacing as a regular
platform device driver. In the future DT support will be
submitted as an incremental feature patch.

Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-04-03 10:30:24 +09:00