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8 Commits (b138c331cbb1990857f2168fe6d981db1c41fa32)

Author SHA1 Message Date
Xiaowei Bao 89b832cd81 PCI: mobiveil: Add workaround for unsupported request error
Errata: unsupported request error on inbound posted write
transaction, PCIe controller reports advisory error instead
of uncorrectable error message to RC.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2019-11-25 16:29:25 +08:00
Xiaowei Bao e01168ca8b PCI: mobiveil: Add the EP driver support
Add the EP driver support for Mobiveil base on endpoint framework.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
[Zhiqiang: Correct the Copyright]
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2019-11-25 16:29:24 +08:00
Hou Zhiqiang 7e3a04890a PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
When LX2 PCIe controller is sending multiple split completions and
ACK latency expires indicating that ACK should be send at priority.
But because of large number of split completions and FC update DLLP,
the controller does not give priority to ACK transmission. This
results into ACK latency timer timeout error at the link partner and
the pending TLPs are replayed by the link partner again.

Workaround:
1. Reduce the ACK latency timeout value to a very small value.
2. Restrict the number of completions from the LX2 PCIe controller
   to 1, by changing the Max Read Request Size (MRRS) of link partner
   to the same value as Max Packet size (MPS).

This patch implemented part 1, the part 2 can be set by kernel parameter
'pci=pcie_bus_perf'

This ERRATA is only for LX2160A Rev1.0, and it will be fixed
in Rev2.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2019-11-25 16:29:23 +08:00
Hou Zhiqiang efca0d2a58 PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577
PCIe configuration access to non-existent function triggered
SERROR interrupt exception.

Workaround:
Disable error reporting on AXI bus during the Vendor ID read
transactions in enumeration.

This ERRATA is only for LX2160A Rev1.0, and it will be fixed
in Rev2.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2019-11-25 16:29:23 +08:00
Hou Zhiqiang 24e0514f88 PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape SoCs
This PCIe controller is based on the Mobiveil GPEX IP, which is
compatible with the PCI Express™ Base Specification, Revision 4.0.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
2019-11-25 16:29:22 +08:00
Hou Zhiqiang 73c5cc9d93 PCI: mobiveil: Add 8-bit and 16-bit CSR register accessors
There are some 8-bit and 16-bit registers in PCIe configuration
space, so add these accessors accordingly.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-11-25 16:29:22 +08:00
Hou Zhiqiang 9a9fe7dbd9 PCI: mobiveil: Make mobiveil_host_init() can be used to re-init host
Make the mobiveil_host_init() function can be used to re-init
host controller's PAB and GPEX CSR register block, as NXP
integrated Mobiveil IP has to reset and then re-init the PAB
and GPEX CSR registers upon hot-reset.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-11-25 16:29:21 +08:00
Hou Zhiqiang f619c54210 PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver
Refactor the Mobiveil PCIe Host Bridge IP driver to make
it easier to add support for both RC and EP mode driver.
This patch moved the Mobiveil driver to an new directory
'drivers/pci/controller/mobiveil' and refactor it according
to the RC and EP abstraction.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
2019-11-25 16:29:21 +08:00