Commit graph

11 commits

Author SHA1 Message Date
Grygorii Strashko e99c4d5762 ARM: dts: dra62x-j5eco-evm: get rid of phy_id property
The phy_id property is deprecated and phy-handle has to be used instead.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-09-20 14:42:55 -07:00
Graeme Smecher 647efef69d ARM: dts: correct missing "compatible" entry for ti81xx SoCs
The missing "compatible" entries are needed by drivers/clk/ti/clkctrl.c,
and without them the structures initialized in drivers/clk/ti/clk-814x.c
are not passed to configuration code. The result is a "not found from
clkctrl data" error message, although boot proceeds anyway.

The reason why the compatible is not found is because the board specific
files override the SoC compatible without including it. This did not
cause any issues until with the clkctrl nodes got introduced.

Very lightly tested on a (lurching) AM3874 design that's in the middle
of a kernel upgrade from TI's abandoned 2.6.37 tree.

Also tested on j5eco-evm and hp-t410 to verify the clkctrl clocks are
found.

Fixes: bb30465b59 ("ARM: dts: dm814x: add clkctrl nodes")
Fixes: 80a06c0d83 ("ARM: dts: dm816x: add clkctrl nodes")
Signed-off-by: Graeme Smecher <gsmecher@threespeedlogic.com>
[tony: updated to fix for 8168-evm, updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-05-03 10:07:47 -07:00
Mathieu Malaterre 9b490b3db5 ARM: dts: am3/am4/dra7/omap: Remove leading 0x and 0s from bindings notation
Improve the DTS files by removing all the leading "0x" and zeros to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have
leading "0x"

and

Warning (unit_address_format): Node /XXX unit name should not have
leading 0s

Converted using the following command:

$ find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec \
sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" \
-e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} +^C

For simplicity, two sed expressions were used to solve each warnings
separately.

To make the regex expression more robust a few other issues were resolved,
namely setting unit-address to lower case, and adding a whitespace before
the the opening curly brace:

https://elinux.org/Device_Tree_Linux#Linux_conventions

This will solve as a side effect warning:

Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format
error, expected "<lower>"

This is a follow up to commit 4c9847b737 ("dt-bindings: Remove leading
0x from bindings notation")

Reported-by: David Daney <ddaney@caviumnetworks.com>
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-12-15 08:36:06 -08:00
Javier Martinez Canillas 387117c127 ARM: dts: dra62x: Add missing unit name to memory nodes
This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-08-31 07:40:27 -07:00
Javier Martinez Canillas 909b0ebde9 ARM: dts: omap3/dra62x: remove unneeded unit name for fixed regulators
This patch fixes the following DTC warnings for many boards:

"Node /fixedregulator@0 has a unit name, but no reg property"

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-08-15 09:42:39 -07:00
Roger Quadros 44a3ab68ca ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].

[1] dm814x TRM: SPRUGZ8F: 11.2.4.12.2 NAND Device-Ready Pin

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-03-01 09:58:09 -08:00
Roger Quadros 0c3e192ad2 ARM: dts: dm814x: dra62x: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-03-01 09:58:09 -08:00
Tony Lindgren 100be58aa8 ARM: dts: Add NAND support for j5-eco evm
Add NAND support for j5-eco evm.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-02-12 13:25:14 -08:00
Tony Lindgren 43fe6de38e ARM: dts: Add usb support for j5-eco evm
Add usb support for j5-eco evm.

Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-12-22 16:01:41 -08:00
Tony Lindgren 4d810fb219 ARM: dts: Add mmc support for dra62x j5-eco evm
There's mmc interface on j5-eco evm that's wired to the
sd_1 interface.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-12-22 16:00:57 -08:00
Tony Lindgren 124bfc66c5 ARM: dts: Add minimal dra62x j5-eco evm support
This allows us to boot dra62x j5-eco evm with NFSroot.

Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-12-22 16:00:28 -08:00