Commit graph

6 commits

Author SHA1 Message Date
Stephen Boyd 7279db9287 ARM: qcom: Fix SCM interface for big-endian kernels
The secure environment only runs in little-endian mode, so any
buffers shared with the secure environment should have their
contents converted to little-endian. We also mark such elements
with __le32 to allow sparse to catch such problems.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-01-23 10:19:33 -06:00
Olav Haugan 4139447035 ARM: qcom: scm: Add logging of actual return code from scm call
When an error occurs during an scm call the error returned is remapped so
we lose the original error code. This means that when an error occurs we
have no idea what actually failed within the secure environment.

Add a logging statement that will log the actual error code from scm call
allowing us to easily determine what caused the error to occur.

Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-01-19 11:53:32 -06:00
Vikram Mulukutla 404b5a97f5 ARM: qcom: scm: Flush the command buffer only instead of the entire cache
scm_call flushes the entire cache before calling into the secure world.
This is both a performance penalty as well as insufficient on SMP systems
where the CPUs possess a write-back L1 cache. Flush only the command and
response buffers instead, moving the responsibility of flushing any other
cached buffer (being passed to the secure world) to callers.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-01-19 11:53:32 -06:00
Stephen Boyd 30cbb0c01b ARM: qcom: scm: Get cacheline size from CTR
Instead of hardcoding the cacheline size as 32, get the cacheline size from
the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-01-19 11:53:31 -06:00
Stephen Boyd f76c691657 ARM: qcom: scm: Fix incorrect cache invalidation
The cache invalidation in scm_call() correctly rounds down the start
address to invalidate the beginning of the cacheline but doesn't properly
round up the 'end' address to make it aligned.  The last chunk of the
buffer won't be invalidated when 'end' is not cacheline size aligned so
make sure to invalidate the last few bytes in such situations. It also
doesn't do anything about outer caches so make sure to invalidate and flush
those as well.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-01-19 11:53:31 -06:00
Kumar Gala 8fc1b0f87d ARM: qcom: Split Qualcomm support into legacy and multiplatform
Introduce a new mach-qcom that will support SoCs that intend to be
multiplatform compatible while keeping mach-msm to legacy SoC/board
support that will not transition over to multiplatform.

As part of this, we move support for MSM8X60, MSM8960 and MSM8974 over
to mach-qcom.

Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-02-06 16:20:26 -06:00
Renamed from arch/arm/mach-msm/scm.c (Browse further)