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3043 commits

Author SHA1 Message Date
Martin Sperl 96bf9c69d5 clk: bcm2835: expose raw clock-registers via debugfs
For debugging purposes under some circumstance
it helps to be able to see the actual clock registers.

E.g: when looking at the clock divider it is helpful to
see what the actual clock divider is.

This patch exposes all the clock registers specific to each
clock/pll/pll-divider via debugfs.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl 6e1e60dace clk: bcm2835: clean up coding style issues
Fix all the checkpatch complaints for clk-bcm2835.c

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl 959ca92a32 clk: bcm2835: correctly enable fractional clock support
The current driver calculates the clock divider with
fractional support enabled.

But it does not enable fractional support in the
control register itself resulting in an integer only divider,
but in clk_set_rate responds back the fractionally divided
clock frequency.

This patch enables fractional support in the control register
whenever there is a fractional bit set in the requested clock divider.

Mash clock limits are are also handled for the PWM clock
applying the correct divider limits (2 and max_int) applicable to
basic fractional divider support (mash order of 1).

It also adds locking to protect the read/modify/write cycle of
the register modification.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl 997f16bd5d clk: bcm2835: divider value has to be 1 or more
Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl ec36a5c668 clk: bcm2835: add locking to pll*_on/off methods
Add missing locking to:
* bcm2835_pll_divider_on
* bcm2835_pll_divider_off
to protect the read modify write cycle for the
register access protecting both cm_reg and a2w_reg
registers.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Martin Sperl 6727f086cf clk: bcm2835: pll_off should only update CM_PLL_ANARST
bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-17 10:42:17 -07:00
Heiko Stuebner 2c6fae2501 clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036
The emac needs constant and very specific rate but the possible PLL-sources
are very limited, so we expect the PLL source to be set manually on per
board and don't want it to get changed in an automatic way later.
So add the necessary clock-id and disable reparenting on set_rate calls.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16 19:28:02 -04:00
Xing Zheng e764b93924 clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
Associate the new clock id the clock.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16 19:28:01 -04:00
Vladimir Zapolskiy 4d3ac66624 clk: bcm2835: fix check of error code returned by devm_ioremap_resource()
The change fixes potential oops while accessing iomem on invalid
address, if devm_ioremap_resource() fails due to some reason.

The devm_ioremap_resource() function returns ERR_PTR() and never
returns NULL, which makes useless a following check for NULL.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Fixes: 5e63dcc74b ("clk: bcm2835: Add a driver for the auxiliary peripheral clock gates")
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:14:11 -07:00
Simon Horman e8087b5b90 clk: renesas: div6: use RENESAS for #define
Name the #define guarding compilation of this header
__RENESAS_CLK_DIV6_H__ rather than __SHMOBILE_CLK_DIV6_H__.

This is a follow-up to renaming the directory in which this file lives from
shmobile to renesas which is in turn part of an ongoing process to migrate
from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that
RENESAS seems to be a more appropriate name than SHMOBILE for the majority
of Renesas ARM based SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:13:02 -07:00
Simon Horman 09c32427c9 clk: renesas: Rename header file renesas.h
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.

Along with the above mentioned Kconfig changes it seems appropriate
to also rename files.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 18:12:14 -07:00
Stephen Boyd 4c9462b434 clk: max77{686,802}: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 15:19:49 -07:00
Stephen Boyd ac82a8b507 clk: versatile: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Pawel Moll <pawel.moll@arm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 15:19:21 -07:00
Stephen Boyd 1295e36a48 clk: sunxi: Remove use of variable length array
Using an array allocated on the stack may lead to stack overflows
and other problems so let's move the allocation to the heap
instead. This silences the following checker warning as well.

drivers/clk/sunxi/clk-sun8i-mbus.c:36:29: warning: Variable length array is used

Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-15 15:15:27 -07:00
Stephen Boyd d3781a74bc clk: fixed-rate: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04 14:31:17 -08:00
Stephen Boyd 81925c5eaa clk: qcom: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04 12:53:53 -08:00
Joachim Eastwood 378523d150 clk: add lpc18xx creg clk driver
The CREG block on lpc18xx contains configuration register
for two low power clocks. Support enabling of these two
clocks with a clk driver that access CREG trough the
syscon regmap interface.

These clocks are needed to support peripherals like the
internal RTC on lpc18xx.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-04 12:52:10 -08:00
Stephen Boyd 37655fae0c Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
 and some more clock-ids.
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Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull second batch of rockchip clk updates from Heiko Stuebner:

Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.

* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: include downstream muxes into fractional dividers on rk3368
  clk: rockchip: set the clock ids for RK3228 HDMI
  clk: rockchip: set the clock ids for RK3228 VOP
  clk: rockchip: add the tsadc clocks found on rk3228 SoCs
  clk: rockchip: add the new clock ids for RK3228 HDMI
  clk: rockchip: add the new clock ids for RK3228 VOP
  clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
  clk: rockchip: fix coding style for clk-cpu.c
  clk: rockchip: don't return NULL when registering mmc branch fails
  clk: rockchip: don't return NULL when registering inverter fails
  clk: rockchip: check grf when waiting pll lock
  clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
2016-03-04 09:36:29 -08:00
Sylvain Lemieux 8626556f25 clk: lpc32xx: fix compilation warning
Remove the following false positives compilation warning:
- drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register':
  warning: 'hw' may be used uninitialized in this function [-Wmaybe-uninitialized]
- drivers/clk/nxp/clk-lpc32xx.c: In function 'clk_hclk_pll_round_rate':
  warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'n' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'm' may be used uninitialized in this function [-Wmaybe-uninitialized]

Tested using gcc version 4.7.3.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
[sboyd@codeaurora.org: Drop assignment of hw to NULL as return
silences it and is less likely to lead to hiding problems later]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:41:43 -08:00
Loc Ho 0f4c7a138d clk: xgene: Add missing parenthesis when clearing divider value
In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Toan Le <toanle@apm.com>
Fixes: 1382ea631d ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:37:15 -08:00
Stephen Boyd 0d9967fe4b clk: mb86s7x: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:27:48 -08:00
Stephen Boyd 4106684e11 clk: x86: Remove clkdev.h and clk.h includes
This driver is a clk provider and not a clk consumer, so remove
the clk.h include. Also, drop clkdev.h because there's not clkdev
usage here either.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:27:26 -08:00
Stephen Boyd 553b485817 clk: x86: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:27:18 -08:00
Stephen Boyd 2969f6ee37 clk: mvebu: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:26:42 -08:00
Simon Horman b3a33077c0 clk: renesas: move drivers to renesas directory
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.

Along with the above mentioned Kconfig changes it seems appropriate
to also rename directories that only hold drivers for such SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03 11:22:53 -08:00
Stephen Boyd 27fbd266de Merge branch 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull shmobile clk updates from Geert Uytterhoeven:

   - Fix a bug in the div6 clock driver that was exposed by CAN
     support on R-Car H3,
   - Add more module clocks for R-Car H3.

* 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: shmobile: r8a7795: Add CAN FD peripheral clock
  clk: shmobile: r8a7795: Add CANFD clock
  clk: shmobile: r8a7795: Add CAN peripheral clock
  clk: shmobile: div6: Fix .recalc_rate() using a stale divisor
  clk: shmobile: r8a7795: Add LVDS module clock
  clk: shmobile: r8a7795: Add FCP clocks
2016-03-03 11:21:40 -08:00
Stephen Boyd 803c43311f clk: si5{14,351,70}: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:51:13 -08:00
Stephen Boyd 905936823e clk: scpi: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:50:58 -08:00
Stephen Boyd 8620925231 clk: s2mps11: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Andi Shyti <andi.shyti@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:50:32 -08:00
Stephen Boyd 1edfc1e700 clk: pwm: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:50:08 -08:00
Stephen Boyd 124603990d clk: efm32gg: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:48:47 -08:00
Stephen Boyd 0b4d613a71 clk: zynq: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:48:26 -08:00
Stephen Boyd 66f4ae777d clk: ux500: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:48:03 -08:00
Stephen Boyd 45e21151a2 clk: ti: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:47:46 -08:00
Stephen Boyd f6da46a307 clk: tegra: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:47:19 -08:00
Stephen Boyd afb4bdc9d8 clk: spear: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:46:55 -08:00
Stephen Boyd 728f288d2a clk: samsung: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:46:29 -08:00
Stephen Boyd 2c63935dd6 clk: pxa: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:46:00 -08:00
Stephen Boyd 615b34de1f clk: nxp: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:45:22 -08:00
Stephen Boyd 0f4207f3d8 clk: mxs: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:44:59 -08:00
Stephen Boyd 38c7035f9c clk: imx: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:44:26 -08:00
Stephen Boyd 3d08f1564b clk: mediatek: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:44:06 -08:00
Stephen Boyd f61990f3c5 clk: hisilicon: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Bintian Wang <bintian.wang@huawei.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:43:32 -08:00
Stephen Boyd a9bb2ef7c3 clk: at91: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:43:08 -08:00
Stephen Boyd bd41aa6773 clk: bcm: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Lee Jones <lee@kernel.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:42:41 -08:00
Stephen Boyd 5788923b27 Merge tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull i.MX clk updates from Shawn Guo:

The i.MX clock update for 4.6:
- Add the clock driver support for the latest i.MX6 family SoCs
  addition - i.MX6QP.
- Clean up the whitespace in i.MX6UL clock driver and add the missing
  KPP clock.
- Correct pwm7 clock name in i.MX6UL clock driver.

* tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: add kpp clock for i.MX6UL
  clk: imx: whitespace cleanup; no functional change
  clk: imx: correct pwm7 clock name in driver for i.MX6UL
  clk: imx: Add clock support for imx6qp
2016-03-02 14:31:47 -08:00
Stephen Boyd 06a9852747 Merge tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clk updates from Maxime Ripard:

Allwinner clocks additions for 4.6

A bunch of things, mostly:
  - Finally switched everything over to OF_CLK_DECLARE, which should remove
    orphans clocks entirely
  - Reworked the clk-factors to be able to add new parameters
  - Improved the error reporting
  - A bunch of new clocks for new SoCs.

* tag 'sunxi-clocks-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits)
  clk: sunxi: Add apb0 gates for H3
  clk: sunxi: Improve divs_clk error handling and reporting
  clk: sunxi: improve divider_clk error handling and reporting
  clk: sunxi: improve mux_clk error handling and reporting
  clk: sunxi: Fix sun8i-a23-apb0-clk divider flags
  clk: sunxi: Remove clk_register_clkdev calls
  clk: sunxi: Remove old probe and protection code
  clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
  clk: sunxi: Make clocks setup functions take const pointer
  clk: sunxi: Make clocks setup functions return their clock
  clk: sunxi: improve error reporting for the mux clock
  clk: sunxi: don't mark sun6i_ar100_data __initconst
  clk: sunxi: add bus gates for A83T
  clk: sunxi: Add apb0 gates for A83T
  clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
  clk: sunxi: rewrite sun6i-ar100 using factors clk
  clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
  clk: sunxi: factors: Drop round_rate from clk ops
  clk: sunxi: factors: Support custom formulas
  clk: sunxi: factors: Consolidate get_factors parameters into a struct
  ...
2016-03-02 14:31:42 -08:00
Stephen Boyd 0f75e1a370 clk: qcom: msm8960: Fix ce3_src register offset
The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 5f775498bd ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 14:31:31 -08:00
Michael Turquette 3b0f4ae3e9 Merge branch 'clk-ti' into clk-next
Conflicts:
	drivers/clk/Kconfig
2016-03-01 16:23:40 -08:00
Stephen Boyd 8a8b6eb7a8 clk: ti: Fix some errors found by static checkers
drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static?
drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static?
drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type?
drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921)

The last one looks like a real bug because we don't return an
error on allocation failure.

Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-01 16:21:25 -08:00
Tony Lindgren c2ee9bdc85 clk: ti: Allow COMPILE_TEST to build selected drivers
The arch independent drivers can be build testeed with
COMPILE_TEST. Let's allow that for drivers/clk/ti.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-03-01 16:21:25 -08:00
Tony Lindgren 21330497f3 clk: ti: Add support for dm814x ADPLL
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.

Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.

Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-03-01 16:21:25 -08:00
Archit Taneja 811a498e5e clk: qcom: Fix pre-divider usage for pixel RCG
The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
its current value from the NS register.

Using the pre-divider wasn't really intended when creating these ops.
The pixel RCG was only intended to achieve fractional multiplication
provided in the pixel_table array. Leaving the pre-divider to the
existing register value results in a wrong pixel clock when the
bootloader sets up the display. This was left unidentified because
the IFC6410 Plus board on which this was verified didn't have a
bootloader that configured the display.

Don't set the RCG pre-divider in freq_tbl to the existing NS register
value. Force it to 1 and only use the M/N counter to achieve the desired
fractional multiplication.

Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-29 12:57:06 -08:00
Lothar Waßmann f6c3aec2f7 clk: imx: add kpp clock for i.MX6UL
Add the necessary clock to use the KPP interface on i.MX6UL.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-28 10:45:29 +08:00
Lothar Waßmann 9797d81936 clk: imx: whitespace cleanup; no functional change
remove whitespace before TAB.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-28 10:45:13 +08:00
Stephen Boyd d3622b5885 clk: h8300: Properly cast to __iomem pointer
Sparse complains here because we dropped the __iomem annotation
when casting the aligned address. Add __iomem back so that sparse
stops complaining.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd 921bacfa34 clk: ti: Update for of_clk_get_parent_count() returning unsigned int
Change the types here to unsigned int instead of int and update
the checks for == 0 instead < 1 to be more explicit about what's
going on now that of_clk_get_parent_count() has changed return
types.

Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd 36bf281141 clk: sunxi: Use proper type for of_clk_get_parent_count() return value
The return type of of_clk_get_parent_count() is an unsigned int
now, so let's update the code here to be more explicit about the
range of values we can test for.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd caeb057cd3 clk: st: Remove impossible check for of_clk_get_parent_count() < 0
The checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.

Cc: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd ebf3f9a923 clk: h8300: Remove impossible check for of_clk_get_parent_count()
The checks for < 1 can be simplified now that
of_clk_get_parent_count() returns an unsigned int. Update the
code to reflect the int to unsigned int change.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd 0985df8953 clk: gpio: Remove impossible check for of_clk_get_parent_count() < 0
The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the type here.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd 8c1b1e54fa clk: at91: Remove impossible checks for of_clk_get_parent_count()
These checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Change the
checks for == 0 and update the type.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Stephen Boyd 929e7f3bc7 clk: Make of_clk_get_parent_count() return unsigned ints
Russell King recently pointed out a bug in the clk-gpio code
where it fails to register the clk if of_clk_get_parent_count()
returns an error because the "clocks" property isn't present in
the DT node. If we're trying to count parents from DT we'd like
to know the count, not if there is a "clocks" property or not.
Furthermore, some drivers are assigning the return value to their
clk_init_data::num_parents member which is unsigned, leading to
potentially large numbers of parents when the property isn't
present.

Let's change the API to return an unsigned int instead of an int.
All the callers just want to know the count anyway, and this
avoids the bug that was in the clk-gpio driver.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 16:01:32 -08:00
Geert Uytterhoeven 3e5dd6f6e6 clk: Ignore disabled DT clock providers
of_clk_init() uses for_each_matching_node_and_match() to find clock
providers, which returns all matching device nodes, whether they are
enabled or not. Hence clock providers that are disabled explicitly in DT
using e.g.

	"status = "disabled";

are still activated.

Add a check to ignore device nodes that are not enabled, like
of_irq_init() does.

Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-26 09:39:38 -08:00
Ramesh Shanmugasundaram a080c8c346 clk: shmobile: r8a7795: Add CAN FD peripheral clock
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:04:30 +01:00
Ramesh Shanmugasundaram 7e00d63199 clk: shmobile: r8a7795: Add CANFD clock
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:04:30 +01:00
Ramesh Shanmugasundaram 11c6fb7832 clk: shmobile: r8a7795: Add CAN peripheral clock
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:04:29 +01:00
Geert Uytterhoeven 3092d3b8e5 clk: shmobile: div6: Fix .recalc_rate() using a stale divisor
cpg_div6_clock_set_rate() only programs the new divisor if the clock
isn't stopped. If the clock is stopped, it will update the cached
divisor value only, which will be programmed into the clock registers
when enabling the clock later.

However, cpg_div6_clock_recalc_rate() reads the divisor from the clock
registers instead of using the cached value, leading to an incorrect
result if the clock is currently stopped.

Make cpg_div6_clock_recalc_rate() use the cached value to fix this.

Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
2016-02-26 12:03:10 +01:00
Laurent Pinchart 31aeb5a523 clk: shmobile: r8a7795: Add LVDS module clock
The parent clock hasn't been validated yet.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:01:42 +01:00
Laurent Pinchart c5f80c5f6e clk: shmobile: r8a7795: Add FCP clocks
The parent clock isn't documented in the datasheet, use S2D1 as a best
guess for now.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 12:00:49 +01:00
Shawn Lin 023bd7166b clk: skip unnecessary set_phase if nothing to do
Let's compare the degrees from clk_set_rate with
clk->core->phase. If the requested degrees is already
there, skip the following steps.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[sboyd@codeaurora.org: s/drgrees/degrees/ in commit text]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 18:10:51 -08:00
Elaine Zhang 7af8a26ce7 clk: rockchip: include downstream muxes into fractional dividers on rk3368
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3368 clocks were left out, so convert them now.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:08:45 +01:00
Yakir Yang bdc7deec2f clk: rockchip: set the clock ids for RK3228 HDMI
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:08:04 +01:00
Yakir Yang 0a9d4ac08e clk: rockchip: set the clock ids for RK3228 VOP
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:07:15 +01:00
Caesar Wang a3cb9aa4ba clk: rockchip: add the tsadc clocks found on rk3228 SoCs
This patch adds the needed clocks for rk3228 tsadc.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26 02:05:12 +01:00
Martin Sperl 2103a21561 clk: bcm2835: added missing clock register definitions
Added missing CTRL and DIV clock register definitions for:
PCM, SLIM, TCNT, TEC, TD0, TD1

Register information taken from:
https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
which extracted the information from the header files shared by
Broadcom/rpi foundation in this file:
http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 16:07:59 -08:00
Simon Horman 57130e6434 clk: shmobile: Remove ARCH_SHMOBILE_MULTI
As of 9b5ba0df4e ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms
that use Renesas clock drivers now select ARCH_RENESAS. As it is present in
drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed.

This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 15:44:09 -08:00
Stephen Boyd 7450ca6c32 Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
 from the suspend/resume register save/restore list
 and exposition of two clocks required for the
 exynos5433 HDMI subsystem operation.
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Merge tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung into clk-next

Pull Samsung clk driver changes from Sylwester Nawrocki:

Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.

* tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung:
  clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
  clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
  clk: samsung: exynos5433: Drop RO registers from the save/restore lists
  clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
  clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
  clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
  clk/samsung: exynos5433: add pclk_decon clock
  clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
2016-02-25 15:18:12 -08:00
Kevin Smith 1594d568c6 clk: mvebu: Move corediv config to mvebu config
The core clock does not depend on corediv, so enabling corediv
based on the clock is not really correct.  Move the corediv
config option from the clock driver Kconfig to the mvebu Kconfig
so that it can be enabled by the MACH option instead.

This also enables corediv on Armada 375 and 38X, which was
previously missing.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 15:05:53 -08:00
Kevin Smith bd3677ff31 clk: mvebu: Remove corediv clock from Armada XP
There is no corediv clock on Armada XP, so this is unnecessary.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 15:05:47 -08:00
Linus Walleij ec7957a6aa clk: versatile: sp810: support reentrance
Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.

Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.

This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
  clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<c00167f8>] (unwind_backtrace) from [<c0013204>]
             (show_stack+0x10/0x14)
[<c0013204>] (show_stack) from [<c01a049c>]
             (dump_stack+0x84/0x9c)
[<c01a049c>] (dump_stack) from [<c0024990>]
             (warn_slowpath_common+0x74/0xb0)
[<c0024990>] (warn_slowpath_common) from [<c0024a68>]
             (warn_slowpath_null+0x1c/0x24)
[<c0024a68>] (warn_slowpath_null) from [<c051eb44>]
             (clk_sp810_of_setup+0x110/0x154)
[<c051eb44>] (clk_sp810_of_setup) from [<c051e3a4>]
             (of_clk_init+0x12c/0x1c8)
[<c051e3a4>] (of_clk_init) from [<c0504714>]
             (time_init+0x20/0x2c)
[<c0504714>] (time_init) from [<c0501b18>]
             (start_kernel+0x244/0x3c4)
[<c0501b18>] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Fixes: 6e973d2c43 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 15:03:28 -08:00
Stephen Boyd 2da5f5db39 clk: Get rid of HAVE_MACH_CLKDEV
This config was used for the ARM port so that it could use a
machine specific clkdev.h include, but those are all gone now.
The MIPS architecture is the last user, and from what I can tell
it doesn't actually use it anyway, so let's remove the config all
together.

Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Joshua Henderson <joshua.henderson@microchip.com>
2016-02-25 14:41:20 -08:00
Stephen Boyd 0af1a24f5b Merge branch 'clk-ipq4019' into clk-next
* clk-ipq4019:
  clk: qcom: Add IPQ4019 Global Clock Controller support
2016-02-25 14:32:27 -08:00
Varadarajan Narayanan 6971e86399 clk: qcom: Add IPQ4019 Global Clock Controller support
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 14:32:12 -08:00
Stephen Boyd 73f3f13825 clk: shmobile: Free 'clock' on error path
We forgot to free this clock when we return early in this code.

Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25 12:25:31 -08:00
Krzysztof Adamski 6e17b41816 clk: sunxi: Add apb0 gates for H3
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).

Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
         the commit log a bit]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-25 11:30:32 -08:00
Jonghwa Lee a6cb74cbc9 clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2}
clocks definition.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-25 12:10:00 +01:00
Sylwester Nawrocki 3795e0f6e4 clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
Control bits for the ACLK_CAM1_552_USER and ACLK_CAM1_400_USER
mux clocks are in MUX_SEL_CAM10, not MUX_SEL_CAM01 register.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-25 12:09:59 +01:00
Sylwester Nawrocki f0abd93125 clk: samsung: exynos5433: Drop RO registers from the save/restore lists
Restoring read-only registers is of not much effect, drop them
from the respective lists.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-25 12:09:58 +01:00
Marek Szyprowski f190a87e27 clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
This fixes bit field offsets in the CMU_TOP CLK_DIV_SCLK_ISP_SENSOR_{A,B}
clock definitions.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-25 12:09:57 +01:00
Sylwester Nawrocki a665d30f1f clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
This corrects assignment of bit offsets of the MUX_SEL_CAM04 register
to the respective mux clocks.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-25 12:09:42 +01:00
Sudip Mukherjee c7f23180c6 clk: shmobile: check for failure
We were not checking the return from devm_add_action() which can fail.
Start using the helper devm_add_action_or_reset() and return directly
as we know that the cleanup has been done by this helper.

Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-24 15:01:42 -08:00
Sylwester Nawrocki 3c30e382ae clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
This fixes "MPWM" -> "WPWM" typo in 3 *ISP_MWPM clock definitions.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-23 12:48:11 +01:00
Stephen Boyd 706d5c73e3 clk: Update some outdated comments
__clk_init() was renamed to __clk_core_init() but these comments
weren't updated.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22 15:43:41 -08:00
Stephen Boyd fa459711a0 Revert "clk: avoid circular clock topology"
This reverts commit 858d588156.

Joachim reports that this commit breaks lpc18xx boot. This is
because the hardware has circular clk topology where PLLs can
feed into dividers and the same dividers can feed into the PLLs.
The hardware is designed this way so that you can choose to put
the divider before the PLL or after the PLL depending on what you
configure to be the parent of the divider and what you configure
to be the parent of the PLL.

So let's drop this patch for now because we have hardware that
actually has loops. A future patch could check for circular
parents when we change parents and fail the switch, but that's
probably best left to some debugging Kconfig option so that we
don't suffer the sanity checking cost all the time.

Reported-by: Joachim Eastwood <manabian@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22 15:01:39 -08:00
Dinh Nguyen 56713da3ee clk: socfpga: allow for multiple parents on Arria10 periph clocks
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22 14:17:37 -08:00
Tero Kristo b6f5128459 clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrs
Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22 14:16:49 -08:00
Stephen Boyd 1e59403990 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
2016-02-22 14:16:24 -08:00
Srinivas Kandagatla 732d691369 clk: qcom: msm8960: fix ce3_core clk enable register
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bd ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22 14:15:53 -08:00
Tero Kristo a0d54c3899 clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
As the code in this file is being executed within irq context in some
cases, we must avoid the clk_get_rate which uses mutex internally.
Switch the code to use clk_hw_get_rate instead which is non-locking.

This fixes an issue where PM runtime will hang the system if enabled
with a serial console before a suspend-resume cycle.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Fixes: a53ad8ef3d ("clk: ti: Convert to clk_hw based provider APIs")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-22 14:03:02 -08:00
Michael Turquette f073cd8a3e Merge branch 'clk-samsung' into clk-next 2016-02-22 10:24:40 -08:00
Krzysztof Kozlowski 85997a7cba clk: samsung: Don't build ARMv8 clock drivers on ARMv7
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
so it is built also on ARMv7. This does not bring any kind of benefit.
There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like
multi_v7 for ARMv7).

Instead build clock drivers only for respective SoC's architecture.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-22 10:20:24 -08:00
Andre Przywara d331328da6 clk: sunxi: Improve divs_clk error handling and reporting
We catch errors in the base clock registration, failure to ioremap
and failures in the final of_clk_add_provider() call.
Also we unmap the registers when we need to rollback.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-21 19:44:49 -08:00
Andre Przywara b26803ebfb clk: sunxi: improve divider_clk error handling and reporting
We now report a failing ioremap, failing output names parsing,
failures in table registration and in the final step.
Also there was a bug where clk_register_divider_table() would return
an ERR_PTR value instead of NULL, which we were checking for.
We now implement proper rollback in case of an error.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-21 19:44:38 -08:00
Andre Przywara 72360b9116 clk: sunxi: improve mux_clk error handling and reporting
We now catch and report a failing ioremap, also a failure in the final
step of the clock registration is now handled and reported.
Also warnings are turned into errors.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-21 19:44:09 -08:00
Michael Turquette e1f520dc70 Merge branch 'clk-shmobile-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next 2016-02-19 12:46:09 -08:00
Stephen Boyd 6a05d862c3 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: gpio: Really allow an optional clock= DT property
  Revert "clk: qcom: Specify LE device endianness"
2016-02-18 19:17:29 -08:00
Stephen Boyd 4462b4bbfc clk: gpio: Really allow an optional clock= DT property
We mis-merged the original patch from Russell here and so the
patch went almost all the way, except that we still failed to
probe when there wasn't a clocks property in the DT node. Allow
that case by making a negative value from
of_clk_get_parent_count() into "no parents", like the original
patch did.

Fixes: 7ed88aa2ef ("clk: fix clk-gpio.c with optional clock= DT property")
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-18 19:10:22 -08:00
Anatolij Gustschin 81a467efe3 clk: imx: correct pwm7 clock name in driver for i.MX6UL
Don't capitalize p in the pwm7 clock name.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-18 22:25:19 +08:00
Magnus Damm f099aa0757 clk: shmobile: r8a7795: Add INTC-EX clock
Add the "intc-ex" clock to the r8a7795 CPG MSSR driver.

According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18 09:01:46 +01:00
Andrew F. Davis fb4dd22203 clk: Make of_clk_get_from_provider() available to modules
Export symbol of_clk_get_from_provider so it can be used in
loadable kernel modules

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-17 16:50:13 -08:00
Alexandre Belloni 0002ca168f clk: at91: remove useless includes
Over time, some includes were copy pasted from other clocks drivers but are
not necessary.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17 17:53:04 +01:00
Alexandre Belloni 60cad091a5 clk: at91: pmc: remove useless capacities handling
Capacities only handles interrupts and they are not use anymore. Remove the
whole initialisation.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17 17:53:04 +01:00
Alexandre Belloni af719c1807 clk: at91: pmc: drop at91_pmc_base
at91_pmc_base is not used anymore, remove it along with at91_pmc_read and
at91_pmc_write.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17 17:53:03 +01:00
Alexandre Belloni fbc7edca5a ARM: at91: pm: move idle functions to pm.c
Avoid using code from clk/at91 for PM.
This also has the bonus effect of setting arm_pm_idle for sama5 platforms.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2016-02-17 17:53:02 +01:00
Alexandre Belloni ea52bc6467 clk: at91: pmc: move pmc structures to C file
pmc.c is now the only user of struct at91_pmc*, move their definition in
the C file.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17 17:53:00 +01:00
Alexandre Belloni a5df602bd3 clk: at91: pmc: merge at91_pmc_init in atmel_pmc_probe
at91_pmc_init() doesn't do much anymore, merge it in atmel_pmc_probe().

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17 17:53:00 +01:00
Alexandre Belloni 99a8170652 clk: at91: remove IRQ handling and use polling
The AT91 clock drivers make use of IRQs to avoid polling when waiting for
some clocks to be enabled. Unfortunately, this leads to a crash when those
IRQs are threaded (which happens when using preempt-rt) because they are
registered before thread creation is possible.

Use polling on those clocks instead to avoid the problem.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17 17:52:59 +01:00
Boris Brezillon 1bdf02326b clk: at91: make use of syscon/regmap internally
Use the regmap coming from syscon to access the registers instead of using
pmc_read/pmc_write. This allows to avoid passing the at91_pmc structure to
the child nodes of the PMC.

The final benefit is to have each clock register itself instead of having
to iterate over the children.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-02-17 17:52:58 +01:00
Boris Brezillon 863a81c3be clk: at91: make use of syscon to share PMC registers in several drivers
The PMC block is providing several functionnalities:
 - system clk management
 - cpuidle
 - platform suspend

Replace the void __iomem *regs field by a regmap (retrieved using syscon)
so that we can later share the regmap across several drivers without
exporting a new specific API or a global void __iomem * variable.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-17 17:52:58 +01:00
Krzysztof Kozlowski 215cd9674f clk: samsung: Enable COMPILE_TEST for Samsung clocks
Enable the COMPILE_TEST to get build coverage of some of Samsung clock
controller drivers. Still some of them will be built only if
appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX).

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16 17:21:41 -08:00
Michael Turquette 3aef66490d Merge branch 'clk-bcm2835' into clk-next 2016-02-16 12:31:51 -08:00
Eric Anholt 79c1e2fc2c clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()
We were rolling this ourselves, but clk-divider can do it now.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16 12:30:09 -08:00
Eric Anholt 773b3966dd clk: bcm2835: Fix setting of PLL divider clock rates
Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write.  It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.

Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).

Cc: stable@vger.kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-16 12:30:07 -08:00
Kees Cook 416dd13ad6 ARM: 8503/1: clk_register_clkdev: remove format string interface
Many callers either use NULL or const strings for the third argument of
clk_register_clkdev. For those that do not and use a non-const string,
this is a risk for format strings being accidentally processed (for
example in device names). As this interface is already used as if it
weren't a format string (prints nothing when NULL), and there are zero
users of the format strings, remove the format string interface to make
sure format strings will not leak into the clkdev.

$ git grep '\bclk_register_clkdev\b' | grep % | wc -l
0

Unfortunately, all the internals expect a va_list even though they treat
a NULL format string as special. To deal with this, we must pass either
(..., "%s", string) or (..., NULL) so that a the va_list will be created
correctly (passing the name as an argument, not as a format string).

Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2016-02-16 16:34:18 +00:00
Chen-Yu Tsai 33f60d0260 clk: sunxi: Fix sun8i-a23-apb0-clk divider flags
The APB0 clock on A23 is a zero-based divider, not a power-of-two based
divider.

Note that this patch does not apply cleanly to kernels before 4.5-rc1,
which added CLK_OF_DECLARE support to this driver.

Fixes: 57a1fbf284 ("clk: sunxi: Add A23 APB0 divider clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-16 09:47:41 +01:00
Shawn Lin fc6d875ecb clk: rockchip: fix coding style for clk-cpu.c
Fix the issue reported by checkpatch:
ERROR: space prohibited before that ',' (ctx:WxW)
+               writel(clksel->val , cpuclk->reg_base + clksel->reg);

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 23:38:35 +01:00
Shawn Lin 022dce0bd0 clk: rockchip: don't return NULL when registering mmc branch fails
Avoid return NULL if rockchip_clk_register_mmc fails, otherwise
rockchip_clk_register_branches print "unknown clock type". The acutal
case is that it's a known clock type but we fail to regiser it, which
may makes user confuse the reason of failure.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 23:37:27 +01:00
Shawn Lin ddd02e1456 clk: rockchip: don't return NULL when registering inverter fails
Avoid return NULL if rockchip_clk_register_inverter fails, otherwise
rockchip_clk_register_branches print "unknown clock type". The acutal
case is that it's a known clock type but we fail to regiser it, which
may makes user confuse the reason of failure.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 23:35:20 +01:00
Shawn Lin eb4e10c61d clk: rockchip: check grf when waiting pll lock
rockchip_clk_get_grf pass on return value from
syscon_regmap_lookup_by_phandle, so we check grf to
make sure whether to do the following things or not.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 22:38:27 +01:00
Shawn Lin 282312d1ac clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
Add clk_disable_unprepare to handle cpuclk->alt_parent if
rockchip_clk_register_cpuclk fails.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15 22:32:00 +01:00
Michael Turquette 70750ff2c9 Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
 place in the clock tree instead of having to register factor
 clocks in the init callback separately. And as always some more
 clock-ids and non-regression fixes for mistakes introduced in
 past kernel releases.
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Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
2016-02-15 11:59:45 -08:00
Bai Ping ee36027427 clk: imx: Add clock support for imx6qp
most of the clock tree structures on i.MX6 Quad Plus are
same as on i.MX6Q. there still some differences between
these two SOCs. compared to the i.XM6Q, the differents of
clocks on i.MX6QP is mainly on:

1. New clock gate added to support the PRE and PRG modules
2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and
   CAN clock roots.
3. MMDC channel 1 clock gate is now controllable.
4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP
5. EMI clock root divider fix
6. other updates fo CSCMRx, CSCDRx and CS2CDR registers.

detailed infomation, please refer to the i.MX6QP RM.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-14 11:06:29 +08:00
Stephen Boyd c430daf951 Revert "clk: qcom: Specify LE device endianness"
This reverts commit 329cabcecf.

The commit that caused us to specify LE device endianness here,
29bb45f25f (regmap-mmio: Use native endianness for read/write,
2015-10-29), has been reverted in mainline so now when we specify
LE it actively breaks big endian kernels because the byte
swapping in regmap-mmio is incorrect. Let's revert this change
because it will 1) fix the big endian kernels and 2) be redundant
to specify LE because that will become the default soon.

Cc: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-12 14:24:24 -08:00
Rajendra Nayak 7208d1d9c5 clk: qcom: mmcc8974: Use gdscs .parent and remove genpd calls
With gdsc driver capable of handling hierarchical power domains,
specify oxili_gdsc as parent of oxilicx_gdsc.

Remove all direct calls to genpd from the mmcc clock driver. The
adding and removing of subdomains is now handled from within
the gdsc driver.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:34:04 -08:00
Rajendra Nayak 7e824d5079 clk: qcom: gdsc: Add mmcc gdscs for msm8996 family
Add all gdsc data which are part of mmcc on msm8996 family

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:34:03 -08:00
Rajendra Nayak 52111672f7 clk: qcom: gdsc: Add GDSCs in msm8996 GCC
Add all data for the GDSCs which are part of msm8996 GCC block

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:26:19 -08:00
Rajendra Nayak a823bb9fbe clk: qcom: gdsc: Add support for votable gdscs
Some gdscs might be controlled via voting registers and might not
really disable when the kernel intends to disable them (due to other
votes keeping them enabled)
Mark these gdscs with a flag for we do not check/wait on a disable
status for these gdscs within the kernel disable callback.

Also at boot, if these GDSCs are found to be ON, we make sure we
vote for them before we inform the genpd framework about their
status. If genpd gets no users, it then disables (removes the vote)
them as part of genpd_poweroff_unused()

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:24:53 -08:00
Rajendra Nayak 77b1067a19 clk: qcom: gdsc: Add support for gdscs with gds hw controller
Some gdsc power domains can have a gds_hw_controller block inside
to help ensure all slave devices within the power domain are idle
before the gdsc is actually switched off.
This is mainly useful in power domains which host a MMU, in which
case its necessary to make sure there are no outstanding MMU operations
or pending bus transactions before the power domain is turned off.

In gdscs with gds_hw_controller block, its necessary to check the
gds_hw_ctrl status bits instead of the ones in gdscr, to determine
the state of the powerdomain.

While at it, also move away from using jiffies and use ktime APIs
instead for busy looping on status bits.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:24:03 -08:00
Rajendra Nayak c2c7f0a474 clk: qcom: gdsc: Add support for hierarchical power domains
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs
specify the parents (if any) and the driver add genpd subdomains for them.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-11 16:24:00 -08:00
Maxime Ripard b0b6413f0d clk: sunxi: Remove clk_register_clkdev calls
Now that our protection code doesn't use the global name lookup anymore, we
can remove the clkdev registrations.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 20:05:47 +01:00
Maxime Ripard 3a4d9af48a clk: sunxi: Remove old probe and protection code
Now that we don't have any user left for the old registration code, we can
remove it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 20:05:47 +01:00
Maxime Ripard c087230875 clk: sunxi: convert current clocks registration to CLK_OF_DECLARE
The current clock registration and protection code has a few drawbacks, the
two main ones being that we create a lot of orphans clock in the
registration phase, which will be troublesome when we will start being less
relaxed about them.

The protection code also relies on clkdev, which we don't really use but
for this particular case.

Fix both at the same time by moving everyone to the CLK_OF_DECLARE that
will probe our clock tree in the right and thus avoid orphans, and by
protecting directly the clock returned by our registration function.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 20:05:46 +01:00
Maxime Ripard 5b5226d17d clk: sunxi: Make clocks setup functions take const pointer
All the data structure that we pass to the clocks setup functions are
declared const, while our setup functions expects a regular pointer. This
was hidden by the fact that we cast a void * pointer back to these
structures, which made it go unnoticed.

Fix the functions prototype.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 18:17:04 +01:00
Maxime Ripard 96f185ac9a clk: sunxi: Make clocks setup functions return their clock
The clocks registration code in clk-sunxi was most of the time not
returning the struct clk (or struct clk array) that was registered,
preventing the users of such functions to manipulate it, for example to
protect it.

Make them return it so that we can start using it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-11 18:17:03 +01:00
Sylvain Lemieux 7e0810c948 clk: lpc32xx: add HCLK PLL output configuration
This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.

If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.

The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10 12:45:16 -08:00
Stephen Boyd 58bb621536 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: versatile: mask VCO bits before writing
2016-02-10 12:44:33 -08:00
Linus Walleij df9cd56421 clk: versatile: mask VCO bits before writing
The Versatile syscon ICST driver OR:s the bits into place but
forgets to mask the previous value, making the code only work
if the register is zero or giving haphazard results. Mask the
19 bits used by the Versatile syscon interface register.

Regression caused and now fixed by yours truly.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Fixes: 179c8fb3c2 ("clk: versatile-icst: convert to use regmap")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-10 09:56:31 -08:00
Sylvain Lemieux 4db9a9ba60 clk: lpc32xx: do not register clock "0"
The following errors are display in the console during the power-on:
[    0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12
[    0.000000] lpc32xx_clk_init: failed to register (null) clock: -12

There is no need to register clock "0"; the first clock used is 1;

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
[sboyd@codeaurora.org: s/prepare/register/]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09 16:19:34 -08:00
Masahiro Yamada 2430a94d1e clk: fix __clk_init_parent() for single parent clocks
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"),
__clk_init_parent() called .get_parent() only for multi-parent
clocks.  That commit changed the behavior to call .get_parent()
if available even for single-parent clocks and root clocks.

It turned out a problem because there are some single-parent clocks
that implement .get_parent() callback and return non-zero index.
The SOCFPGA clock is the case; the commit broke the SOCFPGA boards.

To keep the original behavior, invoke .get_parent() only when
num_parents is greater than 1.

Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-09 10:18:48 -08:00
Sudip Mukherjee 66f5ce2538 clk: qcom: common: check for failure
We were not checking the return from devm_add_action() which can fail.
Start using the helper and devm_add_action_or_reset() and return
directly as we know that the cleanup has been done by this helper.

Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 17:06:43 -08:00
Andreas Färber bb473593c8 clk: meson: Fix meson_clk_register_clks() signature type mismatch
As preparation for arm64 based mesongxbb, which pulls in this code once
enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch.
The loop uses a local unsigned int variable, so adopt that type,
matching the header.

Fixes: 7a29a86943 ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:22:44 -08:00
Arnd Bergmann 60ea57a433 clk: socfpga: fix __init annotation
clang found a bug with the __socfpga_pll_init definition:

drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and
      global variables

This moves the __init annotation to the right place so the function
actually gets discarded.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:13:31 -08:00
Mike Looijmans c7d5a46b10 drivers/clk/Kconfig: Move the TI CDCE chips close together
There are two TI CDCE clock chips in this file. Move them close
together so they're easier to find.

No functional change, just cosmetic.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Alphabetize]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:10:32 -08:00
Mike Looijmans 048c58b4e1 drivers/clk/Kconfig: Fix typo "Sypport" instead of "Support"
Simple cosmetic fix.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08 14:09:49 -08:00
Stephen Boyd f2626ba965 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: tegra: super: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warning for pll_m
  clk: tegra: Use definition for pll_u override bit
  clk: tegra: Fix warning caused by pll_u failing to lock
  clk: tegra: Fix clock sources for Tegra210 EMC
  clk: tegra: Add the APB2APE audio clock on Tegra210
  clk: tegra: Add missing of_node_put()
  clk: tegra: Fix PLLE SS coefficients
  clk: tegra: Fix typos around clearing PLLE bits during enable
  clk: tegra: Do not disable PLLE when under hardware control
  clk: tegra: Fix pllx dyn step calculation
  clk: tegra: pll: Fix potential sleeping-while-atomic
  clk: tegra: Fix the misnaming of nvenc from msenc
  clk: tegra: Fix naming of MISC registers
  clk: tegra: Remove improper flags for lock_enable
  clk: tegra: Fix divider on VI_I2C
2016-02-08 14:01:10 -08:00
Stephen Boyd 0e954fea5b clk: tegra: Fixes for v4.5-rc3
This set contains a bunch of miscellaneous fixes that have accumulated
 over the past couple of weeks, primarily for the Tegra210 support added
 in v4.5-rc1.
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Merge tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes

Pull tegra fixes from Thierry Reding:

clk: tegra: Fixes for v4.5-rc3

This set contains a bunch of miscellaneous fixes that have accumulated
over the past couple of weeks, primarily for the Tegra210 support added
in v4.5-rc1.

* tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: super: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warnings for functions not declared as static
  clk: tegra: Fix sparse warning for pll_m
  clk: tegra: Use definition for pll_u override bit
  clk: tegra: Fix warning caused by pll_u failing to lock
  clk: tegra: Fix clock sources for Tegra210 EMC
  clk: tegra: Add the APB2APE audio clock on Tegra210
  clk: tegra: Add missing of_node_put()
  clk: tegra: Fix PLLE SS coefficients
  clk: tegra: Fix typos around clearing PLLE bits during enable
  clk: tegra: Do not disable PLLE when under hardware control
  clk: tegra: Fix pllx dyn step calculation
  clk: tegra: pll: Fix potential sleeping-while-atomic
  clk: tegra: Fix the misnaming of nvenc from msenc
  clk: tegra: Fix naming of MISC registers
  clk: tegra: Remove improper flags for lock_enable
  clk: tegra: Fix divider on VI_I2C
2016-02-08 13:51:04 -08:00
Yoshihiro Shimoda 7826c61138 clk: shmobile: r8a7795: Add USB-DMAC clocks
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-08 16:26:54 +01:00
Dirk Behme 90c073e539 clk: shmobile: r8a7795: Add SD divider support
This patch adds SD[0..3] clock divider support for R-Car Gen3 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-08 16:26:04 +01:00
Stephen Boyd 47b0eeb3dc clk: Deprecate CLK_IS_ROOT
We don't use CLK_IS_ROOT but in a few places in the common clk
framework core. Let's replace those checks with a check for the
number of parents a clk has instead of the flag, freeing up one
flag for something else. We don't remove the flag yet so that
things keep building, but we'll remove it once all drivers have
removed their flag usage.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-06 23:38:26 -08:00
Stephen Boyd 14b04f28a0 clk: gpio: Make into a platform driver
clk_get() for DT based clks already returns EPROBE_DEFER when the
OF clk provider is not present. So having all this code in the
clk provider to return EPROBE_DEFER when the gpio isn't ready yet
can be replaced with a platform driver that doesn't add the clk
provider until the gpio can be requested. Get rid of the
OF_CLK_DECLARE and convert this to a platform driver instead.

Tested-by: Jyri Sarha <jsarha@ti.com>
Cc: Sergej Sawazki <ce3a@gmx.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon@solid-run.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-06 23:38:20 -08:00
Heiko Stuebner 36714529f8 clk: rockchip: convert manually created factor clocks to the new type
Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.

This also unifies the artificial separation of the hclk_vcodec etc clocks
again.

We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 15:54:20 +01:00
Heiko Stuebner 29a30c269a clk: rockchip: add a factor clock type
Add a clock type for fixed factor clocks. This allows us to define fixed
factor clocks where they appear in the clock hierarchy instead of in the
init function.

The additional factor_gate type, finally allows us to model some last
parts of the clock tree correctly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 15:49:09 +01:00
Heiko Stuebner aebe3ad801 clk: rockchip: fix parent of hclk_vcodec on rk3036
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock
hclk_vcodec_pre in between and not a child of hclk_disp_pre.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04 13:53:15 +01:00
Andrzej Hajda 02ed910cb4 clk/samsung: exynos5433: add pclk_decon clock
This undocumented gate clock is used by DECON IP.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-03 11:03:50 +01:00
Andrzej Hajda 68b2206a57 clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
HDMI driver must re-parent respective muxes during HDMI-PHY on/off
to HDMI-PHY output clocks. To reference those clocks their
definitions should be added.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-02-03 11:03:34 +01:00
Shawn Lin 2467b6745e clk: rockchip: free memory in error cases when registering clock branches
Add free memeory if rockchip_clk_register_branch fails.

Fixes: a245fecbb8 ("clk: rockchip: add basic infrastructure...")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-02 22:09:50 +01:00
Insu Yun 4106a3d9eb clk: unlock for handling unregistered clock
If clock is already unregistered, it returns with holding lock.
It needs to be unlocked.

Signed-off-by: Insu Yun <wuninsu@gmail.com>
[sboyd@codeaurora.org: Use goto instead]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:54:07 -08:00
Arnd Bergmann 7001ec560a clk: vt8500: don't return possibly uninitialized data
The clk-vt8500.c driver would previously enter an endless loop
when invalid settings got requested, this was now fixed. However,
the driver will now return uninitialized data for a subset of those
cases instead, as the gcc correctly warns:

clk/clk-vt8500.c: In function 'wm8650_find_pll_bits':
clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized]
  *divisor2 = best_div2;
            ^
clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized]
  *divisor1 = best_div1;
            ^
clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized]
  *multiplier = best_mul;

This reworks the error handling in the driver so we now return
-EINVAL from clk_round_rate() and clk_set_rate() when we get
impossible inputs.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 090341b0a9 ("clk: vt8500: fix sign of possible PLL values")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:17 -08:00
Masahiro Yamada e8f0e68ec0 clk: slightly optimize clk_core_set_parent()
If clk_fetch_parent_index() fails, p_rate is unused.  Move the
assignment after the error checking.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:17 -08:00
Masahiro Yamada 470b5e2f97 clk: simplify clk_fetch_parent_index() function
The clk_core_get_parent_by_index can be used as a helper function
to simplify the implementation of clk_fetch_parent_index().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:16 -08:00
Masahiro Yamada 508f884a66 clk: make sure parent is not NULL in clk_fetch_parent_index()
If parent is given with NULL, clk_fetch_parent_index() could return
a positive index value.

Currently, parent is checked by the callers of this function, but
it would be safer to do it in this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:15 -08:00
Masahiro Yamada 0e8f6e499e clk: walk the orphan clock list more simply
This loop can be much simpler. If a new parent is available for
orphan clocks, __clk_init_parent(orphan) can detect it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:14 -08:00
Masahiro Yamada 858d588156 clk: avoid circular clock topology
Currently, clk_register() never checks a circular parent looping,
but clock providers could register such an insane clock topology.
For example, "clk_a" could have "clk_b" as a parent, and vice versa.
In this case, clk_core_reparent() creates a circular parent list
and __clk_recalc_accuracies() calls itself recursively forever.

The core infrastructure should be kind enough to bail out, showing
an appropriate error message in such a case.  This helps to easily
find a bug in clock providers.  (uh, I made such a silly mistake
when I was implementing my clock providers first.  I was upset
because the kernel did not respond, without any error message.)

This commit adds a new helper function, __clk_is_ancestor().  It
returns true if the second argument is a possible ancestor of the
first one.  If a clock core is a possible ancestor of itself, it
would make a loop when it were registered.  That should be detected
as an error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:13 -08:00
Masahiro Yamada 5146e0b059 clk: simplify __clk_init_parent()
The translation from the index into clk_core is done by
clk_core_get_parent_by_index().  The if-block for num_parents == 1
case is duplicating the code in the clk_core_get_parent_by_index().

Drop the "if (num_parents == 1)" from the special case.  Instead,
set the index to zero if .get_parent() is missing.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:53:10 -08:00
Masahiro Yamada 3c8e77dd20 clk: move checking .get_parent to __clk_core_init()
The .get_parent is mandatory for multi-parent clocks.  Move the check
to __clk_core_init(), like other callback checkings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
[sboyd@codeaurora.org: Squashed in error path handling, fix typos
in commit message]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-02 11:52:06 -08:00
Andre Przywara d221b7a878 clk: sunxi: improve error reporting for the mux clock
clk_register_mux returns a pointer wrapped error value in case of
failure, so a simple NULL check is not sufficient to catch errors.
Fix that and elaborate on the failure reason on the way. The whole
function does not return any error value, so silently failing may
leave users scratching their heads because the kernel does not
provide any clues on what's wrong.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 19:02:00 +01:00
Arnd Bergmann 14b5a4bf7a clk: sunxi: don't mark sun6i_ar100_data __initconst
The clk-sun6i-ar100 clk driver is a platform driver that may use
deferred probing, so its probe function must not access
__init symbols. Kbuild warns about this:

WARNING: drivers/clk/sunxi/built-in.o(.text+0x15f0): Section mismatch in reference from the function sun6i_a31_ar100_clk_probe() to the (unknown reference) .init.rodata:(unknown)
The function sun6i_a31_ar100_clk_probe() references
the (unknown reference) __initconst (unknown).
This is often because sun6i_a31_ar100_clk_probe lacks a __initconst
annotation or the annotation of (unknown) is wrong.

Removing the __initconst annotation avoids the warning and makes
deferred probing work.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 3ca2377b6f ("clk: sunxi: rewrite sun6i-ar100 using factors clk")
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 18:33:25 +01:00
Jon Hunter 5a1d5eff3e clk: tegra: super: Fix sparse warnings for functions not declared as static
Sparse reports the following warnings for structures and functions that
should be declared static:

drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol
 'tegra_super_gen_info_gen4' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol
 'tegra_super_gen_info_gen5' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol
 'tegra_super_clk_init' was not declared. Should it be static?

Fix this by making the above static.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:34 +01:00
Jon Hunter fd360e2084 clk: tegra: Fix sparse warnings for functions not declared as static
Sparse reports the following warnings for functions in clk-tegra210.c
that should be declared as static:

drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol
 'tegra210_pllcx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol
 '_pllc_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol
 '_pllc2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol
 '_pllc3_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol
 '_plla1_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol
 'tegra210_plla_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol
 'tegra210_plld_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol
 'tegra210_plld2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol
 'tegra210_plldp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol
 'tegra210_pllc4_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol
 'tegra210_pllre_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol
 'tegra210_pllx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol
 'tegra210_pllmb_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol
 'tegra210_pllp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol
 'tegra210_pllu_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol
 'tegra210_clk_adjust_vco_min' was not declared. Should it be static?

Fix this by declaring the above as static.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:33 +01:00
Jon Hunter d9e657919a clk: tegra: Fix sparse warning for pll_m
Sparse generates the following warning for the pll_m params structure:

drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry
 defined twice
drivers/clk/tegra/clk-tegra210.c:1570:10:   also defined here

Fix this by correcting the index for the MISC1 register.

Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks")

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:32 +01:00
Jon Hunter 2d5b6cf84a clk: tegra: Use definition for pll_u override bit
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
the code directly uses the bit number. Therefore, use the definition,
PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:31 +01:00
Jon Hunter 0649c3232b clk: tegra: Fix warning caused by pll_u failing to lock
If the pll_u is not configured by the bootloader, then on kernel boot the
following warning is seen:

 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
 tegra_init_from_table: Failed to enable pll_u_out1
 ------------[ cut here ]------------
 WARNING: at drivers/clk/tegra/clk.c:269
 Modules linked in:

 CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
 Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
 task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
 PC is at tegra_init_from_table+0x140/0x164
 LR is at tegra_init_from_table+0x140/0x164
 pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
 sp : ffffffc0bc0abd50
 x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
 x27: ffffffc000a06000 x26: ffffffc0bc019780
 x25: ffffffc00086a708 x24: ffffffc00086a790
 x23: ffffffc0006d7188 x22: ffffffc0bc010000
 x21: 000000000000016e x20: ffffffc0bc00d100
 x19: ffffffc000944178 x18: 0000000000000007
 x17: 000000000000000e x16: 0000000000000001
 x15: 0000000000000007 x14: 000000000000000e
 x13: 0000000000000013 x12: 000000000000001a
 x11: 000000000000004d x10: 0000000000000750
 x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
 x7 : 0000000000000001 x6 : 0000000002d5f0f8
 x5 : 0000000000000000 x4 : 0000000000000000
 x3 : 0000000000000002 x2 : ffffffc000996724
 x1 : 0000000000000000 x0 : 0000000000000032

 ---[ end trace cbd20ae519e92ced ]---
 Call trace:
 [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
 [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
 [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
 [<ffffffc00008291c>] do_one_initcall+0x90/0x194
 [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
 [<ffffffc000636bb0>] kernel_init+0x10/0xdc
 [<ffffffc000085cd0>] ret_from_fork+0x10/0x40
 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
 tegra_init_from_table: Failed to enable pll_u_out2
 ------------[ cut here ]------------

pll_u can be either controlled by software or hardware and this is
selected via the OVERRIDE bit in the pll_u base register. In the function
tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
hardware control of the pll. However, at the same time the pll_u clocks
are populated in the init_table for tegra210 and so software will try to
configure the pll_u if it is not already configured and hence, the above
warning is seen when the pll fails to lock. Remove the pll_u clocks from
the init_table so that software does not try to configure this pll on
boot.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:31 +01:00
Jon Hunter 4f8d444030 clk: tegra: Fix clock sources for Tegra210 EMC
The EMC clock sources for Tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If Tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.

Also add the additional pll_p clock source for the EMC.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:30 +01:00
Jon Hunter 2956994168 clk: tegra: Add the APB2APE audio clock on Tegra210
The APB2APE clock for the audio subsystem is required for powering up the
audio power domain and accessing the various modules in this subsystem on
Tegra210 devices. Add this clock for Tegra210.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:29 +01:00
Amitoj Kaur Chawla 047d6d8401 clk: tegra: Add missing of_node_put()
for_each_child_of_node() performs an of_node_get() on each iteration, so
before breaking out of the loop an of_node_put() is required.

Found using Coccinelle. The semantic patch used for this is as follows:

// <smpl>
@@
expression e;
local idexpression child;
@@

 for_each_child_of_node(root, child) {
   ... when != of_node_put(child)
       when != e = child
(
   return child;
|
+  of_node_put(child);
?  return ...;
)
   ...
 }
// </smpl>

Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:28 +01:00
Mark Kuo 442f53fb1b clk: tegra: Fix PLLE SS coefficients
The PLLE SS coefficients are different between Tegra210 and Tegra114.
Add SoC generation specific versions for Tegra114 and Tegra210 and use
them in their respective ->enable() callbacks.

Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:27 +01:00
Rhyland Klein fd2963b071 clk: tegra: Fix typos around clearing PLLE bits during enable
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
them. This patch fixes both places where we incorrectly set instead of
cleared those bits.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:26 +01:00
Mark Kuo f59b0168d3 clk: tegra: Do not disable PLLE when under hardware control
Software should not disable PLLE if PLLE is already put under hardware
control.

Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:25 +01:00
Rhyland Klein 3dad5c5fa1 clk: tegra: Fix pllx dyn step calculation
The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:24 +01:00
Andrew Bresticker 3eb61566a6 clk: tegra: pll: Fix potential sleeping-while-atomic
Since the ->enable() callback is called with a spinlock held, we cannot
call potentially blocking functions such as clk_get_rate() or
clk_get_parent(), so use the unlocked versions instead.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
[rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as
it isn't present upstream]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:23 +01:00
Rhyland Klein 736971bed2 clk: tegra: Fix the misnaming of nvenc from msenc
When adding the nvenc clock, it was partially named msenc in the code.
Since the msenc clock isn't present in Tegra210 and has been replaced by
the nvenc clock, its misleading to see it present. Therefore, properly
rename it.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:22 +01:00
Rhyland Klein 474f2ba268 clk: tegra: Fix naming of MISC registers
Some register for PLLM and PLLMB were named MISC0 but according to the
TRM, they have different names. Sync up the names to make it easier to
understand which register they are really referring to.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-02-02 15:49:20 +01:00
Vishnu Patekar be338e4c58 clk: sunxi: add bus gates for A83T
A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 14:14:24 +01:00
Vishnu Patekar 2d6f5f0cf6 clk: sunxi: Add apb0 gates for A83T
APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-02 14:11:46 +01:00
Masahiro Yamada c44fccb5f7 clk: replace pr_warn() with pr_err() for fatal cases
These three cases let clk_register() fail.  They should be considered
as error messages.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:59 -08:00
Masahiro Yamada 3c436bf95a clk: drop the initial core->parents look-ups from __clk_core_init()
The core->parents is a cache to save expensive clock parent look-ups.
It will be filled as needed later.  We do not have to do it here.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:54 -08:00
Masahiro Yamada 88cfbef2ac clk: simplify clk_core_get_parent_by_index()
Drop the "if (!core->parents)" case and refactor the function a bit
because core->parents is always allocated.  (Strictly speaking, it is
ZERO_SIZE_PTR if core->num_parents == 0, but such a case is omitted
by the if-conditional above.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:50 -08:00
Masahiro Yamada 176d11690b clk: move core->parents allocation to clk_register()
Currently, __clk_core_init() allows failure of the kcalloc() for the
core->parents.  So, clk_fetch_parent_index() and __clk_init_parent()
also try to allocate core->parents in case it has not been allocated
yet.  Scattering memory allocation here and there makes things
complicated.

Like other clk_core members, allocate core->parents in clk_register()
and let it fail in case of memory shortage.  If we cannot allocate
such a small piece of memory, the system is already insane.  There is
no point to postpone the memory allocation.

Also, allocate core->parents regardless of core->num_parents.  We want
it even if core->num_parents == 1 because clk_fetch_parent_index()
might be called against the clk_core with a single parent.

If core->num_parents == 0, core->parents is set to ZERO_SIZE_PTR. It
is harmless because no access happens to core->parents in such a case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:46 -08:00
Masahiro Yamada 3a6e845451 clk: change sizeof(struct clk *) to sizeof(*core->parents)
Now, the clock parent is not "struct clk *", but "struct clk_core *".
Of course, the size of a pointer is always same, but strictly speaking,
sizeof(struct clk *) should be sizeof(struct clk_core *) here.

This mismatch happened when we split the structure into struct clk
and struct clk_core.  For the potential possibility of future renaming,
sizeof(*core->parents) would be better.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:43 -08:00
Masahiro Yamada 027f942ce4 clk: remove unnecessary !core->parents conditional
This if-block has been here since the introduction of the common
clock framework.  Now no clock drivers are statically initialized.
core->parent is always NULL at this point.  Drop the redundant
check and the confusing comment.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:39 -08:00
Masahiro Yamada be45ebf25f clk: rename __clk_init() into __clk_core_init()
Now this function takes clk_core as its argument.  __clk_core_init()
would be more suitable for the name of this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:36 -08:00
Masahiro Yamada d35c80c248 clk: change the argument of __clk_init() into pointer to clk_core
The argument clk_user is used only for the clk_user->core.  The rest
of this function only takes care of clk_core.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:32 -08:00
Masahiro Yamada d9e743408e clk: remove unused first argument of __clk_init()
The "struct device *dev" is not used at all in this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-01 17:01:28 -08:00
Arnd Bergmann ea7743e271 ARM: pxa: define clock registers as __iomem
We should not dereference registers as pointers, so use readl/writel
instead for these registers.

The clock registers are accessed in multiple files, so we have to
change them all at once.

I stumbled over these registers while looking at something unrelated.
There are in fact other registers with the same problem, but I did
not try to address those at this point.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2016-02-01 21:43:41 +01:00
Stephen Boyd 4fcad2eaaa Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: rockchip: rk3368: fix some clock gates
  clk: rockchip: rk3036: rename emac ext source clock
  clk: rockchip: rk3036: fix the div offset for emac clock
  clk: rockchip: rk3036: fix uarts clock error
  clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-29 17:26:31 -08:00
Stephen Boyd 60c7e2d2ed Fixes for wrong register offsets in both rk3036 and rk3368.
Also rename the external input for the emac on rk3036, which
 should still be ok to do, as that binding was only introduced
 during this merge-window.
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Merge tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

Pull rockchip fixes from Heiko Stuebner:

Fixes for wrong register offsets in both rk3036 and rk3368.
Also rename the external input for the emac on rk3036, which
should still be ok to do, as that binding was only introduced
during this merge-window.

* tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3368: fix some clock gates
  clk: rockchip: rk3036: rename emac ext source clock
  clk: rockchip: rk3036: fix the div offset for emac clock
  clk: rockchip: rk3036: fix uarts clock error
  clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-29 17:24:28 -08:00
Arnd Bergmann 9849fadfc0 clk: st: avoid uninitialized variable use
My previous patch fixed some warnings about printing a couple
of variables that are always uninitialized in quadfs_pll_fs660c32_set_rate(),
but I now got a warning that only shows up in some configurations (i.e.
without gcc -Os) about the params.ndiv being used uninitialized in the
error case:

drivers/clk/st/clkgen-fsyn.c: In function 'quadfs_pll_fs660c32_set_rate':
drivers/clk/st/clkgen-fsyn.c:584:75: warning: 'params.ndiv' may be used uninitialized in this function [-Wmaybe-uninitialized]
drivers/clk/st/clkgen-fsyn.c:574:16: note: 'params.ndiv' was declared here

This changes the error handling so we bail for invalid arguments rather
than continuing with uninitialized data.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:20:08 -08:00
Stephen Boyd 3d6f1c7212 clk: axi-clkgen: Remove sometimes impossible check
The size of unsigned long on 64-bit architectures is equal to the
size of u64, so this check is impossible there. This throws off
static checkers:

drivers/clk/clk-axi-clkgen.c:331 axi_clkgen_recalc_rate() warn:
impossible condition '(tmp > (~0)) => (0-u64max > u64max)'

Let's change this code to use min_t() instead so that we
get the same effect on architectures where sizeof(unsigned long)
doesn't equal sizeof(u64).

Cc: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:11:02 -08:00
Lars-Peter Clausen 62d1e7823d clk: axi-clkgen: Add multi-parent support
The clock generator has two clock inputs that can be used as the reference
clock. Add support for switching between them at runtime.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:06:14 -08:00
Lars-Peter Clausen d95b599c03 clk: axi-clkgen: Remove version 1 support
Version 1 of the axi-clkgen core has not been used in new designs for over
two years now. This is a soft peripheral used in FPGAs and anybody who has
updated their kernel to the latest version will also have updated the
bitstream containing the clock generator. So it should be safe to drop
support for this now.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 17:04:07 -08:00
LABBE Corentin 8d0a69d735 clk: palmas: fix a possible NULL dereference
of_match_device could return NULL, and so cause a NULL pointer
dereference later.
Even if the probability of this case is very low, fixing it made
static analyzers happy.

Solving this with of_device_get_match_data made also code simplier.

Reported-by: coverity (CID 1324137)
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:57:09 -08:00
LABBE Corentin 93fffbbee1 clk: palmas: constify the palmas_clks_of_match_data structure
The palmas_clks_of_match_data structures are never modified.
This patch constify them.

Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:57:02 -08:00
Masahiro Yamada 653d1452b4 clk: optimize the divider walk in clk_divider_bestdiv()
Because _next_div() returns a valid divider, there is no need to
consult _is_valid_div() for the validity of the divider in every
iteration.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:45:32 -08:00
Andrzej Hajda 090341b0a9 clk: vt8500: fix sign of possible PLL values
With unsigned values underflow in loops can occur resulting in
theoretically infinite loops.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:43:58 -08:00
Masahiro Yamada 0b225e41e3 clk: add clk_unregister_fixed_rate()
Allow to unregister fixed rate clock.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:37:24 -08:00
Masahiro Yamada cbf9591f66 clk: add clk_unregister_fixed_factor()
Allow to unregister fixed factor clock.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:35:49 -08:00
Srinivas Kandagatla 5540ac8da1 clk:gcc-msm8916: add missing mss_q6_bimc_axi clock
This clock is required for loading the qdsp firmware.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:35:22 -08:00
Stephen Boyd 4c9f242203 Merge branch 'clk-iproc' into clk-next
* clk-iproc:
  clk: iproc: Remove __init from header
  clk: iproc: Add support for Cygnus audio clocks
  Documentation: dt-bindings: Add DT bindings for Cygnus audio clock
2016-01-29 16:35:02 -08:00
Ray Jui df416e565d clk: iproc: Remove __init from header
Remove __init macro from all function prototypes in clk-iproc.h

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:31:40 -08:00
Simran Rai bcd8be1398 clk: iproc: Add support for Cygnus audio clocks
This patch adds support for Broadcom Cygnus audio PLL and leaf
clocks

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:31:38 -08:00
James Liao b9e65ebc65 clk: Move vendor's Kconfig into CCF menu section
Move all vendor's Kconfig into CCF menu section to prevent
new drivers putting their Kconfig files in a wrong place.

Some Kconfigs need to be modified at the same time to avoid build
warnings.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
[sboyd@codeaurora.org: Fix typos in commit message]
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 16:30:06 -08:00
James Liao 4974259e18 clk: mediatek: Fix memory leak on clock init fail
mtk_clk_register_composite() may leak memory due to some error
handling path don't free all allocated memory. This patch
free all pointers that may allocate memory before error return.
And it's safe because kfree() can handle NULL pointers.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 13:02:51 -08:00
Geliang Tang 5fd9c05c84 clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.

Signed-off-by: Geliang Tang <geliangtang@163.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:59:50 -08:00
Stephen Boyd f9285b54d6 clk: xgene: Remove return from void function
This function doesn't return anything because it's void. Drop the
return statement.

Cc: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:57:54 -08:00
Loc Ho 47727beb26 clk: xgene: Add SoC and PMD PLL clocks with v2 hardware
Add X-Gene SoC and PMD PLL clocks support for v2 hardware.
X-Gene SoC v2 and above use an slightly different SoC
and PMD PLL hardware logic.

Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:54:35 -08:00
Andi Shyti dedbb2724d clk: s2mps11: remove redundant code
The definition of s2mps11_name is meant to resolve the name of a
given clock. Remove it because the clocks have the same name we
can get it directly from the s2mps11_clks_init structure.

While in the probe function the s2mps11_clks is used only to
iterate through the s2mps11_clks. The naming itself brings
confusion and the readability does not improve much.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:47:22 -08:00
Andi Shyti 36da4def1e clk: s2mps11: remove redundant static variables declaration
The clk_table and clk_data are declared static. The clk_table
contains the three clock data structures belonging to the s2mps11
driver. In the probe function it gets stored into clk_data.

Remove clk_table and refer directly to clk_data.

clk_data, itself, is also declared static. Declare locally it
and allocate it inside the probe function, as it is not used
anywhere else.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:47:02 -08:00
Andi Shyti 31ad0e2a9a clk: s2mps11: allocate only one structure for clock init
The driver allocates three structures, s2mpsxx_clk_init, for
three different clock types (s2mps11, s2mps13 and s2mps14). They
are quite similar but they differ only by the name. Only one of
these structures is used, while the others lie unused in the
memory.

The clock's name, though, is not such a meaningful information
and by assigning the same name to the initial data we can avoid
over allocation. The common name chosen will be s2mps11,
coherently with the device driver name, instead of the clock
device.

Therefore, remove the structures associated to s2mps13 and
s2mps14 and use only the one referred to s2mps11 for all kind of
clocks.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:46:47 -08:00
Andi Shyti 26adc5fa27 clk: s2mps11: merge two for loops in one
The driver already loops once, there is no reason to loop again
for a different purpose. Merge the second loop into the first.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:46:06 -08:00
Heiko Stuebner 5035981979 clk-divider: make sure read-only dividers do not write to their register
Commit e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.

On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.

To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.

The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.

Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:44:37 -08:00
Marc Gonzalez eac2d86d60 clk: tango4: rename ARCH_TANGOX to ARCH_TANGO
Requested by arm-soc maintainer Kevin Hilman in v9 review.
http://article.gmane.org/gmane.linux.ports.arm.kernel/456331

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:08:02 -08:00
Axel Lin d22eb66b3c clk: scpi: Fix checking return value of platform_device_register_simple()
platform_device_register_simple() returns ERR_PTR on error.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:07:59 -08:00
Stephen Boyd 1ce133ec89 clk: mvebu: Mark ioremapped memory as __iomem
Silence the following sparse warning

drivers/clk/mvebu/dove-divider.c:252:14: warning: incorrect type in assignment (different address spaces)
drivers/clk/mvebu/dove-divider.c:252:14:    expected void *base
drivers/clk/mvebu/dove-divider.c:252:14:    got void [noderef] <asn:2>*
drivers/clk/mvebu/dove-divider.c:256:13: warning: incorrect type in argument 2 (different address spaces)
drivers/clk/mvebu/dove-divider.c:256:13:    expected void [noderef] <asn:2>*base
drivers/clk/mvebu/dove-divider.c:256:13:    got void *base
drivers/clk/mvebu/dove-divider.c:257:25: warning: incorrect type in argument 1 (different address spaces)
drivers/clk/mvebu/dove-divider.c:257:25:    expected void volatile [noderef] <asn:2>*iomem_cookie
drivers/clk/mvebu/dove-divider.c:257:25:    got void *base

Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29 12:06:47 -08:00
Chen-Yu Tsai 8f2bf2ad96 clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk
sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very
complicated clocks, but is not really needed here.

Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux
+ divider. This makes the code easier to understand.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:29 +01:00
Chen-Yu Tsai 3ca2377b6f clk: sunxi: rewrite sun6i-ar100 using factors clk
sun6i's AR100 clock is a classic factors clk case:

AR100 = ((parent mux) >> p) / (m + 1)

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:28 +01:00
Chen-Yu Tsai a78bb35552 clk: sunxi: rewrite sun6i-a31-ahb1-clk using factors clk with custom recalc
The factors clk implementation has been extended to support custom
recalc callbacks to support clocks that use one factor for certain
parents only, like a pre-divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:28 +01:00
Chen-Yu Tsai 50d6ea47ba clk: sunxi: factors: Drop round_rate from clk ops
The common clock framework requires either determine_rate or round_rate
to be implemented. We use determine_rate so we can pass the parent index
to the get_factors callback. This cannot be done easily with round_rate,
so just drop it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:27 +01:00
Chen-Yu Tsai 435b7be1d8 clk: sunxi: factors: Support custom formulas
Some clocks cannot be modelled using the standard factors clk formula,
such as clocks with special pre-dividers on one parent, or clocks
with all power-of-two dividers.

Add support for a custom .recalc callback for factors clk. Also pass
the current parent index to the .get_factor and .recalc callbacks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-29 11:30:27 +01:00
Alexander Kochetkov 89aa027e60 clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on rk3188
Allow sclk_i2s0 and i2s0_frac to change their parents rate as
that the upstream dividers are purely there to feed sclk_i2s0

Tested on radxarock-lite.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-29 10:18:49 +01:00
Shawn Lin bb07698fc8 clk: rockchip: fix wrong mmc phase shift for rk3228
mmc sample shift is 0 for rk3228 refer to user manaul.
So it's broken if we enable mmc tuning for rk3228.

Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-28 18:02:26 +01:00
Chen-Yu Tsai cfa6368860 clk: sunxi: factors: Consolidate get_factors parameters into a struct
The .get_factors callback of factors_clk has 6 parameters. To extend
factors_clk in any way that requires adding parameters to .get_factors
would make that list even longer, not to mention changing all the
function declarations.

Do this once now and consolidate all the parameters into a struct.
Also drop the space before function pointer arguments, since checkpatch
complains.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 18:57:37 +01:00
Chen-Yu Tsai 4cbeaebb8a clk: sunxi: factors: Add unregister function
sunxi's factors clk did not have an unregister function. This means
multiple structs were leaked whenever a factors clk was unregistered.

Add an unregister function for it. Also keep pointers to the mux and
gate structs so they can be freed.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 18:57:31 +01:00
Chen-Yu Tsai 78ca95c769 clk: sunxi: factors: Add clk cleanup in sunxi_factors_register() error path
sunxi_factors_register() does not check for failures or cleanup after
clk_register_composite() or other clk-related calls.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 18:56:42 +01:00
Chen-Yu Tsai b3e919e03c clk: sunxi: factors: Make struct clk_factors_config table const
struct clk_factors_config contains shifts/widths for the factors of
the factors clk. This is used to read out the factors from the register
value. In no case is it written to, so make it const.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-27 16:50:38 +01:00
Alexander Kochetkov e8b63288b3 clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks
hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.

Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Cc: stable@vger.kernel.org # 4.1.x-
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26 21:09:51 +01:00
Paweł Jarosz 2c41b5a775 clk: rockchip: add tsadc clock on rk3066
Set clock id for sclk_tsadc gating clock of tsadc in rk3066

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26 01:08:02 +01:00
Heiko Stuebner 219a5859c8 clk: rockchip: fix usbphy-related clocks
The otgphy clocks really only drive the phy blocks. These in turn
contain plls that then generate the 480m clocks the clock controller
uses to supply some other clocks like uart0, gpu or the video-codec.

So fix this structure to actually respect that hirarchy and removed
that usb480m fixed-rate clock working as a placeholder till now, as
this wouldn't even work if the supplying phy gets turned off while
its pll-output gets used elsewhere.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Michael Turquette <mturquette@baylibre.com>
2016-01-25 15:00:03 +01:00
Rhyland Klein 14050118af clk: tegra: Remove improper flags for lock_enable
Most PLL's don't actually have LOCK_ENABLE bits. However, most PLL's
also had that flag set, which meant that the clk code was trying to
enable locks, and inadvertantly flipping bits in other fields.

For PLLM, ensure the correct register is used for the misc_register.
PLL_MISC0 contains the EN_LCKDET bit which should be used for enabling
the lock, and PLLM_MISC1 shouldn't be used at all.

Lastly, remove some of the settings which would point to the EN_LCKDET
bits for some PLLs. There is no need to enable the locks, and that is
done as part of the set_defaults logic already.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-01-25 13:56:30 +01:00
Rhyland Klein 21e4903246 clk: tegra: Fix divider on VI_I2C
VI-I2C has 16 bits available for its divider. Switch the divider width
to 16 instead of 8 so correct rates can be set.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-01-25 13:27:51 +01:00