Improve the user friendliness of the DTS code base by including the
R-Car product name in each R-Car Gen2 DTSI file.
The product names are taken from:
Documentation/devicetree/bindings/arm/shmobile.txt
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the SATA device nodes on R-Car H1, H2, and M2-W to use a 2 MiB
I/O space, as specified in Rev.1.0 of the R-Car H1 and R-Car Gen2
hardware user manuals.
See also commit e9f0089b2d ("arm64: dts: r8a7795: Correct SATA
device size to 2MiB").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing properties (like, clock latency, voltage tolerance,
etc) as well to make it all work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This is a branch with a few merge requests that either came in late, or
took a while longer for us to review and merge than usual and thus cut
it a bit close to the merge window. We stage them in a separate branch
and if things look good, we still send them up -- and that's the case
here.
This is mostly DT additions for Renesas platforms, adding IP block
descriptions for existing and new SoCs.
There are also some driver updates for Qualcomm platforms for SMEM/QMI
and GENI, which is their generalized serial protocol interface.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late updates from Olof Johansson:
"This is a branch with a few merge requests that either came in late,
or took a while longer for us to review and merge than usual and thus
cut it a bit close to the merge window. We stage them in a separate
branch and if things look good, we still send them up -- and that's
the case here.
This is mostly DT additions for Renesas platforms, adding IP block
descriptions for existing and new SoCs.
There are also some driver updates for Qualcomm platforms for SMEM/QMI
and GENI, which is their generalized serial protocol interface"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits)
soc: qcom: smem: introduce qcom_smem_virt_to_phys()
soc: qcom: qmi: fix a buffer sizing bug
MAINTAINERS: Update pattern for qcom_scm
soc: Unconditionally include qcom Makefile
soc: qcom: smem: check sooner in qcom_smem_set_global_partition()
soc: qcom: smem: fix qcom_smem_set_global_partition()
soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private()
soc: qcom: smem: byte swap values properly
soc: qcom: smem: return proper type for cached entry functions
soc: qcom: smem: fix first cache entry calculation
soc: qcom: cmd-db: Make endian-agnostic
drivers: qcom: add command DB driver
arm64: dts: renesas: salvator-common: Add ADV7482 support
ARM: dts: r8a7740: Add CEU1
ARM: dts: r8a7740: Add CEU0
arm64: dts: renesas: salvator-common: enable VIN
arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7795-es1: add CSI-2 node
...
Enable support for the ARM Performance Monitor Units in the Cortex-A15
and Cortex-A7 CPU cores on R-Car H2 by adding device nodes for the two
PMUs.
New Linux output:
hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
hw perfevents: /pmu-1: failed to probe PMU!
hw perfevents: /pmu-1: failed to register PMU devices!
The last two lines are due to the Cortex-A7 CPU cores being described in
DT, but not enabled by the firmware.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores,
hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts
can be delivered to all 8 processor cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 5d3b50d3c0 ("ARM: dts: renesas: r8a7790: Add FDP1 instances")
introduced the FDP1 for the r8a7790, but broke the sort ordering of the
device tree nodes.
Move the last VSP up to it's peers to correct the ordering.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a7790 has three FDP1 instances.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit adds watchdog support to the r8a7790 dtsi.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adjusts the definition of the SMP routine size according
to the latest changes made by commit:
"ARM: shmobile: Add watchdog support"
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The internal LVDS encoder now has DT bindings separate from the DU. Port
the device tree over to the new model.
Fixes: c6a27fa41f ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
Fixes: 4bdb7aa7dc ("ARM: dts: r8a7790: add soc node")
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Consistently use a single space before a =.
This patch fixes instances where a tab is used instead.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Sort subnodes of root node to aid maintenance.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Sort the subnodes of the soc node to improve maintainability.
The sort key is the addresss on the bus with instances of the same
IP block grouped together.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add soc node to represent the bus and move all nodes with a base address
into this node. This is consistent with handling of R-Car Gen3, RZ/G1, and
R-Car V2H (R8A77920) SoCs upstream. It is intended to migrate other R-Car
Gen2 SoCs to this scheme.
The ordering is derived from simply moving each node with an address up to
before any nodes without a base address that occur before the soc node. To
improve maintainability follow-up patches will sort subnodes of both the
new soc node and the root node.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Consistently use a single space after a =.
This patch removes instances where a tab or multiple spaces are used
instead. It also avoids running over 80 columns in width in one of the
lines where whitespace is updated.
This patch should not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reduce size of thermal registers in DT for r8a7790 (R-Car H2) SoC.
According to the "User's Manual: Hardware" v2.00 the registers at base
0xe61f0000 extend to an offset of 0x10, rather than 0x14 which is the case
on the r8a73a4 (R-Mobile APE6).
This should not have any runtime affect as mapping granularity is PAGE_SIZE.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* r8a7745 (RZ/G1E) SoC
- Enable SMP
Fabrizio Castro says "Add DT node for the Advanced Power Management
Unit (APMU), add the second CPU core, and use "renesas,apmu" as
"enable-method"."
* r8a7743 (RZ/G1M) SoC
- Add node for thermal sensor module with thermal-zone support
* r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
- Add:
+ Renesas Core Match Timer (CMT) support
+ Renesas Timer Pulse Unit PWM Controller (TPU) support
+ Renesas PWM Timer Controller (PWM) support
* r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and
r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms
- Add sound support
* r8a7743 (RZ/G1M), r8a7745 (RZ/G1E) and r8a7792 (R-Car V2H) SoCs
- Allow DTBs of boards of these SoCs to build without any warnings when
compiled with W=1 using gcc-linaro-5.4.1-2017.05
+ Move nodes which have no reg property out of bus, they don't belong there
+ Also sort sub-nodes of root node to allow for easier maintenance
* r8a7790 (R-Car H2), r8a7791 (R-Car M2-W) and r8a7793 (R-Car M2-N) SoCs
- Correct critical CPU temperature
Chris Paterson says "The current R-Car Gen2 device trees define the CPU
critical temperature as 115°C.
The R-Car hardware manuals state that Tc = –40°C to +105°C. The thermal
sensor has an accuracy of ±5°C and there can be a temperature
difference of 1 or 2 degrees between Tjmax and the thermal sensor due
to the location of the latter.
This means that 95°C is a safer value to use.
This value should also apply to r8a7792 but thermal sensor support has
not been added yet."
* r8a7740 (R-Mobile A1) SoC
- Correct TPU register block size
Geert Uytterhoven says "The Timer Pulse Unit has registers that lie
outside the declared register block. Enlarge the register block size to
fix this.
This was probably based on the old platform code, which also assumed a
register block size of 0x100."
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Merge tag 'renesas-dt2-for-v4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.16
* r8a7745 (RZ/G1E) SoC
- Enable SMP
Fabrizio Castro says "Add DT node for the Advanced Power Management
Unit (APMU), add the second CPU core, and use "renesas,apmu" as
"enable-method"."
* r8a7743 (RZ/G1M) SoC
- Add node for thermal sensor module with thermal-zone support
* r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
- Add:
+ Renesas Core Match Timer (CMT) support
+ Renesas Timer Pulse Unit PWM Controller (TPU) support
+ Renesas PWM Timer Controller (PWM) support
* r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and
r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms
- Add sound support
* r8a7743 (RZ/G1M), r8a7745 (RZ/G1E) and r8a7792 (R-Car V2H) SoCs
- Allow DTBs of boards of these SoCs to build without any warnings when
compiled with W=1 using gcc-linaro-5.4.1-2017.05
+ Move nodes which have no reg property out of bus, they don't belong there
+ Also sort sub-nodes of root node to allow for easier maintenance
* r8a7790 (R-Car H2), r8a7791 (R-Car M2-W) and r8a7793 (R-Car M2-N) SoCs
- Correct critical CPU temperature
Chris Paterson says "The current R-Car Gen2 device trees define the CPU
critical temperature as 115°C.
The R-Car hardware manuals state that Tc = –40°C to +105°C. The thermal
sensor has an accuracy of ±5°C and there can be a temperature
difference of 1 or 2 degrees between Tjmax and the thermal sensor due
to the location of the latter.
This means that 95°C is a safer value to use.
This value should also apply to r8a7792 but thermal sensor support has
not been added yet."
* r8a7740 (R-Mobile A1) SoC
- Correct TPU register block size
Geert Uytterhoven says "The Timer Pulse Unit has registers that lie
outside the declared register block. Enlarge the register block size to
fix this.
This was probably based on the old platform code, which also assumed a
register block size of 0x100."
* tag 'renesas-dt2-for-v4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (37 commits)
ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core
ARM: dts: iwg22d-sodimm: Sound DMA support via DVC on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via SRC on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via BUSIF on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support on DTS
ARM: dts: iwg22d-sodimm: Sound PIO support
ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec
ARM: dts: r8a7745: Add sound support
ARM: dts: r8a7745: Add audio DMAC support
ARM: dts: r8a7745: Add audio clocks
ARM: dts: r8a7740: Correct TPU register block size
ARM: dts: r8a7743: move timer and thermal-zones nodes out of bus
ARM: dts: r8a7743: sort root sub-nodes alphabetically
ARM: dts: iwg20d-q7-common: Sound DMA support via DVC on DTS
ARM: dts: iwg20d-q7-common: Sound DMA support via SRC on DTS
ARM: dts: iwg20d-q7-common: Sound DMA support via BUSIF on DTS
ARM: dts: iwg20d-q7-common: Sound DMA support on DTS
ARM: dts: iwg20d-q7-common: Sound PIO support
ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
ARM: dts: r8a7792: move timer node out of bus
...
Signed-off-by: Olof Johansson <olof@lixom.net>
* Convert to named i2c-gpio bindings
Geert Uytterhoeven says "Commits 7d29f509d2 ("dt-bindings: i2c:
i2c-gpio: Add support for named gpios") and 05c7477885 ("i2c: gpio:
Add support for named gpios in DT") introduced named i2c-gpio DT
bindings, and deprecated the more error-prone unnamed variant.
This patch series switches all Renesas boards to the new bindings, and
adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly
assumed before..."
... Note that after this series is applied, the i2c-gpio buses are no
longer detected when booting new DTBs on old (v4.14 and older) kernels,
which should not be an issue. Booting old DTBs on new kernels is not
affected."
* Update DTS for CMT DT binding rework
Geert Uytterhoeven says "This patch series updates the CMT device nodes
in the various Renesas DTS files sh_cmt clocksource driver for the recent
DT binding rework that was merged in v4.14-rc1 and v4.15-rc1..."
* Add SMP support to r8a7794 (R-Car E2) SoC
Sergei Shtylyov says "Add the device tree node for the Advanced Power
Management Unit (APMU). Use the "enable-method" prop to point out that
the APMU should be used for the SMP support."
* Correct primary compatible value for eeprom
on r7s72100 (RZ/A1H) genmai and r8a7791 (R-Car M2-W) koelsh boards
Geert Uytterhoeven says "The Renesas part numbers of the two-wire serial
interface EEPROMs do not follow the 24Cxx pattern, but the R1EX24xxx
pattern.
Hence change the primary compatible values to the appropriate variant of
"renesas,r1ex24xxx", like is already done on Gose.""
* Move cec_clock to root node on r8a7791 (R-Car M2-W) koelsh board
r8a7791 (R-Car M2-W) koelsh board
* Use R-Car SDHI and Ether Gen1 and 2 fallback compat strings
Use recently posted R-Car SDHI and Ether Gen 1 and 2 fallback
compat strings in the DT of Renesas ARM based SoCs.
* Add IIC cores to dtsi of r8a7745 (RZ/G1E) SoC
* Rework DT architecture for r8a7745 (RZ/G1E) iW-RainboW-G22D development
platform and add serial support.
Fabrizio Castro says "... define a new DT architecture for the
iW-RainboW-G22D SODIMM Development Platform to include the configuration
with the HDMI daughter board and to define the serial interfaces."
* Add USB function support to
r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
* Add PCIEC and ttySC3 support to r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
* Add VIN support to r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
* Add CAN and HDMI support to r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and
r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms
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Merge tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Renesas ARM Based SoC DT Updates for v4.16" from Simon Horman:
* Convert to named i2c-gpio bindings
Geert Uytterhoeven says "Commits 7d29f509d2 ("dt-bindings: i2c:
i2c-gpio: Add support for named gpios") and 05c7477885 ("i2c: gpio:
Add support for named gpios in DT") introduced named i2c-gpio DT
bindings, and deprecated the more error-prone unnamed variant.
This patch series switches all Renesas boards to the new bindings, and
adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly
assumed before..."
... Note that after this series is applied, the i2c-gpio buses are no
longer detected when booting new DTBs on old (v4.14 and older) kernels,
which should not be an issue. Booting old DTBs on new kernels is not
affected."
* Update DTS for CMT DT binding rework
Geert Uytterhoeven says "This patch series updates the CMT device nodes
in the various Renesas DTS files sh_cmt clocksource driver for the recent
DT binding rework that was merged in v4.14-rc1 and v4.15-rc1..."
* Add SMP support to r8a7794 (R-Car E2) SoC
Sergei Shtylyov says "Add the device tree node for the Advanced Power
Management Unit (APMU). Use the "enable-method" prop to point out that
the APMU should be used for the SMP support."
* Correct primary compatible value for eeprom
on r7s72100 (RZ/A1H) genmai and r8a7791 (R-Car M2-W) koelsh boards
Geert Uytterhoeven says "The Renesas part numbers of the two-wire serial
interface EEPROMs do not follow the 24Cxx pattern, but the R1EX24xxx
pattern.
Hence change the primary compatible values to the appropriate variant of
"renesas,r1ex24xxx", like is already done on Gose.""
* Move cec_clock to root node on r8a7791 (R-Car M2-W) koelsh board
r8a7791 (R-Car M2-W) koelsh board
* Use R-Car SDHI and Ether Gen1 and 2 fallback compat strings
Use recently posted R-Car SDHI and Ether Gen 1 and 2 fallback
compat strings in the DT of Renesas ARM based SoCs.
* Add IIC cores to dtsi of r8a7745 (RZ/G1E) SoC
* Rework DT architecture for r8a7745 (RZ/G1E) iW-RainboW-G22D development
platform and add serial support.
Fabrizio Castro says "... define a new DT architecture for the
iW-RainboW-G22D SODIMM Development Platform to include the configuration
with the HDMI daughter board and to define the serial interfaces."
* Add USB function support to
r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
* Add PCIEC and ttySC3 support to r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
* Add VIN support to r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
* Add CAN and HDMI support to r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and
r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms
* tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (61 commits)
ARM: dts: alt: Convert to named i2c-gpio bindings
ARM: dts: koelsch: Convert to named i2c-gpio bindings
ARM: dts: lager: Convert to named i2c-gpio bindings
ARM: dts: armadillo800eva: Convert to named i2c-gpio bindings
ARM: dts: sh73a0: Remove CMT renesas,channels-mask
ARM: dts: r8a7794: Remove CMT renesas,channels-mask
ARM: dts: r8a7793: Remove CMT renesas,channels-mask
ARM: dts: r8a7791: Remove CMT renesas,channels-mask
ARM: dts: r8a7790: Remove CMT renesas,channels-mask
ARM: dts: r8a7740: Remove CMT renesas,channels-mask
ARM: dts: r8a73a4: Remove CMT renesas,channels-mask
ARM: dts: r8a7794: Update CMT compat strings
ARM: dts: r8a7793: Update CMT compat strings
ARM: dts: r8a7791: Update CMT compat strings
ARM: dts: r8a7790: Update CMT compat strings
ARM: dts: r8a73a4: Update CMT compat string
ARM: dts: r8a7794: Add SMP support
ARM: dts: genmai: Correct primary compatible value for eeprom
ARM: dts: koelsch: Correct primary compatible value for eeprom
ARM: dts: r8a7745: add VIN dt support
...
The R-Car H2 hardware manual states that Tc = –40°C to +105°C. The
thermal sensor has an accuracy of ±5°C and there can be a temperature
difference of 1 or 2 degrees between Tjmax and the thermal sensor due
to the location of the latter.
This means that 95°C is a safer value to use.
Fixes: a8b805f360 ("ARM: dts: r8a7790: enable to use thermal-zone")
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the DTS to remove the now deprecated "renesas,channels-mask"
property.
The channel information is now kept in the device driver and can easily
be determined based on the compat string.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use recently updated R-Car Gen2 CMT0 and CMT1 compat strings.
With this change in place we can keep device-specific configuration in
the driver and the driver can be able to support CMT1 specific features.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use newly added R-Car SDHI Gen2 fallback compat string
in the DT of the r8a7790 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use newly added R-Car Gen2 Ether fallback compat string
in the DT of the r8a7790 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
With the latest dtc, we get many warnings about the missing
'#reset-cells' property in these controllers, e.g.:
arch/arm/boot/dts/r8a7790-lager.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /can@e6e80000:resets[0])
arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/dma-controller@e6700000:resets[0])
arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/ethernet@e6800000:resets[0])
arch/arm/boot/dts/r8a7793-gose.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /gpio@e6050000:resets[0])
arch/arm/boot/dts/r8a7794-alt.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /i2c@e6500000:resets[0])
arch/arm/boot/dts/r8a7794-silk.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /interrupt-controller@e61c0000:resets[0])
This adds it for the three r8a779x chips that were lacking it. The
binding mandates this as <1>, so this is the value I use.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[geert: Add fix for r8a7793.dtsi]
Fixes: 34fbd2b127 ("ARM: dts: r8a7790: Add reset control properties")
Fixes: 6e11a322f1 ("ARM: dts: r8a7792: Add reset control properties")
Fixes: 84fb19e1d2 ("ARM: dts: r8a7793: Add reset control properties")
Fixes: 615beb759c ("ARM: dts: r8a7794: Add reset control properties")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Currently only the CPU cores in the CA15 cluster have clocks properties.
Add the missing clocks properties for the CPU cores in the CA7 cluster
to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU cores are driven by the same clock.
Add the missing clocks properties to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7790 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
The following 'capacity-dmips-mhz' dt property values are used:
Cortex-A15: 1024, Cortex-A7: 539
They have been derived form the cpu_efficiency values:
Cortex-A15: 3891, Cortex-A7: 2048
by scaling them so that the Cortex-A15s (big cores) use 1024.
The cpu_efficiency values were originally derived from the "Big.LITTLE
Processing with ARM Cortex™-A15 & Cortex-A7" white paper
(http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x
(3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the
Dhrystone benchmark.
The following platform is affected once cpu-invariant accounting
support is re-connected to the task scheduler:
r8a7790-lager
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use the preferred generic node name instead of the specific name.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that resets usually match the corresponding module clocks.
Exceptions are:
- The audio module has resets for the Serial Sound Interfaces only,
- The display module has only a single reset for all DU channels, but
adding reset properties for the display is postponed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The current practice is to not group clocks under a "clocks" subnode,
but just put them together with the other on-SoC devices.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Convert the R-Car H2 SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use newly added R-Car SATA Gen2 fallback compat string
in the DT of the r8a7790 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before the fallback compat string is considered.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a7790 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7790 and the
fallback binding for R-Car Gen 2
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reserve SRAM for the jump stub for CPU core bringup.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
R-Car H2 has 2 regions of Inter Connect RAM (72 + 4 KiB).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The bogus 'device_type = "pci"' confuses dtc, causing lots of totally
unrelated warnings. After fixing that, real warnings like
arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Node /pci@ee090000/usb@0,1 PCI unit address format error, expected "1,0"
are left. Correct the unit-addresses and reg properties of the subnodes
to fix these.
Signed-off-by: Rob Herring <robh@kernel.org>
[geert: Improve description]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The device trees for Renesas SoCs use either pfc or pin-controller as the
node name for the PFC device. This patch is intended to take a step towards
unifying the node name used as pin-controller which appears to be the more
generic of the two and thus more in keeping with the DT specs.
My analysis is that this is a user-visible change to the extent that kernel
logs, and sysfs entries change from e6060000.pfc and pfc@e6060000 to
e6060000.pin-controller and pin-controller@e6060000.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: bcde372254 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1.
Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0.
Because of this, current platform board (using SRC/DVC/SSI)
Playback/Capture both will use same Audio-DMAC0
(but it depends on data path).
First note is that this "rx" and "tx" are from each IP point,
it doesn't mean Playback/Capture.
Second note is that Audio DMAC assigned on DT is only for
Audio-DMAC, Audio-DMAC-peri-peri has no entry.
=> Audio-DMAC
-> Audio-DMAC-peri-peri
-- HW connection
Playback case
[Mem] => [SRC]--[DVC] -> [SSI]--[Codec]
rx ~~~~~~~~~~~~
Capture
[Mem] <= [DVC]--[SRC] <- [SSI]--[Codec]
tx ~~~~~~~~~~~~
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Cortex-A15/A7 cache controllers are integrated controllers, and thus
the device nodes representing them should not have unit-addresses or reg
properties.
Fixes: 2c3de36700 ("ARM: dts: r8a7790: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.
Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).
In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Use recently added R-Car Gen 2 fallback binding for msiof nodes in
DT for r8a7790 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7790 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Use recently added R-Car Gen 2 fallback binding for iic nodes in
DT for r8a7790 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7790 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Use recently added R-Car Gen 2 fallback binding for i2c nodes in
DT for r8a7790 SoC.
This has no run-time effect for the current driver as the initialisation
sequence is the same for the SoC-specific binding for r8a7790 and the
fallback binding for R-Car Gen 2.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda