* Added extra regs for A15 VGIC
* Added A15 architected timer node
* Split A5 and A9 TWD nodes into two separate ones for timer
and watchdog; interrupt definitions fixed on the way
* Fixed typo in A5 GIC compatible value
All the changes courtesy of Marc Zyngier.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This patch adds Device Tree file for the CoreTile Express A15x2
(V2P-CA15) with Test Chip 1.
As the chip's GIC has 160 interrupt inputs and equivalent SMM
(FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
increased.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
