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20 Commits (f9c75bca44d4754456cba7d3b4f0e15518177b0e)

Author SHA1 Message Date
Yangtao Li f9c75bca44 irqchhip: Convert to using %pOFn instead of device_node.name
In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-12-13 09:35:56 +00:00
Thomas Gleixner 20b420dc42 irqchip updates for 4.19, take #2
- bcm7038: compilation fix for !SMP
 - stm32: fix teardown on probe error
 - s3c24xx: fix compilation warning
 - renesas-irqc: r8a774a1 support
 - tango: chained irq setup simplification
 - gic-v3: allow wake-up sources
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAluAC8YVHG1hcmMuenlu
 Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDsvgP/1LWT1TS/mnxhfo71yueEI75X3Ju
 ZKQ8Za5o6nbu2CvwedEOtPVfAqp5Mg3wNJZKiN4H0db3dxftzqqp7ZQ1P7ZtheZC
 69k0DKXQKN2BXURX3zDHhYA86kjrRcUEJfjF8Wi8Pe1UjrO4lm7fQZEVg9SiSigx
 TxFOakeSlHZqrC0DwEj5P7RpyAQhqb/7ygg9TNjlNgda8F98RmUNm38nEUj+IbPK
 UySYnHTe02Z5nD/9K+piB8gFgpTIfQlhWPA/kgODlsCJUuUY18RkB0CZzRuUBv3a
 58qqpopuvH1jEVqWi3ffXr6m1kPF7Ys8GACC0laH2QgArT5OSGet9Hn7Edo5qh1p
 UPdvJEpuIsgQc1nPEcw84h1SGYg2lEtY0ZR4FdDnh3QQ45Kbkhx0HWLM/14YU/wI
 jutiUAZ7BstdlRwzmjNWwcW2pjhE3/FDBUTifQb/qvh4MEM9Mi4Jr3XARSTuW8o5
 zZXmm47sOomuDl8RyIKvPuQRhmnN0ix86dba0bMIMYx2G9dRjb51o9gfN1nY/E6C
 bWayUZNmSaMAPi+xXBSw+O9mIqg2mwlLzq4EIKMHRUyMBqNL3mFIaefgT5yOLgMG
 98Co+VLgpnp7eraAmHJWLrdf4QhiMD+cHkOD41s5eu0E+BGKLWS/cZdROa4jvucs
 1JzPGTd0o4PHd5vV
 =Mr5O
 -----END PGP SIGNATURE-----

Merge tag 'irqchip-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip updates for 4.19, take #2 from Marc Zyngier:

 - bcm7038: compilation fix for !SMP
 - stm32: fix teardown on probe error
 - s3c24xx: fix compilation warning
 - renesas-irqc: r8a774a1 support
 - tango: chained irq setup simplification
 - gic-v3: allow wake-up sources
2018-08-24 16:06:42 +02:00
Dan Carpenter 4096165d55 irqchip/stm32: Fix init error handling
If there are any errors in stm32_exti_host_init() then it leads to a
NULL dereference in the callers.  The function should clean up after
itself.

Fixes: f9fc174550 ("irqchip/stm32: Add host and driver data structures")
Reviewed-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-08-13 09:03:44 +01:00
Ludovic Barre 6bdd0299cf irqchip/stm32: Add exti0 translation for stm32mp1
This patch fixes a datasheet issue, in the draft version the "exti0"
was not connected whereas is it.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-07-19 16:12:27 +01:00
Arnd Bergmann a84277bf3e irqchip/stm32: Fix non-SMP build warning
A CONFIG_SMP=n build emits a harmless compile-time warning:

drivers/irqchip/irq-stm32-exti.c:495:12: error: 'stm32_exti_h_set_affinity' defined but not used [-Werror=unused-function]

The #ifdef is inconsistent here, and it's better to use an IS_ENABLED() check
that lets the compiler silently drop that function.

Fixes: 927abfc446 ("irqchip/stm32: Add stm32mp1 support with hierarchy domain")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ludovic Barre <ludovic.barre@st.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Link: https://lkml.kernel.org/r/20180605114347.1347128-1-arnd@arndb.de
2018-06-06 12:05:19 +02:00
Ludovic Barre 73958b31c1 irqchip/stm32: Add suspend/resume support for hierarchy domain
This patch adds suspend/resume feature for exti hierarchy domain.
-suspend function sets wake_active into imr of each banks
-resume function restores the mask_cache interrupt into
 imr of each banks

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:22 +01:00
Ludovic Barre 927abfc446 irqchip/stm32: Add stm32mp1 support with hierarchy domain
Exti controller has been differently integrated on stm32mp1 SoC.
A parent irq has only one external interrupt. A hierachy domain could
be used. Handlers are call by parent, each parent interrupt could be
masked and unmasked according to the needs.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:22 +01:00
Ludovic Barre 5a2490e029 irqchip/stm32: Prepare common functions
This patch prepares functions which could be reused by
next variant of stm32 exti controller.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:21 +01:00
Ludovic Barre f9fc174550 irqchip/stm32: Add host and driver data structures
This patch adds host and driver data structures to support
different stm32 exti controllers with variants.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:21 +01:00
Ludovic Barre d9e2b19b02 irqchip/stm32: Add suspend support
This patch adds suspend feature.
-Use default irq_set_wake function to store wakeup request.
-Suspend function set wake_active into imr of each bank
 and save rising/falling trigger registers.
-Resume function restore the mask_cache interrupt into
 imr of each bank and restore rising/falling trigger registers.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:20 +01:00
Ludovic Barre be6230f0c2 irqchip/stm32: Add falling pending register support
This patch adds support of rising/falling pending registers.
Falling pending register (fpr) is needed for next revision.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:20 +01:00
Ludovic Barre ea80aa2a1a irqchip/stm32: Checkpatch fix
-WARNING: struct irq_domain_ops should normally be const
-CHECK: Alignment should match open parenthesis

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:38:20 +01:00
Radoslaw Pietrzyk ff78716d43 irqchip/stm32: Optimizes and cleans up stm32-exti irq_domain
- In stm32_exti_alloc function, discards irq_domain_set_info
  with handle_simple_irq. This overwrite the setting defined while init
  of generic chips. Exti controller manages edge irq type.
- Removes acking in chained irq handler as this is done by
  irq_chip itself inside handle_edge_irq
- removes unneeded irq_domain_ops.xlate callback

Acked-by: Ludovic Barre <ludovic.barre@st.com>
Tested-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24 12:37:54 +01:00
Benjamin Gaignard 8de50dc262 irqchip/stm32: Fix copyright
Uniformize STMicroelectronics copyrights header and add SPDX identifier

CC: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20171130084500.23439-1-benjamin.gaignard@st.com
2018-01-29 16:24:53 +01:00
Ludovic Barre 90af7c254f irqchip/stm32: Move the wakeup on interrupt mask
Move irq_set_wake on interrupt mask, needed to wake up from
low power mode as the event mask is not able to do so.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:43 +00:00
Ludovic Barre 2ca6b9bcaa irqchip/stm32: Fix initial values
-After cold boot, imr default value depends on hardware configuration.
-After hot reboot the registers must be cleared to avoid residue.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:35 +00:00
Ludovic Barre 539c603e14 irqchip/stm32: Add stm32h7 support
stm32h7 has up to 96 inputs
(3 banks of 32 inputs max).

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:28 +00:00
Ludovic Barre 6dd64ee17e irqchip/stm32: Add multi-bank management
-Prepare to manage multi-bank of external interrupts
(N banks of 32 inputs).
-Prepare to manage registers offsets by compatible
(registers offsets could be different follow per stm32 platform).

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07 11:44:06 +00:00
Rob Herring e81f54c668 irqchip: Convert to using %pOF instead of full_name
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Lee Jones <lee@kernel.org>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-tegra@vger.kernel.org
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-08-23 10:09:28 +01:00
Alexandre TORGUE e072041688 drivers/irqchip: Add STM32 external interrupts support
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.

Each line can be independently configured as interrupt or wake-up source,
and triggers either on rising, falling or both edges. Each line can also
be masked independently.

Originally-from: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: arnd@arndb.de
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: bruherrera@gmail.com
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: lee.jones@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1474387259-18926-3-git-send-email-alexandre.torgue@st.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-09-21 14:13:21 +02:00