Mark each interface clock with a corresponding CM_AUTOIDLE bit with
a clkops that has the allow_idle/deny_idle function pointers populated.
This allows the OMAP clock framework to enable and disable autoidle for
these clocks.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
clock34xx_data.c now contains data for the OMAP34xx family, the
OMAP36xx family, and the OMAP3517 family, so rename it to
clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the
chip family-specific clock functions to clock34xx.c, clock36xx.c, or
clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3
superset.
The main goal here is to prepare to compile chip family-specific clock
functions only for kernel builds that target that chip family. To get to
that point, we also need to add CONFIG_SOC_* options for those other
chip families; that will be done in future patches, planned for 2.6.35.
OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL
clkops structure. The OMAP4 variant of this clkops structure has been
removed, and since there was nothing else currently in clock44xx.c, it
too has been removed -- it can always be added back later when there
is some content for it. (The OMAP4 clock autogeneration scripts have been
updated accordingly.)
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ranjith Lohithakshan <ranjithl@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
This patch implements a workaround for the DPLL HS divider limitation
in OMAP3630 as given by Errata ID: i556.
Errata:
When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx).
The reset value gets loaded instead of the previous value.
The following HSDIVIDERs exhibit above behavior:
. DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits)
. DPLL3 : M3 (CM_CLKEN_PLL[12] register bit).
Work Around:
It is mandatory to apply the following sequence to ensure the write
value will
be loaded in DPLL HSDIVIDER FSM:
The global sequence when using PWRDN bit is the following:
. Disable Mx HSDIVIDER clock output related functional clock enable bits
(in CM_FCLKEN_xxx / CM_ICLKEN_xxx)
. Enable PWRDN bit of HSDIVIDER
. Disable PWRDN bit of HSDIVIDER
. Read current HSDIVIDER register value
. Write different value in HSDIVIDER register
. Write expected value in HSDIVIDER register
. Enable Mx HSDIVIDER clock output related functional clocks
(CM_FCLKEN_xxx / CM_ICLKEN_xxx)
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Vijaykumar GN <vijaykumar.gn@ti.com>
[paul@pwsan.com: updated patch to apply; made workaround function static;
marked as being 36xx-specific]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch adds clock support for the following AM35xx modules
- Ethernet MAC
- CAN Controller (HECC)
- New MUSB OTG Controller with integrated Phy
- Video Processing Front End (VPFE)
- Additional UART (UART4)
Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Rename clkops_noncore_dpll_ops for omap3 and omap4.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rename the omap2_clk_init() in the OMAP2, 3, and 4 clock code to be
omap2xxx_clk_init(), omap3xxx_clk_init(), etc. Remove all traces of
the (commented) old virt_prcm_set code from omap3xxx_clk_init() and
omap4xxx_clk_init(), since this will be handled with the OPP code that
is cooking in the PM branch.
After this patch, there should be very little else in the clock code
that blocks a multi-OMAP 2+3 kernel. (OMAP2420+OMAP2430 still has some
outstanding issues that need to be resolved; this is pending on some
additions to the hwmod data.)
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch moves all the dpll control api's to a
common file dpll.c. This is in preperation of omap4
support wherein most of these api's can be reused.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
The OMAP3 clock code currently #includes a large .h file full of static
data structures. Instead, define the data in a .c file.
Russell King <linux@arm.linux.org.uk> proposed this new arrangement:
http://marc.info/?l=linux-omap&m=125967425908895&w=2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Russell King <linux@arm.linux.org.uk>
Current calculation does not take into account any changes to M2 divisor, and
thus when we change VDD2 OPP, dpll3_m2x2 rate does not change. Fixed by
re-routing dpll3_m2x2 parent to dpll3_m2.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Move the remaining headers under plat-omap/include/mach
to plat-omap/include/plat. Also search and replace the
files using these headers to include using the right path.
This was done with:
#!/bin/bash
mach_dir_old="arch/arm/plat-omap/include/mach"
plat_dir_new="arch/arm/plat-omap/include/plat"
headers=$(cd $mach_dir_old && ls *.h)
omap_dirs="arch/arm/*omap*/ \
drivers/video/omap \
sound/soc/omap"
other_files="drivers/leds/leds-ams-delta.c \
drivers/mfd/menelaus.c \
drivers/mfd/twl4030-core.c \
drivers/mtd/nand/ams-delta.c"
for header in $headers; do
old="#include <mach\/$header"
new="#include <plat\/$header"
for dir in $omap_dirs; do
find $dir -type f -name \*.[chS] | \
xargs sed -i "s/$old/$new/"
done
find drivers/ -type f -name \*omap*.[chS] | \
xargs sed -i "s/$old/$new/"
for file in $other_files; do
sed -i "s/$old/$new/" $file
done
done
for header in $(ls $mach_dir_old/*.h); do
git mv $header $plat_dir_new/
done
Signed-off-by: Tony Lindgren <tony@atomide.com>
omap2_init_clk_clkdm() is called as part of the chip architecture-specific
initialization code, so calling it again from the struct clk init pointer
just wastes cycles.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
All MPU-related clocks should be in the mpu_clkdm. This is needed for the
upcoming omap_hwmod patches, which needs to know the clockdomain that arm_fck
is in.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework
and ensure that auto-idle bits are set for these clocks during PRCM
init.
Also add omap3_d2d_idle() function called durint PRCM setup which
ensures D2D pins are MUX'd correctly to enable retention for
standalone (no-modem) devices.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
GPIO de-bounce clocks don't have any impact on the module idle state, so
the clock code should not wait for the module to enable after the de-bounce
clocks are enabled.
Problem found by Kevin Hilman <khilman@deeprootsystems.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
This patch avoids waiting for the camera module to become ready,
since it doesn't have IDLEST bit.
Based on a earlier hack done by Paul Walmsley on Sep 9 2008 on
linux-omap tree.
Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce
introduces a way to "dry run" clock changes before they're committed.
However, this involves putting logic to handle this into each and
every recalc function, and unfortunately due to the caching, led to
some bugs.
Solve both of issues by making the recalc methods always return the
clock rate for the clock, which the caller decides what to do with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Traditionally, we've tracked the parent/child relationships between
clk structures by setting the child's parent member to point at the
upstream clock. As a result, when decending the tree, we have had
to scan all clocks to find the children.
Avoid this wasteful scanning by keeping a list of the clock's children.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the omap3_core_dpll_m2_set_rate() function to the OMAP3 clock code,
which calls into the SRAM function omap3_sram_configure_core_dpll() to
change the CORE DPLL M2 divider. (SRAM code is necessary since rate changes
on clocks upstream from the SDRC can glitch SDRAM accesses.)
Use this function for the set_rate function pointer in the dpll3_m2_ck
struct clk. With this function in place, PM/OPP code should be able to
alter SDRAM speed via code similar to:
clk_set_rate(&dpll3_m2_ck, target_rate).
linux-omap source commit is 7f8b2b0f4fe52238c67d79dedcd2794dcef4dddd.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The DPLL FREQSEL jitter correction bits are set based on a table in
the 34xx TRM, Table 4-38, according to the DPLL's internal clock
frequency "Fint." Several Fint frequency ranges are missing from this
table. Previously, we allowed these Fint frequency ranges to be
selected in the rate rounding code, but did not change the FREQSEL bits.
Correspondence with the OMAP hardware team indicates that Fint values
not in the table should not be used. So, prevent them from being
selected during DPLL rate rounding. This removes warnings and also
can prevent the chip from locking up.
The first pass through the rate rounding code will update the DPLL max
and min dividers appropriately, so later rate rounding passes will run
faster than the first.
Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several
test cycles of this patch - thanks Peter.
linux-omap source commit is f9c1b82f55b60fc39eaa6e7aa1fbe380c0ffe2e9.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Peter de Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Convert struct dpll_data.idlest_bit field to idlest_mask. Needed since
OMAP2 uses two bits for DPLL IDLEST rather than one.
While here, add the missing idlest_* fields for DPLL3.
linux-omap source commits are 25bab0f176b0a97be18a1b38153f266c3a155784
and b0f7fd17db2aaf8e6e9a2732ae3f4de0874db01c.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
into the OMAP3 clock framework.
linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and
clockdomain; so, create powerdomain and clockdomain structures for them.
Mark each DPLL clock as belonging to their respective DPLL clockdomain.
cf. 34xx TRM Table 4-27 (among other references).
linux-omap source commits are acdb615850b9b4f7d1ab68133a16be8c8c0e7419 and
a8798a48f33e9268dcc7f30a4b4a3ce4220fe0c9.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
sys_clkout2 belongs in the core_clkdm (3430 TRM section 4.7.2.2).
It's not clear whether it actually is in the CORE clockdomain, or whether
it is technically in a different clockdomain; but this is closer to
reality than the present configuration.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Filling the set_rate and round_rate fields of dpll4_m4_ck makes
this clock programmable through clk_set_rate(). This is needed
to give omapfb control over the dss1_alwon_fck rate.
This patch includes a fix from Tomi Valkeinen <tomi.valkeinen@nokia.com>.
linux-omap source commits are e42218d45afbc3e654e289e021e6b80c657b16c2 and
9d211b761b3cdf7736602ecf7e68f8a298c13278.
Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add CSI2 clock struct for handling it with clock API when TI PM is disabled.
linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432.
Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The GFX/SGX functional and interface clocks have different masks, for
some unknown reason, so split EN_SGX_SHIFT into one each for fclk and
iclk.
Correct according to the TRM and the far more important 'does this
actually work at all?' metric.
linux-omap source commit is de1121fdb899f762b9e717f44eaf3fae7c00cd3e.
Signed-off-by: Daniel Stone <daniel.stone@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix some bugs in the OMAP3 clock tree pertaining to the 96MHz clocks.
The 96MHz portion of the clock tree should now have reasonable
fidelity to the 34xx TRM Rev I.
One remaining question mark: it's not clear exactly which 96MHz source
clock the USIM uses. This patch sticks with the previous setting, which
seems reasonable.
linux-omap source commit is 15c706e8179ce238c3ba70a25846a36b73bd2359.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove usbhost_sar_fclk from the OMAP3 clock framework. The bit that
the clock was tweaking doesn't actually enable or disable a clock; it
controls whether the hardware will save and restore USBHOST state
when the powerdomain changes state. (That happens to coincidentally
enable a clock for the duration of the operation, hence the earlier
confusion.)
In place of the clock, mark the USBHOST powerdomain as supporting
hardware save-and-restore functionality.
linux-omap source commit is f3ceac86a9d425d101d606d87a5af44afef27179.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add non-CORE DPLL rate set code and M,N programming for OMAP3.
Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework.
You may see some warnings on rate sets from the freqsel code. The
table that TI presented in the 3430 TRM Rev F does not cover Fint <
750000, which definitely occurs in practice. However, the lack of this
freqsel case does not appear to impair the DPLL rate change.
linux-omap source commit is 689fe67c6d1ad8f52f7f7b139a3274b79bf3e784.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
propagate_rate() is recursive, so it makes sense to minimise the
amount of stack which is used for each recursion. So, rather than
recursing back into it from the ->recalc functions if RATE_PROPAGATES
is set, do that test at the higher level.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than employing run-time tests in omap2_clk_wait_ready() to
decide whether we need to wait for the clock to become ready, we
can set the .ops appropriately.
This change deals with the OMAP24xx and OMAP34xx conditionals only.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PARENT_CONTROLS_CLOCK just makes enable/disable no-op, and is
functionally an alias for ALWAYS_ENABLED. This can be handled
in the same way, using clkops_null.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
... and use it for clocks which are ALWAYS_ENABLED. These clocks
use a non-NULL enable_reg pointer for other purposes (such as
selecting clock rates.)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Collect up all the common enable/disable clock operation functions
into a separate operations structure.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This will simplify the MMC low-level init, and make it more
flexible to add support for a newer MMC controller in the
following patches.
The patch rearranges platform data and gets rid of slot vs
controller confusion in the old data structures. Also fix
device id numbering in the clock code.
Some code snippets are based on an earlier patch by
Russell King <linux@arm.linux.org.uk>.
Cc: Pierre Ossman <drzeus-mmc@drzeus.cx>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch changes gpio "driver" to enable debounce clock for
gpio-bank only when debounce is enabled for some gpio in that bank.
Gpio functional clocks are also renamed in clock tree, gpioX_fck ->
gpioX_dbck.
This patch triggers problem with gpio wake-up and Omap3. Gpios in PER
domain aren't capable to generate wake-up if PER domain is in sleep
state. For this iopad wake-up should be used and needed pad
configuration should be done. Enabling iopad wake-up for gpio pads is
left for bootloader or omap mux configuration in kernel.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
E.g dss_l3_ick and dss_l4_ick have same gating control. Having own
clock for both of them causes race condition between enable / disable.
This patch combines this kind of clocks and names new clock as <module>_ick.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch integrates the OMAP3 clock tree with the clockdomain code.
This patch:
- marks OMAP34xx clocks with their corresponding clockdomain.
- adds code to convert the clockdomain name to a clockdomain pointer in the
struct clk during clk_register().
- modifies OMAP2 clock usecounting to call into the clockdomain code
when clocks are enabled or disabled.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for DPLL autoidle control to the OMAP3 clock
framework. These functions will be used by the noncore DPLL enable
and disable code - this is because, according to the CDP code, the
DPLL autoidle status must be saved and restored across DPLL
lock/bypass/off transitions.
N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather
than just two. This code currently does not support the third option,
low-power bypass autoidle.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for mach-omap2 based on current
mcbsp platform driver.
Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Paul Walmsley