/* * TI DaVinci DM365 EVM board support * * Copyright (C) 2009 Texas Instruments Incorporated * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 #define DM365_EVM_PHY_MASK (0x2) #define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ /* NOTE: this is geared for the standard config, with a socketed * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you * swap chips with a different block size, partitioning will * need to be changed. This NAND chip MT29F16G08FAA is the default * NAND shipped with the Spectrum Digital DM365 EVM */ #define NAND_BLOCK_SIZE SZ_128K static struct mtd_partition davinci_nand_partitions[] = { { /* UBL (a few copies) plus U-Boot */ .name = "bootloader", .offset = 0, .size = 28 * NAND_BLOCK_SIZE, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { /* U-Boot environment */ .name = "params", .offset = MTDPART_OFS_APPEND, .size = 2 * NAND_BLOCK_SIZE, .mask_flags = 0, }, { .name = "kernel", .offset = MTDPART_OFS_APPEND, .size = SZ_4M, .mask_flags = 0, }, { .name = "filesystem1", .offset = MTDPART_OFS_APPEND, .size = SZ_512M, .mask_flags = 0, }, { .name = "filesystem2", .offset = MTDPART_OFS_APPEND, .size = MTDPART_SIZ_FULL, .mask_flags = 0, } /* two blocks with bad block table (and mirror) at the end */ }; static struct davinci_nand_pdata davinci_nand_data = { .mask_chipsel = BIT(14), .parts = davinci_nand_partitions, .nr_parts = ARRAY_SIZE(davinci_nand_partitions), .ecc_mode = NAND_ECC_HW, .options = NAND_USE_FLASH_BBT, }; static struct resource davinci_nand_resources[] = { { .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, .flags = IORESOURCE_MEM, }, { .start = DM365_ASYNC_EMIF_CONTROL_BASE, .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; static struct platform_device davinci_nand_device = { .name = "davinci_nand", .id = 0, .num_resources = ARRAY_SIZE(davinci_nand_resources), .resource = davinci_nand_resources, .dev = { .platform_data = &davinci_nand_data, }, }; static struct at24_platform_data eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, .flags = AT24_FLAG_ADDR16, .setup = davinci_get_mac_addr, .context = (void *)0x7f00, }; static struct i2c_board_info i2c_info[] = { { I2C_BOARD_INFO("24c256", 0x50), .platform_data = &eeprom_info, }, }; static struct davinci_i2c_platform_data i2c_pdata = { .bus_freq = 400 /* kHz */, .bus_delay = 0 /* usec */, }; static struct davinci_mmc_config dm365evm_mmc_config = { .wires = 4, .max_freq = 50000000, .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, .version = MMC_CTLR_VERSION_2, }; static void dm365evm_emac_configure(void) { /* * EMAC pins are multiplexed with GPIO and UART * Further details are available at the DM365 ARM * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 */ davinci_cfg_reg(DM365_EMAC_TX_EN); davinci_cfg_reg(DM365_EMAC_TX_CLK); davinci_cfg_reg(DM365_EMAC_COL); davinci_cfg_reg(DM365_EMAC_TXD3); davinci_cfg_reg(DM365_EMAC_TXD2); davinci_cfg_reg(DM365_EMAC_TXD1); davinci_cfg_reg(DM365_EMAC_TXD0); davinci_cfg_reg(DM365_EMAC_RXD3); davinci_cfg_reg(DM365_EMAC_RXD2); davinci_cfg_reg(DM365_EMAC_RXD1); davinci_cfg_reg(DM365_EMAC_RXD0); davinci_cfg_reg(DM365_EMAC_RX_CLK); davinci_cfg_reg(DM365_EMAC_RX_DV); davinci_cfg_reg(DM365_EMAC_RX_ER); davinci_cfg_reg(DM365_EMAC_CRS); davinci_cfg_reg(DM365_EMAC_MDIO); davinci_cfg_reg(DM365_EMAC_MDCLK); /* * EMAC interrupts are multiplexed with GPIO interrupts * Details are available at the DM365 ARM * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 */ davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); } static void dm365evm_mmc_configure(void) { /* * MMC/SD pins are multiplexed with GPIO and EMIF * Further details are available at the DM365 ARM * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 */ davinci_cfg_reg(DM365_SD1_CLK); davinci_cfg_reg(DM365_SD1_CMD); davinci_cfg_reg(DM365_SD1_DATA3); davinci_cfg_reg(DM365_SD1_DATA2); davinci_cfg_reg(DM365_SD1_DATA1); davinci_cfg_reg(DM365_SD1_DATA0); } static void __init evm_init_i2c(void) { davinci_init_i2c(&i2c_pdata); i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); } static struct platform_device *dm365_evm_devices[] __initdata = { &davinci_nand_device, }; static struct davinci_uart_config uart_config __initdata = { .enabled_uarts = (1 << 0), }; static void __init dm365_evm_map_io(void) { dm365_init(); } static __init void dm365_evm_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; platform_add_devices(dm365_evm_devices, ARRAY_SIZE(dm365_evm_devices)); evm_init_i2c(); davinci_serial_init(&uart_config); dm365evm_emac_configure(); dm365evm_mmc_configure(); davinci_setup_mmc(0, &dm365evm_mmc_config); davinci_setup_mmc(1, &dm365evm_mmc_config); soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY; } static __init void dm365_evm_irq_init(void) { davinci_irq_init(); } MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (0x80000100), .map_io = dm365_evm_map_io, .init_irq = dm365_evm_irq_init, .timer = &davinci_timer, .init_machine = dm365_evm_init, MACHINE_END